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0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028 
0029 #include <linux/acpi.h>
0030 #include <linux/pci.h>
0031 #include <linux/slab.h>
0032 
0033 #include <drm/drm_device.h>
0034 
0035 #include "atom.h"
0036 #include "radeon.h"
0037 #include "radeon_reg.h"
0038 
0039 /*
0040  * BIOS.
0041  */
0042 
0043 /* If you boot an IGP board with a discrete card as the primary,
0044  * the IGP rom is not accessible via the rom bar as the IGP rom is
0045  * part of the system bios.  On boot, the system bios puts a
0046  * copy of the igp rom at the start of vram if a discrete card is
0047  * present.
0048  */
0049 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
0050 {
0051     uint8_t __iomem *bios;
0052     resource_size_t vram_base;
0053     resource_size_t size = 256 * 1024; /* ??? */
0054 
0055     if (!(rdev->flags & RADEON_IS_IGP))
0056         if (!radeon_card_posted(rdev))
0057             return false;
0058 
0059     rdev->bios = NULL;
0060     vram_base = pci_resource_start(rdev->pdev, 0);
0061     bios = ioremap(vram_base, size);
0062     if (!bios) {
0063         return false;
0064     }
0065 
0066     if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
0067         iounmap(bios);
0068         return false;
0069     }
0070     rdev->bios = kmalloc(size, GFP_KERNEL);
0071     if (rdev->bios == NULL) {
0072         iounmap(bios);
0073         return false;
0074     }
0075     memcpy_fromio(rdev->bios, bios, size);
0076     iounmap(bios);
0077     return true;
0078 }
0079 
0080 static bool radeon_read_bios(struct radeon_device *rdev)
0081 {
0082     uint8_t __iomem *bios, val1, val2;
0083     size_t size;
0084 
0085     rdev->bios = NULL;
0086     /* XXX: some cards may return 0 for rom size? ddx has a workaround */
0087     bios = pci_map_rom(rdev->pdev, &size);
0088     if (!bios) {
0089         return false;
0090     }
0091 
0092     val1 = readb(&bios[0]);
0093     val2 = readb(&bios[1]);
0094 
0095     if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
0096         pci_unmap_rom(rdev->pdev, bios);
0097         return false;
0098     }
0099     rdev->bios = kzalloc(size, GFP_KERNEL);
0100     if (rdev->bios == NULL) {
0101         pci_unmap_rom(rdev->pdev, bios);
0102         return false;
0103     }
0104     memcpy_fromio(rdev->bios, bios, size);
0105     pci_unmap_rom(rdev->pdev, bios);
0106     return true;
0107 }
0108 
0109 static bool radeon_read_platform_bios(struct radeon_device *rdev)
0110 {
0111     phys_addr_t rom = rdev->pdev->rom;
0112     size_t romlen = rdev->pdev->romlen;
0113     void __iomem *bios;
0114 
0115     rdev->bios = NULL;
0116 
0117     if (!rom || romlen == 0)
0118         return false;
0119 
0120     rdev->bios = kzalloc(romlen, GFP_KERNEL);
0121     if (!rdev->bios)
0122         return false;
0123 
0124     bios = ioremap(rom, romlen);
0125     if (!bios)
0126         goto free_bios;
0127 
0128     memcpy_fromio(rdev->bios, bios, romlen);
0129     iounmap(bios);
0130 
0131     if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa)
0132         goto free_bios;
0133 
0134     return true;
0135 free_bios:
0136     kfree(rdev->bios);
0137     return false;
0138 }
0139 
0140 #ifdef CONFIG_ACPI
0141 /* ATRM is used to get the BIOS on the discrete cards in
0142  * dual-gpu systems.
0143  */
0144 /* retrieve the ROM in 4k blocks */
0145 #define ATRM_BIOS_PAGE 4096
0146 /**
0147  * radeon_atrm_call - fetch a chunk of the vbios
0148  *
0149  * @atrm_handle: acpi ATRM handle
0150  * @bios: vbios image pointer
0151  * @offset: offset of vbios image data to fetch
0152  * @len: length of vbios image data to fetch
0153  *
0154  * Executes ATRM to fetch a chunk of the discrete
0155  * vbios image on PX systems (all asics).
0156  * Returns the length of the buffer fetched.
0157  */
0158 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
0159                 int offset, int len)
0160 {
0161     acpi_status status;
0162     union acpi_object atrm_arg_elements[2], *obj;
0163     struct acpi_object_list atrm_arg;
0164     struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
0165 
0166     atrm_arg.count = 2;
0167     atrm_arg.pointer = &atrm_arg_elements[0];
0168 
0169     atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
0170     atrm_arg_elements[0].integer.value = offset;
0171 
0172     atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
0173     atrm_arg_elements[1].integer.value = len;
0174 
0175     status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
0176     if (ACPI_FAILURE(status)) {
0177         printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
0178         return -ENODEV;
0179     }
0180 
0181     obj = (union acpi_object *)buffer.pointer;
0182     memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
0183     len = obj->buffer.length;
0184     kfree(buffer.pointer);
0185     return len;
0186 }
0187 
0188 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
0189 {
0190     int ret;
0191     int size = 256 * 1024;
0192     int i;
0193     struct pci_dev *pdev = NULL;
0194     acpi_handle dhandle, atrm_handle;
0195     acpi_status status;
0196     bool found = false;
0197 
0198     /* ATRM is for the discrete card only */
0199     if (rdev->flags & RADEON_IS_IGP)
0200         return false;
0201 
0202     while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
0203         dhandle = ACPI_HANDLE(&pdev->dev);
0204         if (!dhandle)
0205             continue;
0206 
0207         status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
0208         if (ACPI_SUCCESS(status)) {
0209             found = true;
0210             break;
0211         }
0212     }
0213 
0214     if (!found) {
0215         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
0216             dhandle = ACPI_HANDLE(&pdev->dev);
0217             if (!dhandle)
0218                 continue;
0219 
0220             status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
0221             if (ACPI_SUCCESS(status)) {
0222                 found = true;
0223                 break;
0224             }
0225         }
0226     }
0227 
0228     if (!found)
0229         return false;
0230 
0231     rdev->bios = kmalloc(size, GFP_KERNEL);
0232     if (!rdev->bios) {
0233         DRM_ERROR("Unable to allocate bios\n");
0234         return false;
0235     }
0236 
0237     for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
0238         ret = radeon_atrm_call(atrm_handle,
0239                        rdev->bios,
0240                        (i * ATRM_BIOS_PAGE),
0241                        ATRM_BIOS_PAGE);
0242         if (ret < ATRM_BIOS_PAGE)
0243             break;
0244     }
0245 
0246     if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
0247         kfree(rdev->bios);
0248         return false;
0249     }
0250     return true;
0251 }
0252 #else
0253 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
0254 {
0255     return false;
0256 }
0257 #endif
0258 
0259 static bool ni_read_disabled_bios(struct radeon_device *rdev)
0260 {
0261     u32 bus_cntl;
0262     u32 d1vga_control;
0263     u32 d2vga_control;
0264     u32 vga_render_control;
0265     u32 rom_cntl;
0266     bool r;
0267 
0268     bus_cntl = RREG32(R600_BUS_CNTL);
0269     d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
0270     d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
0271     vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
0272     rom_cntl = RREG32(R600_ROM_CNTL);
0273 
0274     /* enable the rom */
0275     WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
0276     if (!ASIC_IS_NODCE(rdev)) {
0277         /* Disable VGA mode */
0278         WREG32(AVIVO_D1VGA_CONTROL,
0279                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
0280                       AVIVO_DVGA_CONTROL_TIMING_SELECT)));
0281         WREG32(AVIVO_D2VGA_CONTROL,
0282                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
0283                       AVIVO_DVGA_CONTROL_TIMING_SELECT)));
0284         WREG32(AVIVO_VGA_RENDER_CONTROL,
0285                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
0286     }
0287     WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
0288 
0289     r = radeon_read_bios(rdev);
0290 
0291     /* restore regs */
0292     WREG32(R600_BUS_CNTL, bus_cntl);
0293     if (!ASIC_IS_NODCE(rdev)) {
0294         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
0295         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
0296         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
0297     }
0298     WREG32(R600_ROM_CNTL, rom_cntl);
0299     return r;
0300 }
0301 
0302 static bool r700_read_disabled_bios(struct radeon_device *rdev)
0303 {
0304     uint32_t viph_control;
0305     uint32_t bus_cntl;
0306     uint32_t d1vga_control;
0307     uint32_t d2vga_control;
0308     uint32_t vga_render_control;
0309     uint32_t rom_cntl;
0310     uint32_t cg_spll_func_cntl = 0;
0311     uint32_t cg_spll_status;
0312     bool r;
0313 
0314     viph_control = RREG32(RADEON_VIPH_CONTROL);
0315     bus_cntl = RREG32(R600_BUS_CNTL);
0316     d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
0317     d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
0318     vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
0319     rom_cntl = RREG32(R600_ROM_CNTL);
0320 
0321     /* disable VIP */
0322     WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
0323     /* enable the rom */
0324     WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
0325     /* Disable VGA mode */
0326     WREG32(AVIVO_D1VGA_CONTROL,
0327            (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
0328         AVIVO_DVGA_CONTROL_TIMING_SELECT)));
0329     WREG32(AVIVO_D2VGA_CONTROL,
0330            (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
0331         AVIVO_DVGA_CONTROL_TIMING_SELECT)));
0332     WREG32(AVIVO_VGA_RENDER_CONTROL,
0333            (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
0334 
0335     if (rdev->family == CHIP_RV730) {
0336         cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
0337 
0338         /* enable bypass mode */
0339         WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
0340                         R600_SPLL_BYPASS_EN));
0341 
0342         /* wait for SPLL_CHG_STATUS to change to 1 */
0343         cg_spll_status = 0;
0344         while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
0345             cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
0346 
0347         WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
0348     } else
0349         WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
0350 
0351     r = radeon_read_bios(rdev);
0352 
0353     /* restore regs */
0354     if (rdev->family == CHIP_RV730) {
0355         WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
0356 
0357         /* wait for SPLL_CHG_STATUS to change to 1 */
0358         cg_spll_status = 0;
0359         while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
0360             cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
0361     }
0362     WREG32(RADEON_VIPH_CONTROL, viph_control);
0363     WREG32(R600_BUS_CNTL, bus_cntl);
0364     WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
0365     WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
0366     WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
0367     WREG32(R600_ROM_CNTL, rom_cntl);
0368     return r;
0369 }
0370 
0371 static bool r600_read_disabled_bios(struct radeon_device *rdev)
0372 {
0373     uint32_t viph_control;
0374     uint32_t bus_cntl;
0375     uint32_t d1vga_control;
0376     uint32_t d2vga_control;
0377     uint32_t vga_render_control;
0378     uint32_t rom_cntl;
0379     uint32_t general_pwrmgt;
0380     uint32_t low_vid_lower_gpio_cntl;
0381     uint32_t medium_vid_lower_gpio_cntl;
0382     uint32_t high_vid_lower_gpio_cntl;
0383     uint32_t ctxsw_vid_lower_gpio_cntl;
0384     uint32_t lower_gpio_enable;
0385     bool r;
0386 
0387     viph_control = RREG32(RADEON_VIPH_CONTROL);
0388     bus_cntl = RREG32(R600_BUS_CNTL);
0389     d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
0390     d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
0391     vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
0392     rom_cntl = RREG32(R600_ROM_CNTL);
0393     general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
0394     low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
0395     medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
0396     high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
0397     ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
0398     lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
0399 
0400     /* disable VIP */
0401     WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
0402     /* enable the rom */
0403     WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
0404     /* Disable VGA mode */
0405     WREG32(AVIVO_D1VGA_CONTROL,
0406            (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
0407         AVIVO_DVGA_CONTROL_TIMING_SELECT)));
0408     WREG32(AVIVO_D2VGA_CONTROL,
0409            (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
0410         AVIVO_DVGA_CONTROL_TIMING_SELECT)));
0411     WREG32(AVIVO_VGA_RENDER_CONTROL,
0412            (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
0413 
0414     WREG32(R600_ROM_CNTL,
0415            ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
0416         (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
0417         R600_SCK_OVERWRITE));
0418 
0419     WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
0420     WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
0421            (low_vid_lower_gpio_cntl & ~0x400));
0422     WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
0423            (medium_vid_lower_gpio_cntl & ~0x400));
0424     WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
0425            (high_vid_lower_gpio_cntl & ~0x400));
0426     WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
0427            (ctxsw_vid_lower_gpio_cntl & ~0x400));
0428     WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
0429 
0430     r = radeon_read_bios(rdev);
0431 
0432     /* restore regs */
0433     WREG32(RADEON_VIPH_CONTROL, viph_control);
0434     WREG32(R600_BUS_CNTL, bus_cntl);
0435     WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
0436     WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
0437     WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
0438     WREG32(R600_ROM_CNTL, rom_cntl);
0439     WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
0440     WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
0441     WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
0442     WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
0443     WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
0444     WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
0445     return r;
0446 }
0447 
0448 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
0449 {
0450     uint32_t seprom_cntl1;
0451     uint32_t viph_control;
0452     uint32_t bus_cntl;
0453     uint32_t d1vga_control;
0454     uint32_t d2vga_control;
0455     uint32_t vga_render_control;
0456     uint32_t gpiopad_a;
0457     uint32_t gpiopad_en;
0458     uint32_t gpiopad_mask;
0459     bool r;
0460 
0461     seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
0462     viph_control = RREG32(RADEON_VIPH_CONTROL);
0463     bus_cntl = RREG32(RV370_BUS_CNTL);
0464     d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
0465     d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
0466     vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
0467     gpiopad_a = RREG32(RADEON_GPIOPAD_A);
0468     gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
0469     gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
0470 
0471     WREG32(RADEON_SEPROM_CNTL1,
0472            ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
0473         (0xc << RADEON_SCK_PRESCALE_SHIFT)));
0474     WREG32(RADEON_GPIOPAD_A, 0);
0475     WREG32(RADEON_GPIOPAD_EN, 0);
0476     WREG32(RADEON_GPIOPAD_MASK, 0);
0477 
0478     /* disable VIP */
0479     WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
0480 
0481     /* enable the rom */
0482     WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
0483 
0484     /* Disable VGA mode */
0485     WREG32(AVIVO_D1VGA_CONTROL,
0486            (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
0487         AVIVO_DVGA_CONTROL_TIMING_SELECT)));
0488     WREG32(AVIVO_D2VGA_CONTROL,
0489            (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
0490         AVIVO_DVGA_CONTROL_TIMING_SELECT)));
0491     WREG32(AVIVO_VGA_RENDER_CONTROL,
0492            (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
0493 
0494     r = radeon_read_bios(rdev);
0495 
0496     /* restore regs */
0497     WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
0498     WREG32(RADEON_VIPH_CONTROL, viph_control);
0499     WREG32(RV370_BUS_CNTL, bus_cntl);
0500     WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
0501     WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
0502     WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
0503     WREG32(RADEON_GPIOPAD_A, gpiopad_a);
0504     WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
0505     WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
0506     return r;
0507 }
0508 
0509 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
0510 {
0511     uint32_t seprom_cntl1;
0512     uint32_t viph_control;
0513     uint32_t bus_cntl;
0514     uint32_t crtc_gen_cntl;
0515     uint32_t crtc2_gen_cntl;
0516     uint32_t crtc_ext_cntl;
0517     uint32_t fp2_gen_cntl;
0518     bool r;
0519 
0520     seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
0521     viph_control = RREG32(RADEON_VIPH_CONTROL);
0522     if (rdev->flags & RADEON_IS_PCIE)
0523         bus_cntl = RREG32(RV370_BUS_CNTL);
0524     else
0525         bus_cntl = RREG32(RADEON_BUS_CNTL);
0526     crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
0527     crtc2_gen_cntl = 0;
0528     crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
0529     fp2_gen_cntl = 0;
0530 
0531     if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
0532         fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
0533     }
0534 
0535     if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
0536         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
0537     }
0538 
0539     WREG32(RADEON_SEPROM_CNTL1,
0540            ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
0541         (0xc << RADEON_SCK_PRESCALE_SHIFT)));
0542 
0543     /* disable VIP */
0544     WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
0545 
0546     /* enable the rom */
0547     if (rdev->flags & RADEON_IS_PCIE)
0548         WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
0549     else
0550         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
0551 
0552     /* Turn off mem requests and CRTC for both controllers */
0553     WREG32(RADEON_CRTC_GEN_CNTL,
0554            ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
0555         (RADEON_CRTC_DISP_REQ_EN_B |
0556          RADEON_CRTC_EXT_DISP_EN)));
0557     if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
0558         WREG32(RADEON_CRTC2_GEN_CNTL,
0559                ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
0560             RADEON_CRTC2_DISP_REQ_EN_B));
0561     }
0562     /* Turn off CRTC */
0563     WREG32(RADEON_CRTC_EXT_CNTL,
0564            ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
0565         (RADEON_CRTC_SYNC_TRISTAT |
0566          RADEON_CRTC_DISPLAY_DIS)));
0567 
0568     if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
0569         WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
0570     }
0571 
0572     r = radeon_read_bios(rdev);
0573 
0574     /* restore regs */
0575     WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
0576     WREG32(RADEON_VIPH_CONTROL, viph_control);
0577     if (rdev->flags & RADEON_IS_PCIE)
0578         WREG32(RV370_BUS_CNTL, bus_cntl);
0579     else
0580         WREG32(RADEON_BUS_CNTL, bus_cntl);
0581     WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
0582     if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
0583         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
0584     }
0585     WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
0586     if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
0587         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
0588     }
0589     return r;
0590 }
0591 
0592 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
0593 {
0594     if (rdev->flags & RADEON_IS_IGP)
0595         return igp_read_bios_from_vram(rdev);
0596     else if (rdev->family >= CHIP_BARTS)
0597         return ni_read_disabled_bios(rdev);
0598     else if (rdev->family >= CHIP_RV770)
0599         return r700_read_disabled_bios(rdev);
0600     else if (rdev->family >= CHIP_R600)
0601         return r600_read_disabled_bios(rdev);
0602     else if (rdev->family >= CHIP_RS600)
0603         return avivo_read_disabled_bios(rdev);
0604     else
0605         return legacy_read_disabled_bios(rdev);
0606 }
0607 
0608 #ifdef CONFIG_ACPI
0609 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
0610 {
0611     struct acpi_table_header *hdr;
0612     acpi_size tbl_size;
0613     UEFI_ACPI_VFCT *vfct;
0614     unsigned offset;
0615 
0616     if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr)))
0617         return false;
0618     tbl_size = hdr->length;
0619     if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
0620         DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
0621         return false;
0622     }
0623 
0624     vfct = (UEFI_ACPI_VFCT *)hdr;
0625     offset = vfct->VBIOSImageOffset;
0626 
0627     while (offset < tbl_size) {
0628         GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset);
0629         VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader;
0630 
0631         offset += sizeof(VFCT_IMAGE_HEADER);
0632         if (offset > tbl_size) {
0633             DRM_ERROR("ACPI VFCT image header truncated\n");
0634             return false;
0635         }
0636 
0637         offset += vhdr->ImageLength;
0638         if (offset > tbl_size) {
0639             DRM_ERROR("ACPI VFCT image truncated\n");
0640             return false;
0641         }
0642 
0643         if (vhdr->ImageLength &&
0644             vhdr->PCIBus == rdev->pdev->bus->number &&
0645             vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) &&
0646             vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) &&
0647             vhdr->VendorID == rdev->pdev->vendor &&
0648             vhdr->DeviceID == rdev->pdev->device) {
0649             rdev->bios = kmemdup(&vbios->VbiosContent,
0650                          vhdr->ImageLength,
0651                          GFP_KERNEL);
0652 
0653             if (!rdev->bios)
0654                 return false;
0655             return true;
0656         }
0657     }
0658 
0659     DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
0660     return false;
0661 }
0662 #else
0663 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
0664 {
0665     return false;
0666 }
0667 #endif
0668 
0669 bool radeon_get_bios(struct radeon_device *rdev)
0670 {
0671     bool r;
0672     uint16_t tmp;
0673 
0674     r = radeon_atrm_get_bios(rdev);
0675     if (!r)
0676         r = radeon_acpi_vfct_bios(rdev);
0677     if (!r)
0678         r = igp_read_bios_from_vram(rdev);
0679     if (!r)
0680         r = radeon_read_bios(rdev);
0681     if (!r)
0682         r = radeon_read_disabled_bios(rdev);
0683     if (!r)
0684         r = radeon_read_platform_bios(rdev);
0685     if (!r || rdev->bios == NULL) {
0686         DRM_ERROR("Unable to locate a BIOS ROM\n");
0687         rdev->bios = NULL;
0688         return false;
0689     }
0690     if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
0691         printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
0692         goto free_bios;
0693     }
0694 
0695     tmp = RBIOS16(0x18);
0696     if (RBIOS8(tmp + 0x14) != 0x0) {
0697         DRM_INFO("Not an x86 BIOS ROM, not using.\n");
0698         goto free_bios;
0699     }
0700 
0701     rdev->bios_header_start = RBIOS16(0x48);
0702     if (!rdev->bios_header_start) {
0703         goto free_bios;
0704     }
0705     tmp = rdev->bios_header_start + 4;
0706     if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
0707         !memcmp(rdev->bios + tmp, "MOTA", 4)) {
0708         rdev->is_atom_bios = true;
0709     } else {
0710         rdev->is_atom_bios = false;
0711     }
0712 
0713     DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
0714     return true;
0715 free_bios:
0716     kfree(rdev->bios);
0717     rdev->bios = NULL;
0718     return false;
0719 }
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