drm/radeon/radeon_asic.h

0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028 #ifndef __RADEON_ASIC_H__
0029 #define __RADEON_ASIC_H__
0030
0031 /*
0032  * common functions
0033  */
0034 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
0035 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
0036 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
0037 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
0038
0039 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
0040 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
0041 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
0042 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
0043 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
0044
0045 void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
0046 u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
0047 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
0048 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
0049
0050 /*
0051  * r100,rv100,rs100,rv200,rs200
0052  */
0053 struct r100_mc_save {
0054     u32 GENMO_WT;
0055     u32 CRTC_EXT_CNTL;
0056     u32 CRTC_GEN_CNTL;
0057     u32 CRTC2_GEN_CNTL;
0058     u32 CUR_OFFSET;
0059     u32 CUR2_OFFSET;
0060 };
0061 int r100_init(struct radeon_device *rdev);
0062 void r100_fini(struct radeon_device *rdev);
0063 int r100_suspend(struct radeon_device *rdev);
0064 int r100_resume(struct radeon_device *rdev);
0065 void r100_vga_set_state(struct radeon_device *rdev, bool state);
0066 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
0067 int r100_asic_reset(struct radeon_device *rdev, bool hard);
0068 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
0069 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
0070 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags);
0071 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
0072                 uint64_t entry);
0073 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
0074 int r100_irq_set(struct radeon_device *rdev);
0075 int r100_irq_process(struct radeon_device *rdev);
0076 void r100_fence_ring_emit(struct radeon_device *rdev,
0077               struct radeon_fence *fence);
0078 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
0079                   struct radeon_ring *cp,
0080                   struct radeon_semaphore *semaphore,
0081                   bool emit_wait);
0082 int r100_cs_parse(struct radeon_cs_parser *p);
0083 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
0084 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
0085 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
0086                     uint64_t src_offset,
0087                     uint64_t dst_offset,
0088                     unsigned num_gpu_pages,
0089                     struct dma_resv *resv);
0090 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
0091              uint32_t tiling_flags, uint32_t pitch,
0092              uint32_t offset, uint32_t obj_size);
0093 void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
0094 void r100_bandwidth_update(struct radeon_device *rdev);
0095 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
0096 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
0097 void r100_hpd_init(struct radeon_device *rdev);
0098 void r100_hpd_fini(struct radeon_device *rdev);
0099 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
0100 void r100_hpd_set_polarity(struct radeon_device *rdev,
0101                enum radeon_hpd_id hpd);
0102 void r100_debugfs_rbbm_init(struct radeon_device *rdev);
0103 void r100_debugfs_cp_init(struct radeon_device *rdev);
0104 void r100_cp_disable(struct radeon_device *rdev);
0105 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
0106 void r100_cp_fini(struct radeon_device *rdev);
0107 int r100_pci_gart_init(struct radeon_device *rdev);
0108 void r100_pci_gart_fini(struct radeon_device *rdev);
0109 int r100_pci_gart_enable(struct radeon_device *rdev);
0110 void r100_pci_gart_disable(struct radeon_device *rdev);
0111 void  r100_debugfs_mc_info_init(struct radeon_device *rdev);
0112 int r100_gui_wait_for_idle(struct radeon_device *rdev);
0113 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
0114 void r100_irq_disable(struct radeon_device *rdev);
0115 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
0116 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
0117 void r100_vram_init_sizes(struct radeon_device *rdev);
0118 int r100_cp_reset(struct radeon_device *rdev);
0119 void r100_vga_render_disable(struct radeon_device *rdev);
0120 void r100_restore_sanity(struct radeon_device *rdev);
0121 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
0122                      struct radeon_cs_packet *pkt,
0123                      struct radeon_bo *robj);
0124 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
0125               struct radeon_cs_packet *pkt,
0126               const unsigned *auth, unsigned n,
0127               radeon_packet0_check_t check);
0128 int r100_cs_packet_parse(struct radeon_cs_parser *p,
0129              struct radeon_cs_packet *pkt,
0130              unsigned idx);
0131 void r100_enable_bm(struct radeon_device *rdev);
0132 void r100_set_common_regs(struct radeon_device *rdev);
0133 void r100_bm_disable(struct radeon_device *rdev);
0134 extern bool r100_gui_idle(struct radeon_device *rdev);
0135 extern void r100_pm_misc(struct radeon_device *rdev);
0136 extern void r100_pm_prepare(struct radeon_device *rdev);
0137 extern void r100_pm_finish(struct radeon_device *rdev);
0138 extern void r100_pm_init_profile(struct radeon_device *rdev);
0139 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
0140 extern void r100_page_flip(struct radeon_device *rdev, int crtc,
0141                u64 crtc_base, bool async);
0142 extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc);
0143 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
0144 extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
0145
0146 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
0147               struct radeon_ring *ring);
0148 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
0149               struct radeon_ring *ring);
0150 void r100_gfx_set_wptr(struct radeon_device *rdev,
0151                struct radeon_ring *ring);
0152
0153 /*
0154  * r200,rv250,rs300,rv280
0155  */
0156 struct radeon_fence *r200_copy_dma(struct radeon_device *rdev,
0157                    uint64_t src_offset,
0158                    uint64_t dst_offset,
0159                    unsigned num_gpu_pages,
0160                    struct dma_resv *resv);
0161 void r200_set_safe_registers(struct radeon_device *rdev);
0162
0163 /*
0164  * r300,r350,rv350,rv380
0165  */
0166 extern int r300_init(struct radeon_device *rdev);
0167 extern void r300_fini(struct radeon_device *rdev);
0168 extern int r300_suspend(struct radeon_device *rdev);
0169 extern int r300_resume(struct radeon_device *rdev);
0170 extern int r300_asic_reset(struct radeon_device *rdev, bool hard);
0171 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
0172 extern void r300_fence_ring_emit(struct radeon_device *rdev,
0173                 struct radeon_fence *fence);
0174 extern int r300_cs_parse(struct radeon_cs_parser *p);
0175 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
0176 extern uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags);
0177 extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
0178                      uint64_t entry);
0179 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
0180 extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
0181 extern void r300_set_reg_safe(struct radeon_device *rdev);
0182 extern void r300_mc_program(struct radeon_device *rdev);
0183 extern void r300_mc_init(struct radeon_device *rdev);
0184 extern void r300_clock_startup(struct radeon_device *rdev);
0185 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
0186 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
0187 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
0188 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
0189 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
0190
0191 /*
0192  * r420,r423,rv410
0193  */
0194 extern int r420_init(struct radeon_device *rdev);
0195 extern void r420_fini(struct radeon_device *rdev);
0196 extern int r420_suspend(struct radeon_device *rdev);
0197 extern int r420_resume(struct radeon_device *rdev);
0198 extern void r420_pm_init_profile(struct radeon_device *rdev);
0199 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
0200 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
0201 extern void r420_debugfs_pipes_info_init(struct radeon_device *rdev);
0202 extern void r420_pipes_init(struct radeon_device *rdev);
0203
0204 /*
0205  * rs400,rs480
0206  */
0207 extern int rs400_init(struct radeon_device *rdev);
0208 extern void rs400_fini(struct radeon_device *rdev);
0209 extern int rs400_suspend(struct radeon_device *rdev);
0210 extern int rs400_resume(struct radeon_device *rdev);
0211 void rs400_gart_tlb_flush(struct radeon_device *rdev);
0212 uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags);
0213 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
0214              uint64_t entry);
0215 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
0216 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
0217 int rs400_gart_init(struct radeon_device *rdev);
0218 int rs400_gart_enable(struct radeon_device *rdev);
0219 void rs400_gart_adjust_size(struct radeon_device *rdev);
0220 void rs400_gart_disable(struct radeon_device *rdev);
0221 void rs400_gart_fini(struct radeon_device *rdev);
0222 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
0223
0224 /*
0225  * rs600.
0226  */
0227 extern int rs600_asic_reset(struct radeon_device *rdev, bool hard);
0228 extern int rs600_init(struct radeon_device *rdev);
0229 extern void rs600_fini(struct radeon_device *rdev);
0230 extern int rs600_suspend(struct radeon_device *rdev);
0231 extern int rs600_resume(struct radeon_device *rdev);
0232 int rs600_irq_set(struct radeon_device *rdev);
0233 int rs600_irq_process(struct radeon_device *rdev);
0234 void rs600_irq_disable(struct radeon_device *rdev);
0235 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
0236 void rs600_gart_tlb_flush(struct radeon_device *rdev);
0237 uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags);
0238 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
0239              uint64_t entry);
0240 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
0241 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
0242 void rs600_bandwidth_update(struct radeon_device *rdev);
0243 void rs600_hpd_init(struct radeon_device *rdev);
0244 void rs600_hpd_fini(struct radeon_device *rdev);
0245 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
0246 void rs600_hpd_set_polarity(struct radeon_device *rdev,
0247                 enum radeon_hpd_id hpd);
0248 extern void rs600_pm_misc(struct radeon_device *rdev);
0249 extern void rs600_pm_prepare(struct radeon_device *rdev);
0250 extern void rs600_pm_finish(struct radeon_device *rdev);
0251 extern void rs600_page_flip(struct radeon_device *rdev, int crtc,
0252                 u64 crtc_base, bool async);
0253 extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc);
0254 void rs600_set_safe_registers(struct radeon_device *rdev);
0255 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
0256 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
0257
0258 /*
0259  * rs690,rs740
0260  */
0261 int rs690_init(struct radeon_device *rdev);
0262 void rs690_fini(struct radeon_device *rdev);
0263 int rs690_resume(struct radeon_device *rdev);
0264 int rs690_suspend(struct radeon_device *rdev);
0265 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
0266 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
0267 void rs690_bandwidth_update(struct radeon_device *rdev);
0268 void rs690_line_buffer_adjust(struct radeon_device *rdev,
0269                     struct drm_display_mode *mode1,
0270                     struct drm_display_mode *mode2);
0271 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
0272
0273 /*
0274  * rv515
0275  */
0276 struct rv515_mc_save {
0277     u32 vga_render_control;
0278     u32 vga_hdp_control;
0279     bool crtc_enabled[2];
0280 };
0281
0282 int rv515_init(struct radeon_device *rdev);
0283 void rv515_fini(struct radeon_device *rdev);
0284 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
0285 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
0286 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
0287 void rv515_bandwidth_update(struct radeon_device *rdev);
0288 int rv515_resume(struct radeon_device *rdev);
0289 int rv515_suspend(struct radeon_device *rdev);
0290 void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
0291 void rv515_vga_render_disable(struct radeon_device *rdev);
0292 void rv515_set_safe_registers(struct radeon_device *rdev);
0293 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
0294 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
0295 void rv515_clock_startup(struct radeon_device *rdev);
0296 void rv515_debugfs(struct radeon_device *rdev);
0297 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
0298
0299 /*
0300  * r520,rv530,rv560,rv570,r580
0301  */
0302 int r520_init(struct radeon_device *rdev);
0303 int r520_resume(struct radeon_device *rdev);
0304 int r520_mc_wait_for_idle(struct radeon_device *rdev);
0305
0306 /*
0307  * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
0308  */
0309 int r600_init(struct radeon_device *rdev);
0310 void r600_fini(struct radeon_device *rdev);
0311 int r600_suspend(struct radeon_device *rdev);
0312 int r600_resume(struct radeon_device *rdev);
0313 void r600_vga_set_state(struct radeon_device *rdev, bool state);
0314 int r600_wb_init(struct radeon_device *rdev);
0315 void r600_wb_fini(struct radeon_device *rdev);
0316 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
0317 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
0318 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
0319 int r600_cs_parse(struct radeon_cs_parser *p);
0320 int r600_dma_cs_parse(struct radeon_cs_parser *p);
0321 void r600_fence_ring_emit(struct radeon_device *rdev,
0322               struct radeon_fence *fence);
0323 bool r600_semaphore_ring_emit(struct radeon_device *rdev,
0324                   struct radeon_ring *cp,
0325                   struct radeon_semaphore *semaphore,
0326                   bool emit_wait);
0327 void r600_dma_fence_ring_emit(struct radeon_device *rdev,
0328                   struct radeon_fence *fence);
0329 bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
0330                   struct radeon_ring *ring,
0331                   struct radeon_semaphore *semaphore,
0332                   bool emit_wait);
0333 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
0334 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
0335 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
0336 int r600_asic_reset(struct radeon_device *rdev, bool hard);
0337 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
0338              uint32_t tiling_flags, uint32_t pitch,
0339              uint32_t offset, uint32_t obj_size);
0340 void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
0341 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
0342 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
0343 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
0344 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
0345 int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
0346 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
0347                      uint64_t src_offset, uint64_t dst_offset,
0348                      unsigned num_gpu_pages,
0349                      struct dma_resv *resv);
0350 struct radeon_fence *r600_copy_dma(struct radeon_device *rdev,
0351                    uint64_t src_offset, uint64_t dst_offset,
0352                    unsigned num_gpu_pages,
0353                    struct dma_resv *resv);
0354 void r600_hpd_init(struct radeon_device *rdev);
0355 void r600_hpd_fini(struct radeon_device *rdev);
0356 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
0357 void r600_hpd_set_polarity(struct radeon_device *rdev,
0358                enum radeon_hpd_id hpd);
0359 extern void r600_mmio_hdp_flush(struct radeon_device *rdev);
0360 extern bool r600_gui_idle(struct radeon_device *rdev);
0361 extern void r600_pm_misc(struct radeon_device *rdev);
0362 extern void r600_pm_init_profile(struct radeon_device *rdev);
0363 extern void rs780_pm_init_profile(struct radeon_device *rdev);
0364 extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
0365 extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
0366 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
0367 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
0368 extern int r600_get_pcie_lanes(struct radeon_device *rdev);
0369 bool r600_card_posted(struct radeon_device *rdev);
0370 void r600_cp_stop(struct radeon_device *rdev);
0371 int r600_cp_start(struct radeon_device *rdev);
0372 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
0373 int r600_cp_resume(struct radeon_device *rdev);
0374 void r600_cp_fini(struct radeon_device *rdev);
0375 int r600_count_pipe_bits(uint32_t val);
0376 int r600_mc_wait_for_idle(struct radeon_device *rdev);
0377 int r600_pcie_gart_init(struct radeon_device *rdev);
0378 void r600_scratch_init(struct radeon_device *rdev);
0379 int r600_init_microcode(struct radeon_device *rdev);
0380 u32 r600_gfx_get_rptr(struct radeon_device *rdev,
0381               struct radeon_ring *ring);
0382 u32 r600_gfx_get_wptr(struct radeon_device *rdev,
0383               struct radeon_ring *ring);
0384 void r600_gfx_set_wptr(struct radeon_device *rdev,
0385                struct radeon_ring *ring);
0386 int r600_get_allowed_info_register(struct radeon_device *rdev,
0387                    u32 reg, u32 *val);
0388 /* r600 irq */
0389 int r600_irq_process(struct radeon_device *rdev);
0390 int r600_irq_init(struct radeon_device *rdev);
0391 void r600_irq_fini(struct radeon_device *rdev);
0392 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
0393 int r600_irq_set(struct radeon_device *rdev);
0394 void r600_irq_suspend(struct radeon_device *rdev);
0395 void r600_disable_interrupts(struct radeon_device *rdev);
0396 void r600_rlc_stop(struct radeon_device *rdev);
0397 /* r600 audio */
0398 void r600_audio_fini(struct radeon_device *rdev);
0399 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);
0400 void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
0401                     size_t size);
0402 void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock);
0403 void r600_hdmi_audio_workaround(struct drm_encoder *encoder);
0404 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
0405 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
0406 u32 r600_get_xclk(struct radeon_device *rdev);
0407 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
0408 int rv6xx_get_temp(struct radeon_device *rdev);
0409 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
0410 int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
0411 void r600_dpm_post_set_power_state(struct radeon_device *rdev);
0412 int r600_dpm_late_enable(struct radeon_device *rdev);
0413 /* r600 dma */
0414 uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
0415                struct radeon_ring *ring);
0416 uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
0417                struct radeon_ring *ring);
0418 void r600_dma_set_wptr(struct radeon_device *rdev,
0419                struct radeon_ring *ring);
0420 /* rv6xx dpm */
0421 int rv6xx_dpm_init(struct radeon_device *rdev);
0422 int rv6xx_dpm_enable(struct radeon_device *rdev);
0423 void rv6xx_dpm_disable(struct radeon_device *rdev);
0424 int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
0425 void rv6xx_setup_asic(struct radeon_device *rdev);
0426 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
0427 void rv6xx_dpm_fini(struct radeon_device *rdev);
0428 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
0429 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
0430 void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
0431                  struct radeon_ps *ps);
0432 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
0433                                struct seq_file *m);
0434 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
0435                       enum radeon_dpm_forced_level level);
0436 u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev);
0437 u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev);
0438 /* rs780 dpm */
0439 int rs780_dpm_init(struct radeon_device *rdev);
0440 int rs780_dpm_enable(struct radeon_device *rdev);
0441 void rs780_dpm_disable(struct radeon_device *rdev);
0442 int rs780_dpm_set_power_state(struct radeon_device *rdev);
0443 void rs780_dpm_setup_asic(struct radeon_device *rdev);
0444 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
0445 void rs780_dpm_fini(struct radeon_device *rdev);
0446 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
0447 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
0448 void rs780_dpm_print_power_state(struct radeon_device *rdev,
0449                  struct radeon_ps *ps);
0450 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
0451                                struct seq_file *m);
0452 int rs780_dpm_force_performance_level(struct radeon_device *rdev,
0453                       enum radeon_dpm_forced_level level);
0454 u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev);
0455 u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev);
0456
0457 /*
0458  * rv770,rv730,rv710,rv740
0459  */
0460 int rv770_init(struct radeon_device *rdev);
0461 void rv770_fini(struct radeon_device *rdev);
0462 int rv770_suspend(struct radeon_device *rdev);
0463 int rv770_resume(struct radeon_device *rdev);
0464 void rv770_pm_misc(struct radeon_device *rdev);
0465 void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base,
0466              bool async);
0467 bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc);
0468 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
0469 void r700_cp_stop(struct radeon_device *rdev);
0470 void r700_cp_fini(struct radeon_device *rdev);
0471 struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev,
0472                     uint64_t src_offset, uint64_t dst_offset,
0473                     unsigned num_gpu_pages,
0474                     struct dma_resv *resv);
0475 u32 rv770_get_xclk(struct radeon_device *rdev);
0476 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
0477 int rv770_get_temp(struct radeon_device *rdev);
0478 /* rv7xx pm */
0479 int rv770_dpm_init(struct radeon_device *rdev);
0480 int rv770_dpm_enable(struct radeon_device *rdev);
0481 int rv770_dpm_late_enable(struct radeon_device *rdev);
0482 void rv770_dpm_disable(struct radeon_device *rdev);
0483 int rv770_dpm_set_power_state(struct radeon_device *rdev);
0484 void rv770_dpm_setup_asic(struct radeon_device *rdev);
0485 void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
0486 void rv770_dpm_fini(struct radeon_device *rdev);
0487 u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
0488 u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
0489 void rv770_dpm_print_power_state(struct radeon_device *rdev,
0490                  struct radeon_ps *ps);
0491 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
0492                                struct seq_file *m);
0493 int rv770_dpm_force_performance_level(struct radeon_device *rdev,
0494                       enum radeon_dpm_forced_level level);
0495 bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
0496 u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev);
0497 u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev);
0498
0499 /*
0500  * evergreen
0501  */
0502 struct evergreen_mc_save {
0503     u32 vga_render_control;
0504     u32 vga_hdp_control;
0505     bool crtc_enabled[RADEON_MAX_CRTCS];
0506 };
0507
0508 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
0509 int evergreen_init(struct radeon_device *rdev);
0510 void evergreen_fini(struct radeon_device *rdev);
0511 int evergreen_suspend(struct radeon_device *rdev);
0512 int evergreen_resume(struct radeon_device *rdev);
0513 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
0514 bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
0515 int evergreen_asic_reset(struct radeon_device *rdev, bool hard);
0516 void evergreen_bandwidth_update(struct radeon_device *rdev);
0517 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
0518 void evergreen_hpd_init(struct radeon_device *rdev);
0519 void evergreen_hpd_fini(struct radeon_device *rdev);
0520 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
0521 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
0522                 enum radeon_hpd_id hpd);
0523 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
0524 int evergreen_irq_set(struct radeon_device *rdev);
0525 int evergreen_irq_process(struct radeon_device *rdev);
0526 extern int evergreen_cs_parse(struct radeon_cs_parser *p);
0527 extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
0528 extern void evergreen_pm_misc(struct radeon_device *rdev);
0529 extern void evergreen_pm_prepare(struct radeon_device *rdev);
0530 extern void evergreen_pm_finish(struct radeon_device *rdev);
0531 extern void sumo_pm_init_profile(struct radeon_device *rdev);
0532 extern void btc_pm_init_profile(struct radeon_device *rdev);
0533 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
0534 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
0535 extern void evergreen_page_flip(struct radeon_device *rdev, int crtc,
0536                 u64 crtc_base, bool async);
0537 extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc);
0538 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
0539 void evergreen_disable_interrupt_state(struct radeon_device *rdev);
0540 int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
0541 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
0542                    struct radeon_fence *fence);
0543 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
0544                    struct radeon_ib *ib);
0545 struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev,
0546                     uint64_t src_offset, uint64_t dst_offset,
0547                     unsigned num_gpu_pages,
0548                     struct dma_resv *resv);
0549 int evergreen_get_temp(struct radeon_device *rdev);
0550 int evergreen_get_allowed_info_register(struct radeon_device *rdev,
0551                     u32 reg, u32 *val);
0552 int sumo_get_temp(struct radeon_device *rdev);
0553 int tn_get_temp(struct radeon_device *rdev);
0554 int cypress_dpm_init(struct radeon_device *rdev);
0555 void cypress_dpm_setup_asic(struct radeon_device *rdev);
0556 int cypress_dpm_enable(struct radeon_device *rdev);
0557 void cypress_dpm_disable(struct radeon_device *rdev);
0558 int cypress_dpm_set_power_state(struct radeon_device *rdev);
0559 void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
0560 void cypress_dpm_fini(struct radeon_device *rdev);
0561 bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
0562 int btc_dpm_init(struct radeon_device *rdev);
0563 void btc_dpm_setup_asic(struct radeon_device *rdev);
0564 int btc_dpm_enable(struct radeon_device *rdev);
0565 void btc_dpm_disable(struct radeon_device *rdev);
0566 int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
0567 int btc_dpm_set_power_state(struct radeon_device *rdev);
0568 void btc_dpm_post_set_power_state(struct radeon_device *rdev);
0569 void btc_dpm_fini(struct radeon_device *rdev);
0570 u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
0571 u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
0572 bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
0573 void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
0574                              struct seq_file *m);
0575 u32 btc_dpm_get_current_sclk(struct radeon_device *rdev);
0576 u32 btc_dpm_get_current_mclk(struct radeon_device *rdev);
0577 int sumo_dpm_init(struct radeon_device *rdev);
0578 int sumo_dpm_enable(struct radeon_device *rdev);
0579 int sumo_dpm_late_enable(struct radeon_device *rdev);
0580 void sumo_dpm_disable(struct radeon_device *rdev);
0581 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
0582 int sumo_dpm_set_power_state(struct radeon_device *rdev);
0583 void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
0584 void sumo_dpm_setup_asic(struct radeon_device *rdev);
0585 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
0586 void sumo_dpm_fini(struct radeon_device *rdev);
0587 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
0588 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
0589 void sumo_dpm_print_power_state(struct radeon_device *rdev,
0590                 struct radeon_ps *ps);
0591 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
0592                               struct seq_file *m);
0593 int sumo_dpm_force_performance_level(struct radeon_device *rdev,
0594                      enum radeon_dpm_forced_level level);
0595 u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev);
0596 u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev);
0597 u16 sumo_dpm_get_current_vddc(struct radeon_device *rdev);
0598
0599 /*
0600  * cayman
0601  */
0602 void cayman_fence_ring_emit(struct radeon_device *rdev,
0603                 struct radeon_fence *fence);
0604 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
0605 int cayman_init(struct radeon_device *rdev);
0606 void cayman_fini(struct radeon_device *rdev);
0607 int cayman_suspend(struct radeon_device *rdev);
0608 int cayman_resume(struct radeon_device *rdev);
0609 int cayman_asic_reset(struct radeon_device *rdev, bool hard);
0610 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
0611 int cayman_vm_init(struct radeon_device *rdev);
0612 void cayman_vm_fini(struct radeon_device *rdev);
0613 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
0614              unsigned vm_id, uint64_t pd_addr);
0615 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
0616 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
0617 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
0618 void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
0619                 struct radeon_ib *ib);
0620 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
0621 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
0622
0623 void cayman_dma_vm_copy_pages(struct radeon_device *rdev,
0624                   struct radeon_ib *ib,
0625                   uint64_t pe, uint64_t src,
0626                   unsigned count);
0627 void cayman_dma_vm_write_pages(struct radeon_device *rdev,
0628                    struct radeon_ib *ib,
0629                    uint64_t pe,
0630                    uint64_t addr, unsigned count,
0631                    uint32_t incr, uint32_t flags);
0632 void cayman_dma_vm_set_pages(struct radeon_device *rdev,
0633                  struct radeon_ib *ib,
0634                  uint64_t pe,
0635                  uint64_t addr, unsigned count,
0636                  uint32_t incr, uint32_t flags);
0637 void cayman_dma_vm_pad_ib(struct radeon_ib *ib);
0638
0639 void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
0640              unsigned vm_id, uint64_t pd_addr);
0641
0642 u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
0643             struct radeon_ring *ring);
0644 u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
0645             struct radeon_ring *ring);
0646 void cayman_gfx_set_wptr(struct radeon_device *rdev,
0647              struct radeon_ring *ring);
0648 uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
0649                  struct radeon_ring *ring);
0650 uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
0651                  struct radeon_ring *ring);
0652 void cayman_dma_set_wptr(struct radeon_device *rdev,
0653              struct radeon_ring *ring);
0654 int cayman_get_allowed_info_register(struct radeon_device *rdev,
0655                      u32 reg, u32 *val);
0656
0657 int ni_dpm_init(struct radeon_device *rdev);
0658 void ni_dpm_setup_asic(struct radeon_device *rdev);
0659 int ni_dpm_enable(struct radeon_device *rdev);
0660 void ni_dpm_disable(struct radeon_device *rdev);
0661 int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
0662 int ni_dpm_set_power_state(struct radeon_device *rdev);
0663 void ni_dpm_post_set_power_state(struct radeon_device *rdev);
0664 void ni_dpm_fini(struct radeon_device *rdev);
0665 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
0666 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
0667 void ni_dpm_print_power_state(struct radeon_device *rdev,
0668                   struct radeon_ps *ps);
0669 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
0670                             struct seq_file *m);
0671 int ni_dpm_force_performance_level(struct radeon_device *rdev,
0672                    enum radeon_dpm_forced_level level);
0673 bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
0674 u32 ni_dpm_get_current_sclk(struct radeon_device *rdev);
0675 u32 ni_dpm_get_current_mclk(struct radeon_device *rdev);
0676 int trinity_dpm_init(struct radeon_device *rdev);
0677 int trinity_dpm_enable(struct radeon_device *rdev);
0678 int trinity_dpm_late_enable(struct radeon_device *rdev);
0679 void trinity_dpm_disable(struct radeon_device *rdev);
0680 int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
0681 int trinity_dpm_set_power_state(struct radeon_device *rdev);
0682 void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
0683 void trinity_dpm_setup_asic(struct radeon_device *rdev);
0684 void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
0685 void trinity_dpm_fini(struct radeon_device *rdev);
0686 u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
0687 u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
0688 void trinity_dpm_print_power_state(struct radeon_device *rdev,
0689                    struct radeon_ps *ps);
0690 void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
0691                              struct seq_file *m);
0692 int trinity_dpm_force_performance_level(struct radeon_device *rdev,
0693                     enum radeon_dpm_forced_level level);
0694 void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
0695 u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev);
0696 u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev);
0697 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
0698
0699 /* DCE6 - SI */
0700 void dce6_bandwidth_update(struct radeon_device *rdev);
0701 void dce6_audio_fini(struct radeon_device *rdev);
0702
0703 /*
0704  * si
0705  */
0706 void si_fence_ring_emit(struct radeon_device *rdev,
0707             struct radeon_fence *fence);
0708 void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
0709 int si_init(struct radeon_device *rdev);
0710 void si_fini(struct radeon_device *rdev);
0711 int si_suspend(struct radeon_device *rdev);
0712 int si_resume(struct radeon_device *rdev);
0713 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
0714 bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
0715 int si_asic_reset(struct radeon_device *rdev, bool hard);
0716 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
0717 int si_irq_set(struct radeon_device *rdev);
0718 int si_irq_process(struct radeon_device *rdev);
0719 int si_vm_init(struct radeon_device *rdev);
0720 void si_vm_fini(struct radeon_device *rdev);
0721 void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
0722          unsigned vm_id, uint64_t pd_addr);
0723 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
0724 struct radeon_fence *si_copy_dma(struct radeon_device *rdev,
0725                  uint64_t src_offset, uint64_t dst_offset,
0726                  unsigned num_gpu_pages,
0727                  struct dma_resv *resv);
0728
0729 void si_dma_vm_copy_pages(struct radeon_device *rdev,
0730               struct radeon_ib *ib,
0731               uint64_t pe, uint64_t src,
0732               unsigned count);
0733 void si_dma_vm_write_pages(struct radeon_device *rdev,
0734                struct radeon_ib *ib,
0735                uint64_t pe,
0736                uint64_t addr, unsigned count,
0737                uint32_t incr, uint32_t flags);
0738 void si_dma_vm_set_pages(struct radeon_device *rdev,
0739              struct radeon_ib *ib,
0740              uint64_t pe,
0741              uint64_t addr, unsigned count,
0742              uint32_t incr, uint32_t flags);
0743
0744 void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
0745              unsigned vm_id, uint64_t pd_addr);
0746 u32 si_get_xclk(struct radeon_device *rdev);
0747 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
0748 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
0749 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
0750 int si_get_temp(struct radeon_device *rdev);
0751 int si_get_allowed_info_register(struct radeon_device *rdev,
0752                  u32 reg, u32 *val);
0753 int si_dpm_init(struct radeon_device *rdev);
0754 void si_dpm_setup_asic(struct radeon_device *rdev);
0755 int si_dpm_enable(struct radeon_device *rdev);
0756 int si_dpm_late_enable(struct radeon_device *rdev);
0757 void si_dpm_disable(struct radeon_device *rdev);
0758 int si_dpm_pre_set_power_state(struct radeon_device *rdev);
0759 int si_dpm_set_power_state(struct radeon_device *rdev);
0760 void si_dpm_post_set_power_state(struct radeon_device *rdev);
0761 void si_dpm_fini(struct radeon_device *rdev);
0762 void si_dpm_display_configuration_changed(struct radeon_device *rdev);
0763 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
0764                             struct seq_file *m);
0765 int si_dpm_force_performance_level(struct radeon_device *rdev,
0766                    enum radeon_dpm_forced_level level);
0767 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
0768                          u32 *speed);
0769 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
0770                          u32 speed);
0771 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev);
0772 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode);
0773 u32 si_dpm_get_current_sclk(struct radeon_device *rdev);
0774 u32 si_dpm_get_current_mclk(struct radeon_device *rdev);
0775
0776 /* DCE8 - CIK */
0777 void dce8_bandwidth_update(struct radeon_device *rdev);
0778
0779 /*
0780  * cik
0781  */
0782 uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
0783 u32 cik_get_xclk(struct radeon_device *rdev);
0784 uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
0785 void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
0786 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
0787 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
0788 void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
0789                   struct radeon_fence *fence);
0790 bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
0791                   struct radeon_ring *ring,
0792                   struct radeon_semaphore *semaphore,
0793                   bool emit_wait);
0794 void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
0795 struct radeon_fence *cik_copy_dma(struct radeon_device *rdev,
0796                   uint64_t src_offset, uint64_t dst_offset,
0797                   unsigned num_gpu_pages,
0798                   struct dma_resv *resv);
0799 struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev,
0800                     uint64_t src_offset, uint64_t dst_offset,
0801                     unsigned num_gpu_pages,
0802                     struct dma_resv *resv);
0803 int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
0804 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
0805 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
0806 void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
0807                  struct radeon_fence *fence);
0808 void cik_fence_compute_ring_emit(struct radeon_device *rdev,
0809                  struct radeon_fence *fence);
0810 bool cik_semaphore_ring_emit(struct radeon_device *rdev,
0811                  struct radeon_ring *cp,
0812                  struct radeon_semaphore *semaphore,
0813                  bool emit_wait);
0814 void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
0815 int cik_init(struct radeon_device *rdev);
0816 void cik_fini(struct radeon_device *rdev);
0817 int cik_suspend(struct radeon_device *rdev);
0818 int cik_resume(struct radeon_device *rdev);
0819 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
0820 int cik_asic_reset(struct radeon_device *rdev, bool hard);
0821 void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
0822 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
0823 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
0824 int cik_irq_set(struct radeon_device *rdev);
0825 int cik_irq_process(struct radeon_device *rdev);
0826 int cik_vm_init(struct radeon_device *rdev);
0827 void cik_vm_fini(struct radeon_device *rdev);
0828 void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
0829           unsigned vm_id, uint64_t pd_addr);
0830
0831 void cik_sdma_vm_copy_pages(struct radeon_device *rdev,
0832                 struct radeon_ib *ib,
0833                 uint64_t pe, uint64_t src,
0834                 unsigned count);
0835 void cik_sdma_vm_write_pages(struct radeon_device *rdev,
0836                  struct radeon_ib *ib,
0837                  uint64_t pe,
0838                  uint64_t addr, unsigned count,
0839                  uint32_t incr, uint32_t flags);
0840 void cik_sdma_vm_set_pages(struct radeon_device *rdev,
0841                struct radeon_ib *ib,
0842                uint64_t pe,
0843                uint64_t addr, unsigned count,
0844                uint32_t incr, uint32_t flags);
0845 void cik_sdma_vm_pad_ib(struct radeon_ib *ib);
0846
0847 void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
0848               unsigned vm_id, uint64_t pd_addr);
0849 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
0850 u32 cik_gfx_get_rptr(struct radeon_device *rdev,
0851              struct radeon_ring *ring);
0852 u32 cik_gfx_get_wptr(struct radeon_device *rdev,
0853              struct radeon_ring *ring);
0854 void cik_gfx_set_wptr(struct radeon_device *rdev,
0855               struct radeon_ring *ring);
0856 u32 cik_compute_get_rptr(struct radeon_device *rdev,
0857              struct radeon_ring *ring);
0858 u32 cik_compute_get_wptr(struct radeon_device *rdev,
0859              struct radeon_ring *ring);
0860 void cik_compute_set_wptr(struct radeon_device *rdev,
0861               struct radeon_ring *ring);
0862 u32 cik_sdma_get_rptr(struct radeon_device *rdev,
0863               struct radeon_ring *ring);
0864 u32 cik_sdma_get_wptr(struct radeon_device *rdev,
0865               struct radeon_ring *ring);
0866 void cik_sdma_set_wptr(struct radeon_device *rdev,
0867                struct radeon_ring *ring);
0868 int ci_get_temp(struct radeon_device *rdev);
0869 int kv_get_temp(struct radeon_device *rdev);
0870 int cik_get_allowed_info_register(struct radeon_device *rdev,
0871                   u32 reg, u32 *val);
0872
0873 int ci_dpm_init(struct radeon_device *rdev);
0874 int ci_dpm_enable(struct radeon_device *rdev);
0875 int ci_dpm_late_enable(struct radeon_device *rdev);
0876 void ci_dpm_disable(struct radeon_device *rdev);
0877 int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
0878 int ci_dpm_set_power_state(struct radeon_device *rdev);
0879 void ci_dpm_post_set_power_state(struct radeon_device *rdev);
0880 void ci_dpm_setup_asic(struct radeon_device *rdev);
0881 void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
0882 void ci_dpm_fini(struct radeon_device *rdev);
0883 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
0884 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
0885 void ci_dpm_print_power_state(struct radeon_device *rdev,
0886                   struct radeon_ps *ps);
0887 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
0888                             struct seq_file *m);
0889 int ci_dpm_force_performance_level(struct radeon_device *rdev,
0890                    enum radeon_dpm_forced_level level);
0891 bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
0892 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
0893 u32 ci_dpm_get_current_sclk(struct radeon_device *rdev);
0894 u32 ci_dpm_get_current_mclk(struct radeon_device *rdev);
0895
0896 int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
0897                          u32 *speed);
0898 int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
0899                          u32 speed);
0900 u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev);
0901 void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode);
0902
0903 int kv_dpm_init(struct radeon_device *rdev);
0904 int kv_dpm_enable(struct radeon_device *rdev);
0905 int kv_dpm_late_enable(struct radeon_device *rdev);
0906 void kv_dpm_disable(struct radeon_device *rdev);
0907 int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
0908 int kv_dpm_set_power_state(struct radeon_device *rdev);
0909 void kv_dpm_post_set_power_state(struct radeon_device *rdev);
0910 void kv_dpm_setup_asic(struct radeon_device *rdev);
0911 void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
0912 void kv_dpm_fini(struct radeon_device *rdev);
0913 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
0914 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
0915 void kv_dpm_print_power_state(struct radeon_device *rdev,
0916                   struct radeon_ps *ps);
0917 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
0918                             struct seq_file *m);
0919 int kv_dpm_force_performance_level(struct radeon_device *rdev,
0920                    enum radeon_dpm_forced_level level);
0921 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
0922 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
0923 u32 kv_dpm_get_current_sclk(struct radeon_device *rdev);
0924 u32 kv_dpm_get_current_mclk(struct radeon_device *rdev);
0925
0926 /* uvd v1.0 */
0927 uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
0928                            struct radeon_ring *ring);
0929 uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
0930                            struct radeon_ring *ring);
0931 void uvd_v1_0_set_wptr(struct radeon_device *rdev,
0932                        struct radeon_ring *ring);
0933 int uvd_v1_0_resume(struct radeon_device *rdev);
0934
0935 int uvd_v1_0_init(struct radeon_device *rdev);
0936 void uvd_v1_0_fini(struct radeon_device *rdev);
0937 int uvd_v1_0_start(struct radeon_device *rdev);
0938 void uvd_v1_0_stop(struct radeon_device *rdev);
0939
0940 int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
0941 void uvd_v1_0_fence_emit(struct radeon_device *rdev,
0942              struct radeon_fence *fence);
0943 int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
0944 bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
0945                  struct radeon_ring *ring,
0946                  struct radeon_semaphore *semaphore,
0947                  bool emit_wait);
0948 void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
0949
0950 /* uvd v2.2 */
0951 int uvd_v2_2_resume(struct radeon_device *rdev);
0952 void uvd_v2_2_fence_emit(struct radeon_device *rdev,
0953              struct radeon_fence *fence);
0954 bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev,
0955                  struct radeon_ring *ring,
0956                  struct radeon_semaphore *semaphore,
0957                  bool emit_wait);
0958
0959 /* uvd v3.1 */
0960 bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
0961                  struct radeon_ring *ring,
0962                  struct radeon_semaphore *semaphore,
0963                  bool emit_wait);
0964
0965 /* uvd v4.2 */
0966 int uvd_v4_2_resume(struct radeon_device *rdev);
0967
0968 /* vce v1.0 */
0969 uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
0970                struct radeon_ring *ring);
0971 uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
0972                struct radeon_ring *ring);
0973 void vce_v1_0_set_wptr(struct radeon_device *rdev,
0974                struct radeon_ring *ring);
0975 int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data);
0976 unsigned vce_v1_0_bo_size(struct radeon_device *rdev);
0977 int vce_v1_0_resume(struct radeon_device *rdev);
0978 int vce_v1_0_init(struct radeon_device *rdev);
0979 int vce_v1_0_start(struct radeon_device *rdev);
0980
0981 /* vce v2.0 */
0982 unsigned vce_v2_0_bo_size(struct radeon_device *rdev);
0983 int vce_v2_0_resume(struct radeon_device *rdev);
0984
0985 #endif