drm/radeon/radeon_asic.c

0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028
0029 #include <linux/console.h>
0030 #include <linux/pci.h>
0031 #include <linux/vgaarb.h>
0032
0033 #include <drm/drm_crtc_helper.h>
0034 #include <drm/radeon_drm.h>
0035
0036 #include "atom.h"
0037 #include "radeon.h"
0038 #include "radeon_asic.h"
0039 #include "radeon_reg.h"
0040
0041 /*
0042  * Registers accessors functions.
0043  */
0044 /**
0045  * radeon_invalid_rreg - dummy reg read function
0046  *
0047  * @rdev: radeon device pointer
0048  * @reg: offset of register
0049  *
0050  * Dummy register read function.  Used for register blocks
0051  * that certain asics don't have (all asics).
0052  * Returns the value in the register.
0053  */
0054 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
0055 {
0056     DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
0057     BUG_ON(1);
0058     return 0;
0059 }
0060
0061 /**
0062  * radeon_invalid_wreg - dummy reg write function
0063  *
0064  * @rdev: radeon device pointer
0065  * @reg: offset of register
0066  * @v: value to write to the register
0067  *
0068  * Dummy register read function.  Used for register blocks
0069  * that certain asics don't have (all asics).
0070  */
0071 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
0072 {
0073     DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
0074           reg, v);
0075     BUG_ON(1);
0076 }
0077
0078 /**
0079  * radeon_register_accessor_init - sets up the register accessor callbacks
0080  *
0081  * @rdev: radeon device pointer
0082  *
0083  * Sets up the register accessor callbacks for various register
0084  * apertures.  Not all asics have all apertures (all asics).
0085  */
0086 static void radeon_register_accessor_init(struct radeon_device *rdev)
0087 {
0088     rdev->mc_rreg = &radeon_invalid_rreg;
0089     rdev->mc_wreg = &radeon_invalid_wreg;
0090     rdev->pll_rreg = &radeon_invalid_rreg;
0091     rdev->pll_wreg = &radeon_invalid_wreg;
0092     rdev->pciep_rreg = &radeon_invalid_rreg;
0093     rdev->pciep_wreg = &radeon_invalid_wreg;
0094
0095     /* Don't change order as we are overridding accessor. */
0096     if (rdev->family < CHIP_RV515) {
0097         rdev->pcie_reg_mask = 0xff;
0098     } else {
0099         rdev->pcie_reg_mask = 0x7ff;
0100     }
0101     /* FIXME: not sure here */
0102     if (rdev->family <= CHIP_R580) {
0103         rdev->pll_rreg = &r100_pll_rreg;
0104         rdev->pll_wreg = &r100_pll_wreg;
0105     }
0106     if (rdev->family >= CHIP_R420) {
0107         rdev->mc_rreg = &r420_mc_rreg;
0108         rdev->mc_wreg = &r420_mc_wreg;
0109     }
0110     if (rdev->family >= CHIP_RV515) {
0111         rdev->mc_rreg = &rv515_mc_rreg;
0112         rdev->mc_wreg = &rv515_mc_wreg;
0113     }
0114     if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
0115         rdev->mc_rreg = &rs400_mc_rreg;
0116         rdev->mc_wreg = &rs400_mc_wreg;
0117     }
0118     if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
0119         rdev->mc_rreg = &rs690_mc_rreg;
0120         rdev->mc_wreg = &rs690_mc_wreg;
0121     }
0122     if (rdev->family == CHIP_RS600) {
0123         rdev->mc_rreg = &rs600_mc_rreg;
0124         rdev->mc_wreg = &rs600_mc_wreg;
0125     }
0126     if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
0127         rdev->mc_rreg = &rs780_mc_rreg;
0128         rdev->mc_wreg = &rs780_mc_wreg;
0129     }
0130
0131     if (rdev->family >= CHIP_BONAIRE) {
0132         rdev->pciep_rreg = &cik_pciep_rreg;
0133         rdev->pciep_wreg = &cik_pciep_wreg;
0134     } else if (rdev->family >= CHIP_R600) {
0135         rdev->pciep_rreg = &r600_pciep_rreg;
0136         rdev->pciep_wreg = &r600_pciep_wreg;
0137     }
0138 }
0139
0140 static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev,
0141                             u32 reg, u32 *val)
0142 {
0143     return -EINVAL;
0144 }
0145
0146 /* helper to disable agp */
0147 /**
0148  * radeon_agp_disable - AGP disable helper function
0149  *
0150  * @rdev: radeon device pointer
0151  *
0152  * Removes AGP flags and changes the gart callbacks on AGP
0153  * cards when using the internal gart rather than AGP (all asics).
0154  */
0155 void radeon_agp_disable(struct radeon_device *rdev)
0156 {
0157     rdev->flags &= ~RADEON_IS_AGP;
0158     if (rdev->family >= CHIP_R600) {
0159         DRM_INFO("Forcing AGP to PCIE mode\n");
0160         rdev->flags |= RADEON_IS_PCIE;
0161     } else if (rdev->family >= CHIP_RV515 ||
0162             rdev->family == CHIP_RV380 ||
0163             rdev->family == CHIP_RV410 ||
0164             rdev->family == CHIP_R423) {
0165         DRM_INFO("Forcing AGP to PCIE mode\n");
0166         rdev->flags |= RADEON_IS_PCIE;
0167         rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
0168         rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
0169         rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
0170     } else {
0171         DRM_INFO("Forcing AGP to PCI mode\n");
0172         rdev->flags |= RADEON_IS_PCI;
0173         rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
0174         rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
0175         rdev->asic->gart.set_page = &r100_pci_gart_set_page;
0176     }
0177     rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
0178 }
0179
0180 /*
0181  * ASIC
0182  */
0183
0184 static const struct radeon_asic_ring r100_gfx_ring = {
0185     .ib_execute = &r100_ring_ib_execute,
0186     .emit_fence = &r100_fence_ring_emit,
0187     .emit_semaphore = &r100_semaphore_ring_emit,
0188     .cs_parse = &r100_cs_parse,
0189     .ring_start = &r100_ring_start,
0190     .ring_test = &r100_ring_test,
0191     .ib_test = &r100_ib_test,
0192     .is_lockup = &r100_gpu_is_lockup,
0193     .get_rptr = &r100_gfx_get_rptr,
0194     .get_wptr = &r100_gfx_get_wptr,
0195     .set_wptr = &r100_gfx_set_wptr,
0196 };
0197
0198 static struct radeon_asic r100_asic = {
0199     .init = &r100_init,
0200     .fini = &r100_fini,
0201     .suspend = &r100_suspend,
0202     .resume = &r100_resume,
0203     .vga_set_state = &r100_vga_set_state,
0204     .asic_reset = &r100_asic_reset,
0205     .mmio_hdp_flush = NULL,
0206     .gui_idle = &r100_gui_idle,
0207     .mc_wait_for_idle = &r100_mc_wait_for_idle,
0208     .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
0209     .gart = {
0210         .tlb_flush = &r100_pci_gart_tlb_flush,
0211         .get_page_entry = &r100_pci_gart_get_page_entry,
0212         .set_page = &r100_pci_gart_set_page,
0213     },
0214     .ring = {
0215         [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
0216     },
0217     .irq = {
0218         .set = &r100_irq_set,
0219         .process = &r100_irq_process,
0220     },
0221     .display = {
0222         .bandwidth_update = &r100_bandwidth_update,
0223         .get_vblank_counter = &r100_get_vblank_counter,
0224         .wait_for_vblank = &r100_wait_for_vblank,
0225         .set_backlight_level = &radeon_legacy_set_backlight_level,
0226         .get_backlight_level = &radeon_legacy_get_backlight_level,
0227     },
0228     .copy = {
0229         .blit = &r100_copy_blit,
0230         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0231         .dma = NULL,
0232         .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0233         .copy = &r100_copy_blit,
0234         .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0235     },
0236     .surface = {
0237         .set_reg = r100_set_surface_reg,
0238         .clear_reg = r100_clear_surface_reg,
0239     },
0240     .hpd = {
0241         .init = &r100_hpd_init,
0242         .fini = &r100_hpd_fini,
0243         .sense = &r100_hpd_sense,
0244         .set_polarity = &r100_hpd_set_polarity,
0245     },
0246     .pm = {
0247         .misc = &r100_pm_misc,
0248         .prepare = &r100_pm_prepare,
0249         .finish = &r100_pm_finish,
0250         .init_profile = &r100_pm_init_profile,
0251         .get_dynpm_state = &r100_pm_get_dynpm_state,
0252         .get_engine_clock = &radeon_legacy_get_engine_clock,
0253         .set_engine_clock = &radeon_legacy_set_engine_clock,
0254         .get_memory_clock = &radeon_legacy_get_memory_clock,
0255         .set_memory_clock = NULL,
0256         .get_pcie_lanes = NULL,
0257         .set_pcie_lanes = NULL,
0258         .set_clock_gating = &radeon_legacy_set_clock_gating,
0259     },
0260     .pflip = {
0261         .page_flip = &r100_page_flip,
0262         .page_flip_pending = &r100_page_flip_pending,
0263     },
0264 };
0265
0266 static struct radeon_asic r200_asic = {
0267     .init = &r100_init,
0268     .fini = &r100_fini,
0269     .suspend = &r100_suspend,
0270     .resume = &r100_resume,
0271     .vga_set_state = &r100_vga_set_state,
0272     .asic_reset = &r100_asic_reset,
0273     .mmio_hdp_flush = NULL,
0274     .gui_idle = &r100_gui_idle,
0275     .mc_wait_for_idle = &r100_mc_wait_for_idle,
0276     .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
0277     .gart = {
0278         .tlb_flush = &r100_pci_gart_tlb_flush,
0279         .get_page_entry = &r100_pci_gart_get_page_entry,
0280         .set_page = &r100_pci_gart_set_page,
0281     },
0282     .ring = {
0283         [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
0284     },
0285     .irq = {
0286         .set = &r100_irq_set,
0287         .process = &r100_irq_process,
0288     },
0289     .display = {
0290         .bandwidth_update = &r100_bandwidth_update,
0291         .get_vblank_counter = &r100_get_vblank_counter,
0292         .wait_for_vblank = &r100_wait_for_vblank,
0293         .set_backlight_level = &radeon_legacy_set_backlight_level,
0294         .get_backlight_level = &radeon_legacy_get_backlight_level,
0295     },
0296     .copy = {
0297         .blit = &r100_copy_blit,
0298         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0299         .dma = &r200_copy_dma,
0300         .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0301         .copy = &r100_copy_blit,
0302         .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0303     },
0304     .surface = {
0305         .set_reg = r100_set_surface_reg,
0306         .clear_reg = r100_clear_surface_reg,
0307     },
0308     .hpd = {
0309         .init = &r100_hpd_init,
0310         .fini = &r100_hpd_fini,
0311         .sense = &r100_hpd_sense,
0312         .set_polarity = &r100_hpd_set_polarity,
0313     },
0314     .pm = {
0315         .misc = &r100_pm_misc,
0316         .prepare = &r100_pm_prepare,
0317         .finish = &r100_pm_finish,
0318         .init_profile = &r100_pm_init_profile,
0319         .get_dynpm_state = &r100_pm_get_dynpm_state,
0320         .get_engine_clock = &radeon_legacy_get_engine_clock,
0321         .set_engine_clock = &radeon_legacy_set_engine_clock,
0322         .get_memory_clock = &radeon_legacy_get_memory_clock,
0323         .set_memory_clock = NULL,
0324         .get_pcie_lanes = NULL,
0325         .set_pcie_lanes = NULL,
0326         .set_clock_gating = &radeon_legacy_set_clock_gating,
0327     },
0328     .pflip = {
0329         .page_flip = &r100_page_flip,
0330         .page_flip_pending = &r100_page_flip_pending,
0331     },
0332 };
0333
0334 static const struct radeon_asic_ring r300_gfx_ring = {
0335     .ib_execute = &r100_ring_ib_execute,
0336     .emit_fence = &r300_fence_ring_emit,
0337     .emit_semaphore = &r100_semaphore_ring_emit,
0338     .cs_parse = &r300_cs_parse,
0339     .ring_start = &r300_ring_start,
0340     .ring_test = &r100_ring_test,
0341     .ib_test = &r100_ib_test,
0342     .is_lockup = &r100_gpu_is_lockup,
0343     .get_rptr = &r100_gfx_get_rptr,
0344     .get_wptr = &r100_gfx_get_wptr,
0345     .set_wptr = &r100_gfx_set_wptr,
0346 };
0347
0348 static const struct radeon_asic_ring rv515_gfx_ring = {
0349     .ib_execute = &r100_ring_ib_execute,
0350     .emit_fence = &r300_fence_ring_emit,
0351     .emit_semaphore = &r100_semaphore_ring_emit,
0352     .cs_parse = &r300_cs_parse,
0353     .ring_start = &rv515_ring_start,
0354     .ring_test = &r100_ring_test,
0355     .ib_test = &r100_ib_test,
0356     .is_lockup = &r100_gpu_is_lockup,
0357     .get_rptr = &r100_gfx_get_rptr,
0358     .get_wptr = &r100_gfx_get_wptr,
0359     .set_wptr = &r100_gfx_set_wptr,
0360 };
0361
0362 static struct radeon_asic r300_asic = {
0363     .init = &r300_init,
0364     .fini = &r300_fini,
0365     .suspend = &r300_suspend,
0366     .resume = &r300_resume,
0367     .vga_set_state = &r100_vga_set_state,
0368     .asic_reset = &r300_asic_reset,
0369     .mmio_hdp_flush = NULL,
0370     .gui_idle = &r100_gui_idle,
0371     .mc_wait_for_idle = &r300_mc_wait_for_idle,
0372     .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
0373     .gart = {
0374         .tlb_flush = &r100_pci_gart_tlb_flush,
0375         .get_page_entry = &r100_pci_gart_get_page_entry,
0376         .set_page = &r100_pci_gart_set_page,
0377     },
0378     .ring = {
0379         [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
0380     },
0381     .irq = {
0382         .set = &r100_irq_set,
0383         .process = &r100_irq_process,
0384     },
0385     .display = {
0386         .bandwidth_update = &r100_bandwidth_update,
0387         .get_vblank_counter = &r100_get_vblank_counter,
0388         .wait_for_vblank = &r100_wait_for_vblank,
0389         .set_backlight_level = &radeon_legacy_set_backlight_level,
0390         .get_backlight_level = &radeon_legacy_get_backlight_level,
0391     },
0392     .copy = {
0393         .blit = &r100_copy_blit,
0394         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0395         .dma = &r200_copy_dma,
0396         .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0397         .copy = &r100_copy_blit,
0398         .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0399     },
0400     .surface = {
0401         .set_reg = r100_set_surface_reg,
0402         .clear_reg = r100_clear_surface_reg,
0403     },
0404     .hpd = {
0405         .init = &r100_hpd_init,
0406         .fini = &r100_hpd_fini,
0407         .sense = &r100_hpd_sense,
0408         .set_polarity = &r100_hpd_set_polarity,
0409     },
0410     .pm = {
0411         .misc = &r100_pm_misc,
0412         .prepare = &r100_pm_prepare,
0413         .finish = &r100_pm_finish,
0414         .init_profile = &r100_pm_init_profile,
0415         .get_dynpm_state = &r100_pm_get_dynpm_state,
0416         .get_engine_clock = &radeon_legacy_get_engine_clock,
0417         .set_engine_clock = &radeon_legacy_set_engine_clock,
0418         .get_memory_clock = &radeon_legacy_get_memory_clock,
0419         .set_memory_clock = NULL,
0420         .get_pcie_lanes = &rv370_get_pcie_lanes,
0421         .set_pcie_lanes = &rv370_set_pcie_lanes,
0422         .set_clock_gating = &radeon_legacy_set_clock_gating,
0423     },
0424     .pflip = {
0425         .page_flip = &r100_page_flip,
0426         .page_flip_pending = &r100_page_flip_pending,
0427     },
0428 };
0429
0430 static struct radeon_asic r300_asic_pcie = {
0431     .init = &r300_init,
0432     .fini = &r300_fini,
0433     .suspend = &r300_suspend,
0434     .resume = &r300_resume,
0435     .vga_set_state = &r100_vga_set_state,
0436     .asic_reset = &r300_asic_reset,
0437     .mmio_hdp_flush = NULL,
0438     .gui_idle = &r100_gui_idle,
0439     .mc_wait_for_idle = &r300_mc_wait_for_idle,
0440     .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
0441     .gart = {
0442         .tlb_flush = &rv370_pcie_gart_tlb_flush,
0443         .get_page_entry = &rv370_pcie_gart_get_page_entry,
0444         .set_page = &rv370_pcie_gart_set_page,
0445     },
0446     .ring = {
0447         [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
0448     },
0449     .irq = {
0450         .set = &r100_irq_set,
0451         .process = &r100_irq_process,
0452     },
0453     .display = {
0454         .bandwidth_update = &r100_bandwidth_update,
0455         .get_vblank_counter = &r100_get_vblank_counter,
0456         .wait_for_vblank = &r100_wait_for_vblank,
0457         .set_backlight_level = &radeon_legacy_set_backlight_level,
0458         .get_backlight_level = &radeon_legacy_get_backlight_level,
0459     },
0460     .copy = {
0461         .blit = &r100_copy_blit,
0462         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0463         .dma = &r200_copy_dma,
0464         .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0465         .copy = &r100_copy_blit,
0466         .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0467     },
0468     .surface = {
0469         .set_reg = r100_set_surface_reg,
0470         .clear_reg = r100_clear_surface_reg,
0471     },
0472     .hpd = {
0473         .init = &r100_hpd_init,
0474         .fini = &r100_hpd_fini,
0475         .sense = &r100_hpd_sense,
0476         .set_polarity = &r100_hpd_set_polarity,
0477     },
0478     .pm = {
0479         .misc = &r100_pm_misc,
0480         .prepare = &r100_pm_prepare,
0481         .finish = &r100_pm_finish,
0482         .init_profile = &r100_pm_init_profile,
0483         .get_dynpm_state = &r100_pm_get_dynpm_state,
0484         .get_engine_clock = &radeon_legacy_get_engine_clock,
0485         .set_engine_clock = &radeon_legacy_set_engine_clock,
0486         .get_memory_clock = &radeon_legacy_get_memory_clock,
0487         .set_memory_clock = NULL,
0488         .get_pcie_lanes = &rv370_get_pcie_lanes,
0489         .set_pcie_lanes = &rv370_set_pcie_lanes,
0490         .set_clock_gating = &radeon_legacy_set_clock_gating,
0491     },
0492     .pflip = {
0493         .page_flip = &r100_page_flip,
0494         .page_flip_pending = &r100_page_flip_pending,
0495     },
0496 };
0497
0498 static struct radeon_asic r420_asic = {
0499     .init = &r420_init,
0500     .fini = &r420_fini,
0501     .suspend = &r420_suspend,
0502     .resume = &r420_resume,
0503     .vga_set_state = &r100_vga_set_state,
0504     .asic_reset = &r300_asic_reset,
0505     .mmio_hdp_flush = NULL,
0506     .gui_idle = &r100_gui_idle,
0507     .mc_wait_for_idle = &r300_mc_wait_for_idle,
0508     .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
0509     .gart = {
0510         .tlb_flush = &rv370_pcie_gart_tlb_flush,
0511         .get_page_entry = &rv370_pcie_gart_get_page_entry,
0512         .set_page = &rv370_pcie_gart_set_page,
0513     },
0514     .ring = {
0515         [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
0516     },
0517     .irq = {
0518         .set = &r100_irq_set,
0519         .process = &r100_irq_process,
0520     },
0521     .display = {
0522         .bandwidth_update = &r100_bandwidth_update,
0523         .get_vblank_counter = &r100_get_vblank_counter,
0524         .wait_for_vblank = &r100_wait_for_vblank,
0525         .set_backlight_level = &atombios_set_backlight_level,
0526         .get_backlight_level = &atombios_get_backlight_level,
0527     },
0528     .copy = {
0529         .blit = &r100_copy_blit,
0530         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0531         .dma = &r200_copy_dma,
0532         .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0533         .copy = &r100_copy_blit,
0534         .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0535     },
0536     .surface = {
0537         .set_reg = r100_set_surface_reg,
0538         .clear_reg = r100_clear_surface_reg,
0539     },
0540     .hpd = {
0541         .init = &r100_hpd_init,
0542         .fini = &r100_hpd_fini,
0543         .sense = &r100_hpd_sense,
0544         .set_polarity = &r100_hpd_set_polarity,
0545     },
0546     .pm = {
0547         .misc = &r100_pm_misc,
0548         .prepare = &r100_pm_prepare,
0549         .finish = &r100_pm_finish,
0550         .init_profile = &r420_pm_init_profile,
0551         .get_dynpm_state = &r100_pm_get_dynpm_state,
0552         .get_engine_clock = &radeon_atom_get_engine_clock,
0553         .set_engine_clock = &radeon_atom_set_engine_clock,
0554         .get_memory_clock = &radeon_atom_get_memory_clock,
0555         .set_memory_clock = &radeon_atom_set_memory_clock,
0556         .get_pcie_lanes = &rv370_get_pcie_lanes,
0557         .set_pcie_lanes = &rv370_set_pcie_lanes,
0558         .set_clock_gating = &radeon_atom_set_clock_gating,
0559     },
0560     .pflip = {
0561         .page_flip = &r100_page_flip,
0562         .page_flip_pending = &r100_page_flip_pending,
0563     },
0564 };
0565
0566 static struct radeon_asic rs400_asic = {
0567     .init = &rs400_init,
0568     .fini = &rs400_fini,
0569     .suspend = &rs400_suspend,
0570     .resume = &rs400_resume,
0571     .vga_set_state = &r100_vga_set_state,
0572     .asic_reset = &r300_asic_reset,
0573     .mmio_hdp_flush = NULL,
0574     .gui_idle = &r100_gui_idle,
0575     .mc_wait_for_idle = &rs400_mc_wait_for_idle,
0576     .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
0577     .gart = {
0578         .tlb_flush = &rs400_gart_tlb_flush,
0579         .get_page_entry = &rs400_gart_get_page_entry,
0580         .set_page = &rs400_gart_set_page,
0581     },
0582     .ring = {
0583         [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
0584     },
0585     .irq = {
0586         .set = &r100_irq_set,
0587         .process = &r100_irq_process,
0588     },
0589     .display = {
0590         .bandwidth_update = &r100_bandwidth_update,
0591         .get_vblank_counter = &r100_get_vblank_counter,
0592         .wait_for_vblank = &r100_wait_for_vblank,
0593         .set_backlight_level = &radeon_legacy_set_backlight_level,
0594         .get_backlight_level = &radeon_legacy_get_backlight_level,
0595     },
0596     .copy = {
0597         .blit = &r100_copy_blit,
0598         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0599         .dma = &r200_copy_dma,
0600         .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0601         .copy = &r100_copy_blit,
0602         .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0603     },
0604     .surface = {
0605         .set_reg = r100_set_surface_reg,
0606         .clear_reg = r100_clear_surface_reg,
0607     },
0608     .hpd = {
0609         .init = &r100_hpd_init,
0610         .fini = &r100_hpd_fini,
0611         .sense = &r100_hpd_sense,
0612         .set_polarity = &r100_hpd_set_polarity,
0613     },
0614     .pm = {
0615         .misc = &r100_pm_misc,
0616         .prepare = &r100_pm_prepare,
0617         .finish = &r100_pm_finish,
0618         .init_profile = &r100_pm_init_profile,
0619         .get_dynpm_state = &r100_pm_get_dynpm_state,
0620         .get_engine_clock = &radeon_legacy_get_engine_clock,
0621         .set_engine_clock = &radeon_legacy_set_engine_clock,
0622         .get_memory_clock = &radeon_legacy_get_memory_clock,
0623         .set_memory_clock = NULL,
0624         .get_pcie_lanes = NULL,
0625         .set_pcie_lanes = NULL,
0626         .set_clock_gating = &radeon_legacy_set_clock_gating,
0627     },
0628     .pflip = {
0629         .page_flip = &r100_page_flip,
0630         .page_flip_pending = &r100_page_flip_pending,
0631     },
0632 };
0633
0634 static struct radeon_asic rs600_asic = {
0635     .init = &rs600_init,
0636     .fini = &rs600_fini,
0637     .suspend = &rs600_suspend,
0638     .resume = &rs600_resume,
0639     .vga_set_state = &r100_vga_set_state,
0640     .asic_reset = &rs600_asic_reset,
0641     .mmio_hdp_flush = NULL,
0642     .gui_idle = &r100_gui_idle,
0643     .mc_wait_for_idle = &rs600_mc_wait_for_idle,
0644     .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
0645     .gart = {
0646         .tlb_flush = &rs600_gart_tlb_flush,
0647         .get_page_entry = &rs600_gart_get_page_entry,
0648         .set_page = &rs600_gart_set_page,
0649     },
0650     .ring = {
0651         [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
0652     },
0653     .irq = {
0654         .set = &rs600_irq_set,
0655         .process = &rs600_irq_process,
0656     },
0657     .display = {
0658         .bandwidth_update = &rs600_bandwidth_update,
0659         .get_vblank_counter = &rs600_get_vblank_counter,
0660         .wait_for_vblank = &avivo_wait_for_vblank,
0661         .set_backlight_level = &atombios_set_backlight_level,
0662         .get_backlight_level = &atombios_get_backlight_level,
0663     },
0664     .copy = {
0665         .blit = &r100_copy_blit,
0666         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0667         .dma = &r200_copy_dma,
0668         .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0669         .copy = &r100_copy_blit,
0670         .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0671     },
0672     .surface = {
0673         .set_reg = r100_set_surface_reg,
0674         .clear_reg = r100_clear_surface_reg,
0675     },
0676     .hpd = {
0677         .init = &rs600_hpd_init,
0678         .fini = &rs600_hpd_fini,
0679         .sense = &rs600_hpd_sense,
0680         .set_polarity = &rs600_hpd_set_polarity,
0681     },
0682     .pm = {
0683         .misc = &rs600_pm_misc,
0684         .prepare = &rs600_pm_prepare,
0685         .finish = &rs600_pm_finish,
0686         .init_profile = &r420_pm_init_profile,
0687         .get_dynpm_state = &r100_pm_get_dynpm_state,
0688         .get_engine_clock = &radeon_atom_get_engine_clock,
0689         .set_engine_clock = &radeon_atom_set_engine_clock,
0690         .get_memory_clock = &radeon_atom_get_memory_clock,
0691         .set_memory_clock = &radeon_atom_set_memory_clock,
0692         .get_pcie_lanes = NULL,
0693         .set_pcie_lanes = NULL,
0694         .set_clock_gating = &radeon_atom_set_clock_gating,
0695     },
0696     .pflip = {
0697         .page_flip = &rs600_page_flip,
0698         .page_flip_pending = &rs600_page_flip_pending,
0699     },
0700 };
0701
0702 static struct radeon_asic rs690_asic = {
0703     .init = &rs690_init,
0704     .fini = &rs690_fini,
0705     .suspend = &rs690_suspend,
0706     .resume = &rs690_resume,
0707     .vga_set_state = &r100_vga_set_state,
0708     .asic_reset = &rs600_asic_reset,
0709     .mmio_hdp_flush = NULL,
0710     .gui_idle = &r100_gui_idle,
0711     .mc_wait_for_idle = &rs690_mc_wait_for_idle,
0712     .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
0713     .gart = {
0714         .tlb_flush = &rs400_gart_tlb_flush,
0715         .get_page_entry = &rs400_gart_get_page_entry,
0716         .set_page = &rs400_gart_set_page,
0717     },
0718     .ring = {
0719         [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
0720     },
0721     .irq = {
0722         .set = &rs600_irq_set,
0723         .process = &rs600_irq_process,
0724     },
0725     .display = {
0726         .get_vblank_counter = &rs600_get_vblank_counter,
0727         .bandwidth_update = &rs690_bandwidth_update,
0728         .wait_for_vblank = &avivo_wait_for_vblank,
0729         .set_backlight_level = &atombios_set_backlight_level,
0730         .get_backlight_level = &atombios_get_backlight_level,
0731     },
0732     .copy = {
0733         .blit = &r100_copy_blit,
0734         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0735         .dma = &r200_copy_dma,
0736         .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0737         .copy = &r200_copy_dma,
0738         .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0739     },
0740     .surface = {
0741         .set_reg = r100_set_surface_reg,
0742         .clear_reg = r100_clear_surface_reg,
0743     },
0744     .hpd = {
0745         .init = &rs600_hpd_init,
0746         .fini = &rs600_hpd_fini,
0747         .sense = &rs600_hpd_sense,
0748         .set_polarity = &rs600_hpd_set_polarity,
0749     },
0750     .pm = {
0751         .misc = &rs600_pm_misc,
0752         .prepare = &rs600_pm_prepare,
0753         .finish = &rs600_pm_finish,
0754         .init_profile = &r420_pm_init_profile,
0755         .get_dynpm_state = &r100_pm_get_dynpm_state,
0756         .get_engine_clock = &radeon_atom_get_engine_clock,
0757         .set_engine_clock = &radeon_atom_set_engine_clock,
0758         .get_memory_clock = &radeon_atom_get_memory_clock,
0759         .set_memory_clock = &radeon_atom_set_memory_clock,
0760         .get_pcie_lanes = NULL,
0761         .set_pcie_lanes = NULL,
0762         .set_clock_gating = &radeon_atom_set_clock_gating,
0763     },
0764     .pflip = {
0765         .page_flip = &rs600_page_flip,
0766         .page_flip_pending = &rs600_page_flip_pending,
0767     },
0768 };
0769
0770 static struct radeon_asic rv515_asic = {
0771     .init = &rv515_init,
0772     .fini = &rv515_fini,
0773     .suspend = &rv515_suspend,
0774     .resume = &rv515_resume,
0775     .vga_set_state = &r100_vga_set_state,
0776     .asic_reset = &rs600_asic_reset,
0777     .mmio_hdp_flush = NULL,
0778     .gui_idle = &r100_gui_idle,
0779     .mc_wait_for_idle = &rv515_mc_wait_for_idle,
0780     .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
0781     .gart = {
0782         .tlb_flush = &rv370_pcie_gart_tlb_flush,
0783         .get_page_entry = &rv370_pcie_gart_get_page_entry,
0784         .set_page = &rv370_pcie_gart_set_page,
0785     },
0786     .ring = {
0787         [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
0788     },
0789     .irq = {
0790         .set = &rs600_irq_set,
0791         .process = &rs600_irq_process,
0792     },
0793     .display = {
0794         .get_vblank_counter = &rs600_get_vblank_counter,
0795         .bandwidth_update = &rv515_bandwidth_update,
0796         .wait_for_vblank = &avivo_wait_for_vblank,
0797         .set_backlight_level = &atombios_set_backlight_level,
0798         .get_backlight_level = &atombios_get_backlight_level,
0799     },
0800     .copy = {
0801         .blit = &r100_copy_blit,
0802         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0803         .dma = &r200_copy_dma,
0804         .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0805         .copy = &r100_copy_blit,
0806         .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0807     },
0808     .surface = {
0809         .set_reg = r100_set_surface_reg,
0810         .clear_reg = r100_clear_surface_reg,
0811     },
0812     .hpd = {
0813         .init = &rs600_hpd_init,
0814         .fini = &rs600_hpd_fini,
0815         .sense = &rs600_hpd_sense,
0816         .set_polarity = &rs600_hpd_set_polarity,
0817     },
0818     .pm = {
0819         .misc = &rs600_pm_misc,
0820         .prepare = &rs600_pm_prepare,
0821         .finish = &rs600_pm_finish,
0822         .init_profile = &r420_pm_init_profile,
0823         .get_dynpm_state = &r100_pm_get_dynpm_state,
0824         .get_engine_clock = &radeon_atom_get_engine_clock,
0825         .set_engine_clock = &radeon_atom_set_engine_clock,
0826         .get_memory_clock = &radeon_atom_get_memory_clock,
0827         .set_memory_clock = &radeon_atom_set_memory_clock,
0828         .get_pcie_lanes = &rv370_get_pcie_lanes,
0829         .set_pcie_lanes = &rv370_set_pcie_lanes,
0830         .set_clock_gating = &radeon_atom_set_clock_gating,
0831     },
0832     .pflip = {
0833         .page_flip = &rs600_page_flip,
0834         .page_flip_pending = &rs600_page_flip_pending,
0835     },
0836 };
0837
0838 static struct radeon_asic r520_asic = {
0839     .init = &r520_init,
0840     .fini = &rv515_fini,
0841     .suspend = &rv515_suspend,
0842     .resume = &r520_resume,
0843     .vga_set_state = &r100_vga_set_state,
0844     .asic_reset = &rs600_asic_reset,
0845     .mmio_hdp_flush = NULL,
0846     .gui_idle = &r100_gui_idle,
0847     .mc_wait_for_idle = &r520_mc_wait_for_idle,
0848     .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
0849     .gart = {
0850         .tlb_flush = &rv370_pcie_gart_tlb_flush,
0851         .get_page_entry = &rv370_pcie_gart_get_page_entry,
0852         .set_page = &rv370_pcie_gart_set_page,
0853     },
0854     .ring = {
0855         [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
0856     },
0857     .irq = {
0858         .set = &rs600_irq_set,
0859         .process = &rs600_irq_process,
0860     },
0861     .display = {
0862         .bandwidth_update = &rv515_bandwidth_update,
0863         .get_vblank_counter = &rs600_get_vblank_counter,
0864         .wait_for_vblank = &avivo_wait_for_vblank,
0865         .set_backlight_level = &atombios_set_backlight_level,
0866         .get_backlight_level = &atombios_get_backlight_level,
0867     },
0868     .copy = {
0869         .blit = &r100_copy_blit,
0870         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0871         .dma = &r200_copy_dma,
0872         .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0873         .copy = &r100_copy_blit,
0874         .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0875     },
0876     .surface = {
0877         .set_reg = r100_set_surface_reg,
0878         .clear_reg = r100_clear_surface_reg,
0879     },
0880     .hpd = {
0881         .init = &rs600_hpd_init,
0882         .fini = &rs600_hpd_fini,
0883         .sense = &rs600_hpd_sense,
0884         .set_polarity = &rs600_hpd_set_polarity,
0885     },
0886     .pm = {
0887         .misc = &rs600_pm_misc,
0888         .prepare = &rs600_pm_prepare,
0889         .finish = &rs600_pm_finish,
0890         .init_profile = &r420_pm_init_profile,
0891         .get_dynpm_state = &r100_pm_get_dynpm_state,
0892         .get_engine_clock = &radeon_atom_get_engine_clock,
0893         .set_engine_clock = &radeon_atom_set_engine_clock,
0894         .get_memory_clock = &radeon_atom_get_memory_clock,
0895         .set_memory_clock = &radeon_atom_set_memory_clock,
0896         .get_pcie_lanes = &rv370_get_pcie_lanes,
0897         .set_pcie_lanes = &rv370_set_pcie_lanes,
0898         .set_clock_gating = &radeon_atom_set_clock_gating,
0899     },
0900     .pflip = {
0901         .page_flip = &rs600_page_flip,
0902         .page_flip_pending = &rs600_page_flip_pending,
0903     },
0904 };
0905
0906 static const struct radeon_asic_ring r600_gfx_ring = {
0907     .ib_execute = &r600_ring_ib_execute,
0908     .emit_fence = &r600_fence_ring_emit,
0909     .emit_semaphore = &r600_semaphore_ring_emit,
0910     .cs_parse = &r600_cs_parse,
0911     .ring_test = &r600_ring_test,
0912     .ib_test = &r600_ib_test,
0913     .is_lockup = &r600_gfx_is_lockup,
0914     .get_rptr = &r600_gfx_get_rptr,
0915     .get_wptr = &r600_gfx_get_wptr,
0916     .set_wptr = &r600_gfx_set_wptr,
0917 };
0918
0919 static const struct radeon_asic_ring r600_dma_ring = {
0920     .ib_execute = &r600_dma_ring_ib_execute,
0921     .emit_fence = &r600_dma_fence_ring_emit,
0922     .emit_semaphore = &r600_dma_semaphore_ring_emit,
0923     .cs_parse = &r600_dma_cs_parse,
0924     .ring_test = &r600_dma_ring_test,
0925     .ib_test = &r600_dma_ib_test,
0926     .is_lockup = &r600_dma_is_lockup,
0927     .get_rptr = &r600_dma_get_rptr,
0928     .get_wptr = &r600_dma_get_wptr,
0929     .set_wptr = &r600_dma_set_wptr,
0930 };
0931
0932 static struct radeon_asic r600_asic = {
0933     .init = &r600_init,
0934     .fini = &r600_fini,
0935     .suspend = &r600_suspend,
0936     .resume = &r600_resume,
0937     .vga_set_state = &r600_vga_set_state,
0938     .asic_reset = &r600_asic_reset,
0939     .mmio_hdp_flush = r600_mmio_hdp_flush,
0940     .gui_idle = &r600_gui_idle,
0941     .mc_wait_for_idle = &r600_mc_wait_for_idle,
0942     .get_xclk = &r600_get_xclk,
0943     .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
0944     .get_allowed_info_register = r600_get_allowed_info_register,
0945     .gart = {
0946         .tlb_flush = &r600_pcie_gart_tlb_flush,
0947         .get_page_entry = &rs600_gart_get_page_entry,
0948         .set_page = &rs600_gart_set_page,
0949     },
0950     .ring = {
0951         [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
0952         [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
0953     },
0954     .irq = {
0955         .set = &r600_irq_set,
0956         .process = &r600_irq_process,
0957     },
0958     .display = {
0959         .bandwidth_update = &rv515_bandwidth_update,
0960         .get_vblank_counter = &rs600_get_vblank_counter,
0961         .wait_for_vblank = &avivo_wait_for_vblank,
0962         .set_backlight_level = &atombios_set_backlight_level,
0963         .get_backlight_level = &atombios_get_backlight_level,
0964     },
0965     .copy = {
0966         .blit = &r600_copy_cpdma,
0967         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0968         .dma = &r600_copy_dma,
0969         .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
0970         .copy = &r600_copy_cpdma,
0971         .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
0972     },
0973     .surface = {
0974         .set_reg = r600_set_surface_reg,
0975         .clear_reg = r600_clear_surface_reg,
0976     },
0977     .hpd = {
0978         .init = &r600_hpd_init,
0979         .fini = &r600_hpd_fini,
0980         .sense = &r600_hpd_sense,
0981         .set_polarity = &r600_hpd_set_polarity,
0982     },
0983     .pm = {
0984         .misc = &r600_pm_misc,
0985         .prepare = &rs600_pm_prepare,
0986         .finish = &rs600_pm_finish,
0987         .init_profile = &r600_pm_init_profile,
0988         .get_dynpm_state = &r600_pm_get_dynpm_state,
0989         .get_engine_clock = &radeon_atom_get_engine_clock,
0990         .set_engine_clock = &radeon_atom_set_engine_clock,
0991         .get_memory_clock = &radeon_atom_get_memory_clock,
0992         .set_memory_clock = &radeon_atom_set_memory_clock,
0993         .get_pcie_lanes = &r600_get_pcie_lanes,
0994         .set_pcie_lanes = &r600_set_pcie_lanes,
0995         .set_clock_gating = NULL,
0996         .get_temperature = &rv6xx_get_temp,
0997     },
0998     .pflip = {
0999         .page_flip = &rs600_page_flip,
1000         .page_flip_pending = &rs600_page_flip_pending,
1001     },
1002 };
1003
1004 static const struct radeon_asic_ring rv6xx_uvd_ring = {
1005     .ib_execute = &uvd_v1_0_ib_execute,
1006     .emit_fence = &uvd_v1_0_fence_emit,
1007     .emit_semaphore = &uvd_v1_0_semaphore_emit,
1008     .cs_parse = &radeon_uvd_cs_parse,
1009     .ring_test = &uvd_v1_0_ring_test,
1010     .ib_test = &uvd_v1_0_ib_test,
1011     .is_lockup = &radeon_ring_test_lockup,
1012     .get_rptr = &uvd_v1_0_get_rptr,
1013     .get_wptr = &uvd_v1_0_get_wptr,
1014     .set_wptr = &uvd_v1_0_set_wptr,
1015 };
1016
1017 static struct radeon_asic rv6xx_asic = {
1018     .init = &r600_init,
1019     .fini = &r600_fini,
1020     .suspend = &r600_suspend,
1021     .resume = &r600_resume,
1022     .vga_set_state = &r600_vga_set_state,
1023     .asic_reset = &r600_asic_reset,
1024     .mmio_hdp_flush = r600_mmio_hdp_flush,
1025     .gui_idle = &r600_gui_idle,
1026     .mc_wait_for_idle = &r600_mc_wait_for_idle,
1027     .get_xclk = &r600_get_xclk,
1028     .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1029     .get_allowed_info_register = r600_get_allowed_info_register,
1030     .gart = {
1031         .tlb_flush = &r600_pcie_gart_tlb_flush,
1032         .get_page_entry = &rs600_gart_get_page_entry,
1033         .set_page = &rs600_gart_set_page,
1034     },
1035     .ring = {
1036         [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1037         [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1038         [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1039     },
1040     .irq = {
1041         .set = &r600_irq_set,
1042         .process = &r600_irq_process,
1043     },
1044     .display = {
1045         .bandwidth_update = &rv515_bandwidth_update,
1046         .get_vblank_counter = &rs600_get_vblank_counter,
1047         .wait_for_vblank = &avivo_wait_for_vblank,
1048         .set_backlight_level = &atombios_set_backlight_level,
1049         .get_backlight_level = &atombios_get_backlight_level,
1050     },
1051     .copy = {
1052         .blit = &r600_copy_cpdma,
1053         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1054         .dma = &r600_copy_dma,
1055         .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1056         .copy = &r600_copy_cpdma,
1057         .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1058     },
1059     .surface = {
1060         .set_reg = r600_set_surface_reg,
1061         .clear_reg = r600_clear_surface_reg,
1062     },
1063     .hpd = {
1064         .init = &r600_hpd_init,
1065         .fini = &r600_hpd_fini,
1066         .sense = &r600_hpd_sense,
1067         .set_polarity = &r600_hpd_set_polarity,
1068     },
1069     .pm = {
1070         .misc = &r600_pm_misc,
1071         .prepare = &rs600_pm_prepare,
1072         .finish = &rs600_pm_finish,
1073         .init_profile = &r600_pm_init_profile,
1074         .get_dynpm_state = &r600_pm_get_dynpm_state,
1075         .get_engine_clock = &radeon_atom_get_engine_clock,
1076         .set_engine_clock = &radeon_atom_set_engine_clock,
1077         .get_memory_clock = &radeon_atom_get_memory_clock,
1078         .set_memory_clock = &radeon_atom_set_memory_clock,
1079         .get_pcie_lanes = &r600_get_pcie_lanes,
1080         .set_pcie_lanes = &r600_set_pcie_lanes,
1081         .set_clock_gating = NULL,
1082         .get_temperature = &rv6xx_get_temp,
1083         .set_uvd_clocks = &r600_set_uvd_clocks,
1084     },
1085     .dpm = {
1086         .init = &rv6xx_dpm_init,
1087         .setup_asic = &rv6xx_setup_asic,
1088         .enable = &rv6xx_dpm_enable,
1089         .late_enable = &r600_dpm_late_enable,
1090         .disable = &rv6xx_dpm_disable,
1091         .pre_set_power_state = &r600_dpm_pre_set_power_state,
1092         .set_power_state = &rv6xx_dpm_set_power_state,
1093         .post_set_power_state = &r600_dpm_post_set_power_state,
1094         .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1095         .fini = &rv6xx_dpm_fini,
1096         .get_sclk = &rv6xx_dpm_get_sclk,
1097         .get_mclk = &rv6xx_dpm_get_mclk,
1098         .print_power_state = &rv6xx_dpm_print_power_state,
1099         .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1100         .force_performance_level = &rv6xx_dpm_force_performance_level,
1101         .get_current_sclk = &rv6xx_dpm_get_current_sclk,
1102         .get_current_mclk = &rv6xx_dpm_get_current_mclk,
1103     },
1104     .pflip = {
1105         .page_flip = &rs600_page_flip,
1106         .page_flip_pending = &rs600_page_flip_pending,
1107     },
1108 };
1109
1110 static struct radeon_asic rs780_asic = {
1111     .init = &r600_init,
1112     .fini = &r600_fini,
1113     .suspend = &r600_suspend,
1114     .resume = &r600_resume,
1115     .vga_set_state = &r600_vga_set_state,
1116     .asic_reset = &r600_asic_reset,
1117     .mmio_hdp_flush = r600_mmio_hdp_flush,
1118     .gui_idle = &r600_gui_idle,
1119     .mc_wait_for_idle = &r600_mc_wait_for_idle,
1120     .get_xclk = &r600_get_xclk,
1121     .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1122     .get_allowed_info_register = r600_get_allowed_info_register,
1123     .gart = {
1124         .tlb_flush = &r600_pcie_gart_tlb_flush,
1125         .get_page_entry = &rs600_gart_get_page_entry,
1126         .set_page = &rs600_gart_set_page,
1127     },
1128     .ring = {
1129         [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1130         [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1131         [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1132     },
1133     .irq = {
1134         .set = &r600_irq_set,
1135         .process = &r600_irq_process,
1136     },
1137     .display = {
1138         .bandwidth_update = &rs690_bandwidth_update,
1139         .get_vblank_counter = &rs600_get_vblank_counter,
1140         .wait_for_vblank = &avivo_wait_for_vblank,
1141         .set_backlight_level = &atombios_set_backlight_level,
1142         .get_backlight_level = &atombios_get_backlight_level,
1143     },
1144     .copy = {
1145         .blit = &r600_copy_cpdma,
1146         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1147         .dma = &r600_copy_dma,
1148         .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1149         .copy = &r600_copy_cpdma,
1150         .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1151     },
1152     .surface = {
1153         .set_reg = r600_set_surface_reg,
1154         .clear_reg = r600_clear_surface_reg,
1155     },
1156     .hpd = {
1157         .init = &r600_hpd_init,
1158         .fini = &r600_hpd_fini,
1159         .sense = &r600_hpd_sense,
1160         .set_polarity = &r600_hpd_set_polarity,
1161     },
1162     .pm = {
1163         .misc = &r600_pm_misc,
1164         .prepare = &rs600_pm_prepare,
1165         .finish = &rs600_pm_finish,
1166         .init_profile = &rs780_pm_init_profile,
1167         .get_dynpm_state = &r600_pm_get_dynpm_state,
1168         .get_engine_clock = &radeon_atom_get_engine_clock,
1169         .set_engine_clock = &radeon_atom_set_engine_clock,
1170         .get_memory_clock = NULL,
1171         .set_memory_clock = NULL,
1172         .get_pcie_lanes = NULL,
1173         .set_pcie_lanes = NULL,
1174         .set_clock_gating = NULL,
1175         .get_temperature = &rv6xx_get_temp,
1176         .set_uvd_clocks = &r600_set_uvd_clocks,
1177     },
1178     .dpm = {
1179         .init = &rs780_dpm_init,
1180         .setup_asic = &rs780_dpm_setup_asic,
1181         .enable = &rs780_dpm_enable,
1182         .late_enable = &r600_dpm_late_enable,
1183         .disable = &rs780_dpm_disable,
1184         .pre_set_power_state = &r600_dpm_pre_set_power_state,
1185         .set_power_state = &rs780_dpm_set_power_state,
1186         .post_set_power_state = &r600_dpm_post_set_power_state,
1187         .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1188         .fini = &rs780_dpm_fini,
1189         .get_sclk = &rs780_dpm_get_sclk,
1190         .get_mclk = &rs780_dpm_get_mclk,
1191         .print_power_state = &rs780_dpm_print_power_state,
1192         .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1193         .force_performance_level = &rs780_dpm_force_performance_level,
1194         .get_current_sclk = &rs780_dpm_get_current_sclk,
1195         .get_current_mclk = &rs780_dpm_get_current_mclk,
1196     },
1197     .pflip = {
1198         .page_flip = &rs600_page_flip,
1199         .page_flip_pending = &rs600_page_flip_pending,
1200     },
1201 };
1202
1203 static const struct radeon_asic_ring rv770_uvd_ring = {
1204     .ib_execute = &uvd_v1_0_ib_execute,
1205     .emit_fence = &uvd_v2_2_fence_emit,
1206     .emit_semaphore = &uvd_v2_2_semaphore_emit,
1207     .cs_parse = &radeon_uvd_cs_parse,
1208     .ring_test = &uvd_v1_0_ring_test,
1209     .ib_test = &uvd_v1_0_ib_test,
1210     .is_lockup = &radeon_ring_test_lockup,
1211     .get_rptr = &uvd_v1_0_get_rptr,
1212     .get_wptr = &uvd_v1_0_get_wptr,
1213     .set_wptr = &uvd_v1_0_set_wptr,
1214 };
1215
1216 static struct radeon_asic rv770_asic = {
1217     .init = &rv770_init,
1218     .fini = &rv770_fini,
1219     .suspend = &rv770_suspend,
1220     .resume = &rv770_resume,
1221     .asic_reset = &r600_asic_reset,
1222     .vga_set_state = &r600_vga_set_state,
1223     .mmio_hdp_flush = r600_mmio_hdp_flush,
1224     .gui_idle = &r600_gui_idle,
1225     .mc_wait_for_idle = &r600_mc_wait_for_idle,
1226     .get_xclk = &rv770_get_xclk,
1227     .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1228     .get_allowed_info_register = r600_get_allowed_info_register,
1229     .gart = {
1230         .tlb_flush = &r600_pcie_gart_tlb_flush,
1231         .get_page_entry = &rs600_gart_get_page_entry,
1232         .set_page = &rs600_gart_set_page,
1233     },
1234     .ring = {
1235         [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1236         [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1237         [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1238     },
1239     .irq = {
1240         .set = &r600_irq_set,
1241         .process = &r600_irq_process,
1242     },
1243     .display = {
1244         .bandwidth_update = &rv515_bandwidth_update,
1245         .get_vblank_counter = &rs600_get_vblank_counter,
1246         .wait_for_vblank = &avivo_wait_for_vblank,
1247         .set_backlight_level = &atombios_set_backlight_level,
1248         .get_backlight_level = &atombios_get_backlight_level,
1249     },
1250     .copy = {
1251         .blit = &r600_copy_cpdma,
1252         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1253         .dma = &rv770_copy_dma,
1254         .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1255         .copy = &rv770_copy_dma,
1256         .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1257     },
1258     .surface = {
1259         .set_reg = r600_set_surface_reg,
1260         .clear_reg = r600_clear_surface_reg,
1261     },
1262     .hpd = {
1263         .init = &r600_hpd_init,
1264         .fini = &r600_hpd_fini,
1265         .sense = &r600_hpd_sense,
1266         .set_polarity = &r600_hpd_set_polarity,
1267     },
1268     .pm = {
1269         .misc = &rv770_pm_misc,
1270         .prepare = &rs600_pm_prepare,
1271         .finish = &rs600_pm_finish,
1272         .init_profile = &r600_pm_init_profile,
1273         .get_dynpm_state = &r600_pm_get_dynpm_state,
1274         .get_engine_clock = &radeon_atom_get_engine_clock,
1275         .set_engine_clock = &radeon_atom_set_engine_clock,
1276         .get_memory_clock = &radeon_atom_get_memory_clock,
1277         .set_memory_clock = &radeon_atom_set_memory_clock,
1278         .get_pcie_lanes = &r600_get_pcie_lanes,
1279         .set_pcie_lanes = &r600_set_pcie_lanes,
1280         .set_clock_gating = &radeon_atom_set_clock_gating,
1281         .set_uvd_clocks = &rv770_set_uvd_clocks,
1282         .get_temperature = &rv770_get_temp,
1283     },
1284     .dpm = {
1285         .init = &rv770_dpm_init,
1286         .setup_asic = &rv770_dpm_setup_asic,
1287         .enable = &rv770_dpm_enable,
1288         .late_enable = &rv770_dpm_late_enable,
1289         .disable = &rv770_dpm_disable,
1290         .pre_set_power_state = &r600_dpm_pre_set_power_state,
1291         .set_power_state = &rv770_dpm_set_power_state,
1292         .post_set_power_state = &r600_dpm_post_set_power_state,
1293         .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1294         .fini = &rv770_dpm_fini,
1295         .get_sclk = &rv770_dpm_get_sclk,
1296         .get_mclk = &rv770_dpm_get_mclk,
1297         .print_power_state = &rv770_dpm_print_power_state,
1298         .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1299         .force_performance_level = &rv770_dpm_force_performance_level,
1300         .vblank_too_short = &rv770_dpm_vblank_too_short,
1301         .get_current_sclk = &rv770_dpm_get_current_sclk,
1302         .get_current_mclk = &rv770_dpm_get_current_mclk,
1303     },
1304     .pflip = {
1305         .page_flip = &rv770_page_flip,
1306         .page_flip_pending = &rv770_page_flip_pending,
1307     },
1308 };
1309
1310 static const struct radeon_asic_ring evergreen_gfx_ring = {
1311     .ib_execute = &evergreen_ring_ib_execute,
1312     .emit_fence = &r600_fence_ring_emit,
1313     .emit_semaphore = &r600_semaphore_ring_emit,
1314     .cs_parse = &evergreen_cs_parse,
1315     .ring_test = &r600_ring_test,
1316     .ib_test = &r600_ib_test,
1317     .is_lockup = &evergreen_gfx_is_lockup,
1318     .get_rptr = &r600_gfx_get_rptr,
1319     .get_wptr = &r600_gfx_get_wptr,
1320     .set_wptr = &r600_gfx_set_wptr,
1321 };
1322
1323 static const struct radeon_asic_ring evergreen_dma_ring = {
1324     .ib_execute = &evergreen_dma_ring_ib_execute,
1325     .emit_fence = &evergreen_dma_fence_ring_emit,
1326     .emit_semaphore = &r600_dma_semaphore_ring_emit,
1327     .cs_parse = &evergreen_dma_cs_parse,
1328     .ring_test = &r600_dma_ring_test,
1329     .ib_test = &r600_dma_ib_test,
1330     .is_lockup = &evergreen_dma_is_lockup,
1331     .get_rptr = &r600_dma_get_rptr,
1332     .get_wptr = &r600_dma_get_wptr,
1333     .set_wptr = &r600_dma_set_wptr,
1334 };
1335
1336 static struct radeon_asic evergreen_asic = {
1337     .init = &evergreen_init,
1338     .fini = &evergreen_fini,
1339     .suspend = &evergreen_suspend,
1340     .resume = &evergreen_resume,
1341     .asic_reset = &evergreen_asic_reset,
1342     .vga_set_state = &r600_vga_set_state,
1343     .mmio_hdp_flush = r600_mmio_hdp_flush,
1344     .gui_idle = &r600_gui_idle,
1345     .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1346     .get_xclk = &rv770_get_xclk,
1347     .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1348     .get_allowed_info_register = evergreen_get_allowed_info_register,
1349     .gart = {
1350         .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1351         .get_page_entry = &rs600_gart_get_page_entry,
1352         .set_page = &rs600_gart_set_page,
1353     },
1354     .ring = {
1355         [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1356         [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1357         [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1358     },
1359     .irq = {
1360         .set = &evergreen_irq_set,
1361         .process = &evergreen_irq_process,
1362     },
1363     .display = {
1364         .bandwidth_update = &evergreen_bandwidth_update,
1365         .get_vblank_counter = &evergreen_get_vblank_counter,
1366         .wait_for_vblank = &dce4_wait_for_vblank,
1367         .set_backlight_level = &atombios_set_backlight_level,
1368         .get_backlight_level = &atombios_get_backlight_level,
1369     },
1370     .copy = {
1371         .blit = &r600_copy_cpdma,
1372         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1373         .dma = &evergreen_copy_dma,
1374         .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1375         .copy = &evergreen_copy_dma,
1376         .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1377     },
1378     .surface = {
1379         .set_reg = r600_set_surface_reg,
1380         .clear_reg = r600_clear_surface_reg,
1381     },
1382     .hpd = {
1383         .init = &evergreen_hpd_init,
1384         .fini = &evergreen_hpd_fini,
1385         .sense = &evergreen_hpd_sense,
1386         .set_polarity = &evergreen_hpd_set_polarity,
1387     },
1388     .pm = {
1389         .misc = &evergreen_pm_misc,
1390         .prepare = &evergreen_pm_prepare,
1391         .finish = &evergreen_pm_finish,
1392         .init_profile = &r600_pm_init_profile,
1393         .get_dynpm_state = &r600_pm_get_dynpm_state,
1394         .get_engine_clock = &radeon_atom_get_engine_clock,
1395         .set_engine_clock = &radeon_atom_set_engine_clock,
1396         .get_memory_clock = &radeon_atom_get_memory_clock,
1397         .set_memory_clock = &radeon_atom_set_memory_clock,
1398         .get_pcie_lanes = &r600_get_pcie_lanes,
1399         .set_pcie_lanes = &r600_set_pcie_lanes,
1400         .set_clock_gating = NULL,
1401         .set_uvd_clocks = &evergreen_set_uvd_clocks,
1402         .get_temperature = &evergreen_get_temp,
1403     },
1404     .dpm = {
1405         .init = &cypress_dpm_init,
1406         .setup_asic = &cypress_dpm_setup_asic,
1407         .enable = &cypress_dpm_enable,
1408         .late_enable = &rv770_dpm_late_enable,
1409         .disable = &cypress_dpm_disable,
1410         .pre_set_power_state = &r600_dpm_pre_set_power_state,
1411         .set_power_state = &cypress_dpm_set_power_state,
1412         .post_set_power_state = &r600_dpm_post_set_power_state,
1413         .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1414         .fini = &cypress_dpm_fini,
1415         .get_sclk = &rv770_dpm_get_sclk,
1416         .get_mclk = &rv770_dpm_get_mclk,
1417         .print_power_state = &rv770_dpm_print_power_state,
1418         .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1419         .force_performance_level = &rv770_dpm_force_performance_level,
1420         .vblank_too_short = &cypress_dpm_vblank_too_short,
1421         .get_current_sclk = &rv770_dpm_get_current_sclk,
1422         .get_current_mclk = &rv770_dpm_get_current_mclk,
1423     },
1424     .pflip = {
1425         .page_flip = &evergreen_page_flip,
1426         .page_flip_pending = &evergreen_page_flip_pending,
1427     },
1428 };
1429
1430 static struct radeon_asic sumo_asic = {
1431     .init = &evergreen_init,
1432     .fini = &evergreen_fini,
1433     .suspend = &evergreen_suspend,
1434     .resume = &evergreen_resume,
1435     .asic_reset = &evergreen_asic_reset,
1436     .vga_set_state = &r600_vga_set_state,
1437     .mmio_hdp_flush = r600_mmio_hdp_flush,
1438     .gui_idle = &r600_gui_idle,
1439     .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1440     .get_xclk = &r600_get_xclk,
1441     .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1442     .get_allowed_info_register = evergreen_get_allowed_info_register,
1443     .gart = {
1444         .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1445         .get_page_entry = &rs600_gart_get_page_entry,
1446         .set_page = &rs600_gart_set_page,
1447     },
1448     .ring = {
1449         [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1450         [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1451         [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1452     },
1453     .irq = {
1454         .set = &evergreen_irq_set,
1455         .process = &evergreen_irq_process,
1456     },
1457     .display = {
1458         .bandwidth_update = &evergreen_bandwidth_update,
1459         .get_vblank_counter = &evergreen_get_vblank_counter,
1460         .wait_for_vblank = &dce4_wait_for_vblank,
1461         .set_backlight_level = &atombios_set_backlight_level,
1462         .get_backlight_level = &atombios_get_backlight_level,
1463     },
1464     .copy = {
1465         .blit = &r600_copy_cpdma,
1466         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1467         .dma = &evergreen_copy_dma,
1468         .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1469         .copy = &evergreen_copy_dma,
1470         .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1471     },
1472     .surface = {
1473         .set_reg = r600_set_surface_reg,
1474         .clear_reg = r600_clear_surface_reg,
1475     },
1476     .hpd = {
1477         .init = &evergreen_hpd_init,
1478         .fini = &evergreen_hpd_fini,
1479         .sense = &evergreen_hpd_sense,
1480         .set_polarity = &evergreen_hpd_set_polarity,
1481     },
1482     .pm = {
1483         .misc = &evergreen_pm_misc,
1484         .prepare = &evergreen_pm_prepare,
1485         .finish = &evergreen_pm_finish,
1486         .init_profile = &sumo_pm_init_profile,
1487         .get_dynpm_state = &r600_pm_get_dynpm_state,
1488         .get_engine_clock = &radeon_atom_get_engine_clock,
1489         .set_engine_clock = &radeon_atom_set_engine_clock,
1490         .get_memory_clock = NULL,
1491         .set_memory_clock = NULL,
1492         .get_pcie_lanes = NULL,
1493         .set_pcie_lanes = NULL,
1494         .set_clock_gating = NULL,
1495         .set_uvd_clocks = &sumo_set_uvd_clocks,
1496         .get_temperature = &sumo_get_temp,
1497     },
1498     .dpm = {
1499         .init = &sumo_dpm_init,
1500         .setup_asic = &sumo_dpm_setup_asic,
1501         .enable = &sumo_dpm_enable,
1502         .late_enable = &sumo_dpm_late_enable,
1503         .disable = &sumo_dpm_disable,
1504         .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1505         .set_power_state = &sumo_dpm_set_power_state,
1506         .post_set_power_state = &sumo_dpm_post_set_power_state,
1507         .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1508         .fini = &sumo_dpm_fini,
1509         .get_sclk = &sumo_dpm_get_sclk,
1510         .get_mclk = &sumo_dpm_get_mclk,
1511         .print_power_state = &sumo_dpm_print_power_state,
1512         .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1513         .force_performance_level = &sumo_dpm_force_performance_level,
1514         .get_current_sclk = &sumo_dpm_get_current_sclk,
1515         .get_current_mclk = &sumo_dpm_get_current_mclk,
1516         .get_current_vddc = &sumo_dpm_get_current_vddc,
1517     },
1518     .pflip = {
1519         .page_flip = &evergreen_page_flip,
1520         .page_flip_pending = &evergreen_page_flip_pending,
1521     },
1522 };
1523
1524 static struct radeon_asic btc_asic = {
1525     .init = &evergreen_init,
1526     .fini = &evergreen_fini,
1527     .suspend = &evergreen_suspend,
1528     .resume = &evergreen_resume,
1529     .asic_reset = &evergreen_asic_reset,
1530     .vga_set_state = &r600_vga_set_state,
1531     .mmio_hdp_flush = r600_mmio_hdp_flush,
1532     .gui_idle = &r600_gui_idle,
1533     .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1534     .get_xclk = &rv770_get_xclk,
1535     .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1536     .get_allowed_info_register = evergreen_get_allowed_info_register,
1537     .gart = {
1538         .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1539         .get_page_entry = &rs600_gart_get_page_entry,
1540         .set_page = &rs600_gart_set_page,
1541     },
1542     .ring = {
1543         [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1544         [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1545         [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1546     },
1547     .irq = {
1548         .set = &evergreen_irq_set,
1549         .process = &evergreen_irq_process,
1550     },
1551     .display = {
1552         .bandwidth_update = &evergreen_bandwidth_update,
1553         .get_vblank_counter = &evergreen_get_vblank_counter,
1554         .wait_for_vblank = &dce4_wait_for_vblank,
1555         .set_backlight_level = &atombios_set_backlight_level,
1556         .get_backlight_level = &atombios_get_backlight_level,
1557     },
1558     .copy = {
1559         .blit = &r600_copy_cpdma,
1560         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1561         .dma = &evergreen_copy_dma,
1562         .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1563         .copy = &evergreen_copy_dma,
1564         .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1565     },
1566     .surface = {
1567         .set_reg = r600_set_surface_reg,
1568         .clear_reg = r600_clear_surface_reg,
1569     },
1570     .hpd = {
1571         .init = &evergreen_hpd_init,
1572         .fini = &evergreen_hpd_fini,
1573         .sense = &evergreen_hpd_sense,
1574         .set_polarity = &evergreen_hpd_set_polarity,
1575     },
1576     .pm = {
1577         .misc = &evergreen_pm_misc,
1578         .prepare = &evergreen_pm_prepare,
1579         .finish = &evergreen_pm_finish,
1580         .init_profile = &btc_pm_init_profile,
1581         .get_dynpm_state = &r600_pm_get_dynpm_state,
1582         .get_engine_clock = &radeon_atom_get_engine_clock,
1583         .set_engine_clock = &radeon_atom_set_engine_clock,
1584         .get_memory_clock = &radeon_atom_get_memory_clock,
1585         .set_memory_clock = &radeon_atom_set_memory_clock,
1586         .get_pcie_lanes = &r600_get_pcie_lanes,
1587         .set_pcie_lanes = &r600_set_pcie_lanes,
1588         .set_clock_gating = NULL,
1589         .set_uvd_clocks = &evergreen_set_uvd_clocks,
1590         .get_temperature = &evergreen_get_temp,
1591     },
1592     .dpm = {
1593         .init = &btc_dpm_init,
1594         .setup_asic = &btc_dpm_setup_asic,
1595         .enable = &btc_dpm_enable,
1596         .late_enable = &rv770_dpm_late_enable,
1597         .disable = &btc_dpm_disable,
1598         .pre_set_power_state = &btc_dpm_pre_set_power_state,
1599         .set_power_state = &btc_dpm_set_power_state,
1600         .post_set_power_state = &btc_dpm_post_set_power_state,
1601         .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1602         .fini = &btc_dpm_fini,
1603         .get_sclk = &btc_dpm_get_sclk,
1604         .get_mclk = &btc_dpm_get_mclk,
1605         .print_power_state = &rv770_dpm_print_power_state,
1606         .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
1607         .force_performance_level = &rv770_dpm_force_performance_level,
1608         .vblank_too_short = &btc_dpm_vblank_too_short,
1609         .get_current_sclk = &btc_dpm_get_current_sclk,
1610         .get_current_mclk = &btc_dpm_get_current_mclk,
1611     },
1612     .pflip = {
1613         .page_flip = &evergreen_page_flip,
1614         .page_flip_pending = &evergreen_page_flip_pending,
1615     },
1616 };
1617
1618 static const struct radeon_asic_ring cayman_gfx_ring = {
1619     .ib_execute = &cayman_ring_ib_execute,
1620     .ib_parse = &evergreen_ib_parse,
1621     .emit_fence = &cayman_fence_ring_emit,
1622     .emit_semaphore = &r600_semaphore_ring_emit,
1623     .cs_parse = &evergreen_cs_parse,
1624     .ring_test = &r600_ring_test,
1625     .ib_test = &r600_ib_test,
1626     .is_lockup = &cayman_gfx_is_lockup,
1627     .vm_flush = &cayman_vm_flush,
1628     .get_rptr = &cayman_gfx_get_rptr,
1629     .get_wptr = &cayman_gfx_get_wptr,
1630     .set_wptr = &cayman_gfx_set_wptr,
1631 };
1632
1633 static const struct radeon_asic_ring cayman_dma_ring = {
1634     .ib_execute = &cayman_dma_ring_ib_execute,
1635     .ib_parse = &evergreen_dma_ib_parse,
1636     .emit_fence = &evergreen_dma_fence_ring_emit,
1637     .emit_semaphore = &r600_dma_semaphore_ring_emit,
1638     .cs_parse = &evergreen_dma_cs_parse,
1639     .ring_test = &r600_dma_ring_test,
1640     .ib_test = &r600_dma_ib_test,
1641     .is_lockup = &cayman_dma_is_lockup,
1642     .vm_flush = &cayman_dma_vm_flush,
1643     .get_rptr = &cayman_dma_get_rptr,
1644     .get_wptr = &cayman_dma_get_wptr,
1645     .set_wptr = &cayman_dma_set_wptr
1646 };
1647
1648 static const struct radeon_asic_ring cayman_uvd_ring = {
1649     .ib_execute = &uvd_v1_0_ib_execute,
1650     .emit_fence = &uvd_v2_2_fence_emit,
1651     .emit_semaphore = &uvd_v3_1_semaphore_emit,
1652     .cs_parse = &radeon_uvd_cs_parse,
1653     .ring_test = &uvd_v1_0_ring_test,
1654     .ib_test = &uvd_v1_0_ib_test,
1655     .is_lockup = &radeon_ring_test_lockup,
1656     .get_rptr = &uvd_v1_0_get_rptr,
1657     .get_wptr = &uvd_v1_0_get_wptr,
1658     .set_wptr = &uvd_v1_0_set_wptr,
1659 };
1660
1661 static struct radeon_asic cayman_asic = {
1662     .init = &cayman_init,
1663     .fini = &cayman_fini,
1664     .suspend = &cayman_suspend,
1665     .resume = &cayman_resume,
1666     .asic_reset = &cayman_asic_reset,
1667     .vga_set_state = &r600_vga_set_state,
1668     .mmio_hdp_flush = r600_mmio_hdp_flush,
1669     .gui_idle = &r600_gui_idle,
1670     .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1671     .get_xclk = &rv770_get_xclk,
1672     .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1673     .get_allowed_info_register = cayman_get_allowed_info_register,
1674     .gart = {
1675         .tlb_flush = &cayman_pcie_gart_tlb_flush,
1676         .get_page_entry = &rs600_gart_get_page_entry,
1677         .set_page = &rs600_gart_set_page,
1678     },
1679     .vm = {
1680         .init = &cayman_vm_init,
1681         .fini = &cayman_vm_fini,
1682         .copy_pages = &cayman_dma_vm_copy_pages,
1683         .write_pages = &cayman_dma_vm_write_pages,
1684         .set_pages = &cayman_dma_vm_set_pages,
1685         .pad_ib = &cayman_dma_vm_pad_ib,
1686     },
1687     .ring = {
1688         [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1689         [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1690         [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1691         [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1692         [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1693         [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1694     },
1695     .irq = {
1696         .set = &evergreen_irq_set,
1697         .process = &evergreen_irq_process,
1698     },
1699     .display = {
1700         .bandwidth_update = &evergreen_bandwidth_update,
1701         .get_vblank_counter = &evergreen_get_vblank_counter,
1702         .wait_for_vblank = &dce4_wait_for_vblank,
1703         .set_backlight_level = &atombios_set_backlight_level,
1704         .get_backlight_level = &atombios_get_backlight_level,
1705     },
1706     .copy = {
1707         .blit = &r600_copy_cpdma,
1708         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1709         .dma = &evergreen_copy_dma,
1710         .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1711         .copy = &evergreen_copy_dma,
1712         .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1713     },
1714     .surface = {
1715         .set_reg = r600_set_surface_reg,
1716         .clear_reg = r600_clear_surface_reg,
1717     },
1718     .hpd = {
1719         .init = &evergreen_hpd_init,
1720         .fini = &evergreen_hpd_fini,
1721         .sense = &evergreen_hpd_sense,
1722         .set_polarity = &evergreen_hpd_set_polarity,
1723     },
1724     .pm = {
1725         .misc = &evergreen_pm_misc,
1726         .prepare = &evergreen_pm_prepare,
1727         .finish = &evergreen_pm_finish,
1728         .init_profile = &btc_pm_init_profile,
1729         .get_dynpm_state = &r600_pm_get_dynpm_state,
1730         .get_engine_clock = &radeon_atom_get_engine_clock,
1731         .set_engine_clock = &radeon_atom_set_engine_clock,
1732         .get_memory_clock = &radeon_atom_get_memory_clock,
1733         .set_memory_clock = &radeon_atom_set_memory_clock,
1734         .get_pcie_lanes = &r600_get_pcie_lanes,
1735         .set_pcie_lanes = &r600_set_pcie_lanes,
1736         .set_clock_gating = NULL,
1737         .set_uvd_clocks = &evergreen_set_uvd_clocks,
1738         .get_temperature = &evergreen_get_temp,
1739     },
1740     .dpm = {
1741         .init = &ni_dpm_init,
1742         .setup_asic = &ni_dpm_setup_asic,
1743         .enable = &ni_dpm_enable,
1744         .late_enable = &rv770_dpm_late_enable,
1745         .disable = &ni_dpm_disable,
1746         .pre_set_power_state = &ni_dpm_pre_set_power_state,
1747         .set_power_state = &ni_dpm_set_power_state,
1748         .post_set_power_state = &ni_dpm_post_set_power_state,
1749         .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1750         .fini = &ni_dpm_fini,
1751         .get_sclk = &ni_dpm_get_sclk,
1752         .get_mclk = &ni_dpm_get_mclk,
1753         .print_power_state = &ni_dpm_print_power_state,
1754         .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1755         .force_performance_level = &ni_dpm_force_performance_level,
1756         .vblank_too_short = &ni_dpm_vblank_too_short,
1757         .get_current_sclk = &ni_dpm_get_current_sclk,
1758         .get_current_mclk = &ni_dpm_get_current_mclk,
1759     },
1760     .pflip = {
1761         .page_flip = &evergreen_page_flip,
1762         .page_flip_pending = &evergreen_page_flip_pending,
1763     },
1764 };
1765
1766 static const struct radeon_asic_ring trinity_vce_ring = {
1767     .ib_execute = &radeon_vce_ib_execute,
1768     .emit_fence = &radeon_vce_fence_emit,
1769     .emit_semaphore = &radeon_vce_semaphore_emit,
1770     .cs_parse = &radeon_vce_cs_parse,
1771     .ring_test = &radeon_vce_ring_test,
1772     .ib_test = &radeon_vce_ib_test,
1773     .is_lockup = &radeon_ring_test_lockup,
1774     .get_rptr = &vce_v1_0_get_rptr,
1775     .get_wptr = &vce_v1_0_get_wptr,
1776     .set_wptr = &vce_v1_0_set_wptr,
1777 };
1778
1779 static struct radeon_asic trinity_asic = {
1780     .init = &cayman_init,
1781     .fini = &cayman_fini,
1782     .suspend = &cayman_suspend,
1783     .resume = &cayman_resume,
1784     .asic_reset = &cayman_asic_reset,
1785     .vga_set_state = &r600_vga_set_state,
1786     .mmio_hdp_flush = r600_mmio_hdp_flush,
1787     .gui_idle = &r600_gui_idle,
1788     .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1789     .get_xclk = &r600_get_xclk,
1790     .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1791     .get_allowed_info_register = cayman_get_allowed_info_register,
1792     .gart = {
1793         .tlb_flush = &cayman_pcie_gart_tlb_flush,
1794         .get_page_entry = &rs600_gart_get_page_entry,
1795         .set_page = &rs600_gart_set_page,
1796     },
1797     .vm = {
1798         .init = &cayman_vm_init,
1799         .fini = &cayman_vm_fini,
1800         .copy_pages = &cayman_dma_vm_copy_pages,
1801         .write_pages = &cayman_dma_vm_write_pages,
1802         .set_pages = &cayman_dma_vm_set_pages,
1803         .pad_ib = &cayman_dma_vm_pad_ib,
1804     },
1805     .ring = {
1806         [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1807         [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1808         [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1809         [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1810         [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1811         [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1812         [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
1813         [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
1814     },
1815     .irq = {
1816         .set = &evergreen_irq_set,
1817         .process = &evergreen_irq_process,
1818     },
1819     .display = {
1820         .bandwidth_update = &dce6_bandwidth_update,
1821         .get_vblank_counter = &evergreen_get_vblank_counter,
1822         .wait_for_vblank = &dce4_wait_for_vblank,
1823         .set_backlight_level = &atombios_set_backlight_level,
1824         .get_backlight_level = &atombios_get_backlight_level,
1825     },
1826     .copy = {
1827         .blit = &r600_copy_cpdma,
1828         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1829         .dma = &evergreen_copy_dma,
1830         .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1831         .copy = &evergreen_copy_dma,
1832         .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1833     },
1834     .surface = {
1835         .set_reg = r600_set_surface_reg,
1836         .clear_reg = r600_clear_surface_reg,
1837     },
1838     .hpd = {
1839         .init = &evergreen_hpd_init,
1840         .fini = &evergreen_hpd_fini,
1841         .sense = &evergreen_hpd_sense,
1842         .set_polarity = &evergreen_hpd_set_polarity,
1843     },
1844     .pm = {
1845         .misc = &evergreen_pm_misc,
1846         .prepare = &evergreen_pm_prepare,
1847         .finish = &evergreen_pm_finish,
1848         .init_profile = &sumo_pm_init_profile,
1849         .get_dynpm_state = &r600_pm_get_dynpm_state,
1850         .get_engine_clock = &radeon_atom_get_engine_clock,
1851         .set_engine_clock = &radeon_atom_set_engine_clock,
1852         .get_memory_clock = NULL,
1853         .set_memory_clock = NULL,
1854         .get_pcie_lanes = NULL,
1855         .set_pcie_lanes = NULL,
1856         .set_clock_gating = NULL,
1857         .set_uvd_clocks = &sumo_set_uvd_clocks,
1858         .set_vce_clocks = &tn_set_vce_clocks,
1859         .get_temperature = &tn_get_temp,
1860     },
1861     .dpm = {
1862         .init = &trinity_dpm_init,
1863         .setup_asic = &trinity_dpm_setup_asic,
1864         .enable = &trinity_dpm_enable,
1865         .late_enable = &trinity_dpm_late_enable,
1866         .disable = &trinity_dpm_disable,
1867         .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1868         .set_power_state = &trinity_dpm_set_power_state,
1869         .post_set_power_state = &trinity_dpm_post_set_power_state,
1870         .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1871         .fini = &trinity_dpm_fini,
1872         .get_sclk = &trinity_dpm_get_sclk,
1873         .get_mclk = &trinity_dpm_get_mclk,
1874         .print_power_state = &trinity_dpm_print_power_state,
1875         .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1876         .force_performance_level = &trinity_dpm_force_performance_level,
1877         .enable_bapm = &trinity_dpm_enable_bapm,
1878         .get_current_sclk = &trinity_dpm_get_current_sclk,
1879         .get_current_mclk = &trinity_dpm_get_current_mclk,
1880     },
1881     .pflip = {
1882         .page_flip = &evergreen_page_flip,
1883         .page_flip_pending = &evergreen_page_flip_pending,
1884     },
1885 };
1886
1887 static const struct radeon_asic_ring si_gfx_ring = {
1888     .ib_execute = &si_ring_ib_execute,
1889     .ib_parse = &si_ib_parse,
1890     .emit_fence = &si_fence_ring_emit,
1891     .emit_semaphore = &r600_semaphore_ring_emit,
1892     .cs_parse = NULL,
1893     .ring_test = &r600_ring_test,
1894     .ib_test = &r600_ib_test,
1895     .is_lockup = &si_gfx_is_lockup,
1896     .vm_flush = &si_vm_flush,
1897     .get_rptr = &cayman_gfx_get_rptr,
1898     .get_wptr = &cayman_gfx_get_wptr,
1899     .set_wptr = &cayman_gfx_set_wptr,
1900 };
1901
1902 static const struct radeon_asic_ring si_dma_ring = {
1903     .ib_execute = &cayman_dma_ring_ib_execute,
1904     .ib_parse = &evergreen_dma_ib_parse,
1905     .emit_fence = &evergreen_dma_fence_ring_emit,
1906     .emit_semaphore = &r600_dma_semaphore_ring_emit,
1907     .cs_parse = NULL,
1908     .ring_test = &r600_dma_ring_test,
1909     .ib_test = &r600_dma_ib_test,
1910     .is_lockup = &si_dma_is_lockup,
1911     .vm_flush = &si_dma_vm_flush,
1912     .get_rptr = &cayman_dma_get_rptr,
1913     .get_wptr = &cayman_dma_get_wptr,
1914     .set_wptr = &cayman_dma_set_wptr,
1915 };
1916
1917 static struct radeon_asic si_asic = {
1918     .init = &si_init,
1919     .fini = &si_fini,
1920     .suspend = &si_suspend,
1921     .resume = &si_resume,
1922     .asic_reset = &si_asic_reset,
1923     .vga_set_state = &r600_vga_set_state,
1924     .mmio_hdp_flush = r600_mmio_hdp_flush,
1925     .gui_idle = &r600_gui_idle,
1926     .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1927     .get_xclk = &si_get_xclk,
1928     .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1929     .get_allowed_info_register = si_get_allowed_info_register,
1930     .gart = {
1931         .tlb_flush = &si_pcie_gart_tlb_flush,
1932         .get_page_entry = &rs600_gart_get_page_entry,
1933         .set_page = &rs600_gart_set_page,
1934     },
1935     .vm = {
1936         .init = &si_vm_init,
1937         .fini = &si_vm_fini,
1938         .copy_pages = &si_dma_vm_copy_pages,
1939         .write_pages = &si_dma_vm_write_pages,
1940         .set_pages = &si_dma_vm_set_pages,
1941         .pad_ib = &cayman_dma_vm_pad_ib,
1942     },
1943     .ring = {
1944         [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1945         [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1946         [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1947         [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1948         [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1949         [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1950         [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
1951         [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
1952     },
1953     .irq = {
1954         .set = &si_irq_set,
1955         .process = &si_irq_process,
1956     },
1957     .display = {
1958         .bandwidth_update = &dce6_bandwidth_update,
1959         .get_vblank_counter = &evergreen_get_vblank_counter,
1960         .wait_for_vblank = &dce4_wait_for_vblank,
1961         .set_backlight_level = &atombios_set_backlight_level,
1962         .get_backlight_level = &atombios_get_backlight_level,
1963     },
1964     .copy = {
1965         .blit = &r600_copy_cpdma,
1966         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1967         .dma = &si_copy_dma,
1968         .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1969         .copy = &si_copy_dma,
1970         .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1971     },
1972     .surface = {
1973         .set_reg = r600_set_surface_reg,
1974         .clear_reg = r600_clear_surface_reg,
1975     },
1976     .hpd = {
1977         .init = &evergreen_hpd_init,
1978         .fini = &evergreen_hpd_fini,
1979         .sense = &evergreen_hpd_sense,
1980         .set_polarity = &evergreen_hpd_set_polarity,
1981     },
1982     .pm = {
1983         .misc = &evergreen_pm_misc,
1984         .prepare = &evergreen_pm_prepare,
1985         .finish = &evergreen_pm_finish,
1986         .init_profile = &sumo_pm_init_profile,
1987         .get_dynpm_state = &r600_pm_get_dynpm_state,
1988         .get_engine_clock = &radeon_atom_get_engine_clock,
1989         .set_engine_clock = &radeon_atom_set_engine_clock,
1990         .get_memory_clock = &radeon_atom_get_memory_clock,
1991         .set_memory_clock = &radeon_atom_set_memory_clock,
1992         .get_pcie_lanes = &r600_get_pcie_lanes,
1993         .set_pcie_lanes = &r600_set_pcie_lanes,
1994         .set_clock_gating = NULL,
1995         .set_uvd_clocks = &si_set_uvd_clocks,
1996         .set_vce_clocks = &si_set_vce_clocks,
1997         .get_temperature = &si_get_temp,
1998     },
1999     .dpm = {
2000         .init = &si_dpm_init,
2001         .setup_asic = &si_dpm_setup_asic,
2002         .enable = &si_dpm_enable,
2003         .late_enable = &si_dpm_late_enable,
2004         .disable = &si_dpm_disable,
2005         .pre_set_power_state = &si_dpm_pre_set_power_state,
2006         .set_power_state = &si_dpm_set_power_state,
2007         .post_set_power_state = &si_dpm_post_set_power_state,
2008         .display_configuration_changed = &si_dpm_display_configuration_changed,
2009         .fini = &si_dpm_fini,
2010         .get_sclk = &ni_dpm_get_sclk,
2011         .get_mclk = &ni_dpm_get_mclk,
2012         .print_power_state = &ni_dpm_print_power_state,
2013         .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
2014         .force_performance_level = &si_dpm_force_performance_level,
2015         .vblank_too_short = &ni_dpm_vblank_too_short,
2016         .fan_ctrl_set_mode = &si_fan_ctrl_set_mode,
2017         .fan_ctrl_get_mode = &si_fan_ctrl_get_mode,
2018         .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent,
2019         .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent,
2020         .get_current_sclk = &si_dpm_get_current_sclk,
2021         .get_current_mclk = &si_dpm_get_current_mclk,
2022     },
2023     .pflip = {
2024         .page_flip = &evergreen_page_flip,
2025         .page_flip_pending = &evergreen_page_flip_pending,
2026     },
2027 };
2028
2029 static const struct radeon_asic_ring ci_gfx_ring = {
2030     .ib_execute = &cik_ring_ib_execute,
2031     .ib_parse = &cik_ib_parse,
2032     .emit_fence = &cik_fence_gfx_ring_emit,
2033     .emit_semaphore = &cik_semaphore_ring_emit,
2034     .cs_parse = NULL,
2035     .ring_test = &cik_ring_test,
2036     .ib_test = &cik_ib_test,
2037     .is_lockup = &cik_gfx_is_lockup,
2038     .vm_flush = &cik_vm_flush,
2039     .get_rptr = &cik_gfx_get_rptr,
2040     .get_wptr = &cik_gfx_get_wptr,
2041     .set_wptr = &cik_gfx_set_wptr,
2042 };
2043
2044 static const struct radeon_asic_ring ci_cp_ring = {
2045     .ib_execute = &cik_ring_ib_execute,
2046     .ib_parse = &cik_ib_parse,
2047     .emit_fence = &cik_fence_compute_ring_emit,
2048     .emit_semaphore = &cik_semaphore_ring_emit,
2049     .cs_parse = NULL,
2050     .ring_test = &cik_ring_test,
2051     .ib_test = &cik_ib_test,
2052     .is_lockup = &cik_gfx_is_lockup,
2053     .vm_flush = &cik_vm_flush,
2054     .get_rptr = &cik_compute_get_rptr,
2055     .get_wptr = &cik_compute_get_wptr,
2056     .set_wptr = &cik_compute_set_wptr,
2057 };
2058
2059 static const struct radeon_asic_ring ci_dma_ring = {
2060     .ib_execute = &cik_sdma_ring_ib_execute,
2061     .ib_parse = &cik_ib_parse,
2062     .emit_fence = &cik_sdma_fence_ring_emit,
2063     .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2064     .cs_parse = NULL,
2065     .ring_test = &cik_sdma_ring_test,
2066     .ib_test = &cik_sdma_ib_test,
2067     .is_lockup = &cik_sdma_is_lockup,
2068     .vm_flush = &cik_dma_vm_flush,
2069     .get_rptr = &cik_sdma_get_rptr,
2070     .get_wptr = &cik_sdma_get_wptr,
2071     .set_wptr = &cik_sdma_set_wptr,
2072 };
2073
2074 static const struct radeon_asic_ring ci_vce_ring = {
2075     .ib_execute = &radeon_vce_ib_execute,
2076     .emit_fence = &radeon_vce_fence_emit,
2077     .emit_semaphore = &radeon_vce_semaphore_emit,
2078     .cs_parse = &radeon_vce_cs_parse,
2079     .ring_test = &radeon_vce_ring_test,
2080     .ib_test = &radeon_vce_ib_test,
2081     .is_lockup = &radeon_ring_test_lockup,
2082     .get_rptr = &vce_v1_0_get_rptr,
2083     .get_wptr = &vce_v1_0_get_wptr,
2084     .set_wptr = &vce_v1_0_set_wptr,
2085 };
2086
2087 static struct radeon_asic ci_asic = {
2088     .init = &cik_init,
2089     .fini = &cik_fini,
2090     .suspend = &cik_suspend,
2091     .resume = &cik_resume,
2092     .asic_reset = &cik_asic_reset,
2093     .vga_set_state = &r600_vga_set_state,
2094     .mmio_hdp_flush = &r600_mmio_hdp_flush,
2095     .gui_idle = &r600_gui_idle,
2096     .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2097     .get_xclk = &cik_get_xclk,
2098     .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2099     .get_allowed_info_register = cik_get_allowed_info_register,
2100     .gart = {
2101         .tlb_flush = &cik_pcie_gart_tlb_flush,
2102         .get_page_entry = &rs600_gart_get_page_entry,
2103         .set_page = &rs600_gart_set_page,
2104     },
2105     .vm = {
2106         .init = &cik_vm_init,
2107         .fini = &cik_vm_fini,
2108         .copy_pages = &cik_sdma_vm_copy_pages,
2109         .write_pages = &cik_sdma_vm_write_pages,
2110         .set_pages = &cik_sdma_vm_set_pages,
2111         .pad_ib = &cik_sdma_vm_pad_ib,
2112     },
2113     .ring = {
2114         [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2115         [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2116         [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2117         [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2118         [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2119         [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2120         [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2121         [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2122     },
2123     .irq = {
2124         .set = &cik_irq_set,
2125         .process = &cik_irq_process,
2126     },
2127     .display = {
2128         .bandwidth_update = &dce8_bandwidth_update,
2129         .get_vblank_counter = &evergreen_get_vblank_counter,
2130         .wait_for_vblank = &dce4_wait_for_vblank,
2131         .set_backlight_level = &atombios_set_backlight_level,
2132         .get_backlight_level = &atombios_get_backlight_level,
2133     },
2134     .copy = {
2135         .blit = &cik_copy_cpdma,
2136         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2137         .dma = &cik_copy_dma,
2138         .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2139         .copy = &cik_copy_dma,
2140         .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2141     },
2142     .surface = {
2143         .set_reg = r600_set_surface_reg,
2144         .clear_reg = r600_clear_surface_reg,
2145     },
2146     .hpd = {
2147         .init = &evergreen_hpd_init,
2148         .fini = &evergreen_hpd_fini,
2149         .sense = &evergreen_hpd_sense,
2150         .set_polarity = &evergreen_hpd_set_polarity,
2151     },
2152     .pm = {
2153         .misc = &evergreen_pm_misc,
2154         .prepare = &evergreen_pm_prepare,
2155         .finish = &evergreen_pm_finish,
2156         .init_profile = &sumo_pm_init_profile,
2157         .get_dynpm_state = &r600_pm_get_dynpm_state,
2158         .get_engine_clock = &radeon_atom_get_engine_clock,
2159         .set_engine_clock = &radeon_atom_set_engine_clock,
2160         .get_memory_clock = &radeon_atom_get_memory_clock,
2161         .set_memory_clock = &radeon_atom_set_memory_clock,
2162         .get_pcie_lanes = NULL,
2163         .set_pcie_lanes = NULL,
2164         .set_clock_gating = NULL,
2165         .set_uvd_clocks = &cik_set_uvd_clocks,
2166         .set_vce_clocks = &cik_set_vce_clocks,
2167         .get_temperature = &ci_get_temp,
2168     },
2169     .dpm = {
2170         .init = &ci_dpm_init,
2171         .setup_asic = &ci_dpm_setup_asic,
2172         .enable = &ci_dpm_enable,
2173         .late_enable = &ci_dpm_late_enable,
2174         .disable = &ci_dpm_disable,
2175         .pre_set_power_state = &ci_dpm_pre_set_power_state,
2176         .set_power_state = &ci_dpm_set_power_state,
2177         .post_set_power_state = &ci_dpm_post_set_power_state,
2178         .display_configuration_changed = &ci_dpm_display_configuration_changed,
2179         .fini = &ci_dpm_fini,
2180         .get_sclk = &ci_dpm_get_sclk,
2181         .get_mclk = &ci_dpm_get_mclk,
2182         .print_power_state = &ci_dpm_print_power_state,
2183         .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2184         .force_performance_level = &ci_dpm_force_performance_level,
2185         .vblank_too_short = &ci_dpm_vblank_too_short,
2186         .powergate_uvd = &ci_dpm_powergate_uvd,
2187         .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode,
2188         .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode,
2189         .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent,
2190         .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent,
2191         .get_current_sclk = &ci_dpm_get_current_sclk,
2192         .get_current_mclk = &ci_dpm_get_current_mclk,
2193     },
2194     .pflip = {
2195         .page_flip = &evergreen_page_flip,
2196         .page_flip_pending = &evergreen_page_flip_pending,
2197     },
2198 };
2199
2200 static struct radeon_asic kv_asic = {
2201     .init = &cik_init,
2202     .fini = &cik_fini,
2203     .suspend = &cik_suspend,
2204     .resume = &cik_resume,
2205     .asic_reset = &cik_asic_reset,
2206     .vga_set_state = &r600_vga_set_state,
2207     .mmio_hdp_flush = &r600_mmio_hdp_flush,
2208     .gui_idle = &r600_gui_idle,
2209     .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2210     .get_xclk = &cik_get_xclk,
2211     .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2212     .get_allowed_info_register = cik_get_allowed_info_register,
2213     .gart = {
2214         .tlb_flush = &cik_pcie_gart_tlb_flush,
2215         .get_page_entry = &rs600_gart_get_page_entry,
2216         .set_page = &rs600_gart_set_page,
2217     },
2218     .vm = {
2219         .init = &cik_vm_init,
2220         .fini = &cik_vm_fini,
2221         .copy_pages = &cik_sdma_vm_copy_pages,
2222         .write_pages = &cik_sdma_vm_write_pages,
2223         .set_pages = &cik_sdma_vm_set_pages,
2224         .pad_ib = &cik_sdma_vm_pad_ib,
2225     },
2226     .ring = {
2227         [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2228         [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2229         [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2230         [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2231         [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2232         [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2233         [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2234         [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2235     },
2236     .irq = {
2237         .set = &cik_irq_set,
2238         .process = &cik_irq_process,
2239     },
2240     .display = {
2241         .bandwidth_update = &dce8_bandwidth_update,
2242         .get_vblank_counter = &evergreen_get_vblank_counter,
2243         .wait_for_vblank = &dce4_wait_for_vblank,
2244         .set_backlight_level = &atombios_set_backlight_level,
2245         .get_backlight_level = &atombios_get_backlight_level,
2246     },
2247     .copy = {
2248         .blit = &cik_copy_cpdma,
2249         .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2250         .dma = &cik_copy_dma,
2251         .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2252         .copy = &cik_copy_dma,
2253         .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2254     },
2255     .surface = {
2256         .set_reg = r600_set_surface_reg,
2257         .clear_reg = r600_clear_surface_reg,
2258     },
2259     .hpd = {
2260         .init = &evergreen_hpd_init,
2261         .fini = &evergreen_hpd_fini,
2262         .sense = &evergreen_hpd_sense,
2263         .set_polarity = &evergreen_hpd_set_polarity,
2264     },
2265     .pm = {
2266         .misc = &evergreen_pm_misc,
2267         .prepare = &evergreen_pm_prepare,
2268         .finish = &evergreen_pm_finish,
2269         .init_profile = &sumo_pm_init_profile,
2270         .get_dynpm_state = &r600_pm_get_dynpm_state,
2271         .get_engine_clock = &radeon_atom_get_engine_clock,
2272         .set_engine_clock = &radeon_atom_set_engine_clock,
2273         .get_memory_clock = &radeon_atom_get_memory_clock,
2274         .set_memory_clock = &radeon_atom_set_memory_clock,
2275         .get_pcie_lanes = NULL,
2276         .set_pcie_lanes = NULL,
2277         .set_clock_gating = NULL,
2278         .set_uvd_clocks = &cik_set_uvd_clocks,
2279         .set_vce_clocks = &cik_set_vce_clocks,
2280         .get_temperature = &kv_get_temp,
2281     },
2282     .dpm = {
2283         .init = &kv_dpm_init,
2284         .setup_asic = &kv_dpm_setup_asic,
2285         .enable = &kv_dpm_enable,
2286         .late_enable = &kv_dpm_late_enable,
2287         .disable = &kv_dpm_disable,
2288         .pre_set_power_state = &kv_dpm_pre_set_power_state,
2289         .set_power_state = &kv_dpm_set_power_state,
2290         .post_set_power_state = &kv_dpm_post_set_power_state,
2291         .display_configuration_changed = &kv_dpm_display_configuration_changed,
2292         .fini = &kv_dpm_fini,
2293         .get_sclk = &kv_dpm_get_sclk,
2294         .get_mclk = &kv_dpm_get_mclk,
2295         .print_power_state = &kv_dpm_print_power_state,
2296         .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2297         .force_performance_level = &kv_dpm_force_performance_level,
2298         .powergate_uvd = &kv_dpm_powergate_uvd,
2299         .enable_bapm = &kv_dpm_enable_bapm,
2300         .get_current_sclk = &kv_dpm_get_current_sclk,
2301         .get_current_mclk = &kv_dpm_get_current_mclk,
2302     },
2303     .pflip = {
2304         .page_flip = &evergreen_page_flip,
2305         .page_flip_pending = &evergreen_page_flip_pending,
2306     },
2307 };
2308
2309 /**
2310  * radeon_asic_init - register asic specific callbacks
2311  *
2312  * @rdev: radeon device pointer
2313  *
2314  * Registers the appropriate asic specific callbacks for each
2315  * chip family.  Also sets other asics specific info like the number
2316  * of crtcs and the register aperture accessors (all asics).
2317  * Returns 0 for success.
2318  */
2319 int radeon_asic_init(struct radeon_device *rdev)
2320 {
2321     radeon_register_accessor_init(rdev);
2322
2323     /* set the number of crtcs */
2324     if (rdev->flags & RADEON_SINGLE_CRTC)
2325         rdev->num_crtc = 1;
2326     else
2327         rdev->num_crtc = 2;
2328
2329     rdev->has_uvd = false;
2330     rdev->has_vce = false;
2331
2332     switch (rdev->family) {
2333     case CHIP_R100:
2334     case CHIP_RV100:
2335     case CHIP_RS100:
2336     case CHIP_RV200:
2337     case CHIP_RS200:
2338         rdev->asic = &r100_asic;
2339         break;
2340     case CHIP_R200:
2341     case CHIP_RV250:
2342     case CHIP_RS300:
2343     case CHIP_RV280:
2344         rdev->asic = &r200_asic;
2345         break;
2346     case CHIP_R300:
2347     case CHIP_R350:
2348     case CHIP_RV350:
2349     case CHIP_RV380:
2350         if (rdev->flags & RADEON_IS_PCIE)
2351             rdev->asic = &r300_asic_pcie;
2352         else
2353             rdev->asic = &r300_asic;
2354         break;
2355     case CHIP_R420:
2356     case CHIP_R423:
2357     case CHIP_RV410:
2358         rdev->asic = &r420_asic;
2359         /* handle macs */
2360         if (rdev->bios == NULL) {
2361             rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2362             rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2363             rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2364             rdev->asic->pm.set_memory_clock = NULL;
2365             rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2366         }
2367         break;
2368     case CHIP_RS400:
2369     case CHIP_RS480:
2370         rdev->asic = &rs400_asic;
2371         break;
2372     case CHIP_RS600:
2373         rdev->asic = &rs600_asic;
2374         break;
2375     case CHIP_RS690:
2376     case CHIP_RS740:
2377         rdev->asic = &rs690_asic;
2378         break;
2379     case CHIP_RV515:
2380         rdev->asic = &rv515_asic;
2381         break;
2382     case CHIP_R520:
2383     case CHIP_RV530:
2384     case CHIP_RV560:
2385     case CHIP_RV570:
2386     case CHIP_R580:
2387         rdev->asic = &r520_asic;
2388         break;
2389     case CHIP_R600:
2390         rdev->asic = &r600_asic;
2391         break;
2392     case CHIP_RV610:
2393     case CHIP_RV630:
2394     case CHIP_RV620:
2395     case CHIP_RV635:
2396     case CHIP_RV670:
2397         rdev->asic = &rv6xx_asic;
2398         rdev->has_uvd = true;
2399         break;
2400     case CHIP_RS780:
2401     case CHIP_RS880:
2402         rdev->asic = &rs780_asic;
2403         /* 760G/780V/880V don't have UVD */
2404         if ((rdev->pdev->device == 0x9616)||
2405             (rdev->pdev->device == 0x9611)||
2406             (rdev->pdev->device == 0x9613)||
2407             (rdev->pdev->device == 0x9711)||
2408             (rdev->pdev->device == 0x9713))
2409             rdev->has_uvd = false;
2410         else
2411             rdev->has_uvd = true;
2412         break;
2413     case CHIP_RV770:
2414     case CHIP_RV730:
2415     case CHIP_RV710:
2416     case CHIP_RV740:
2417         rdev->asic = &rv770_asic;
2418         rdev->has_uvd = true;
2419         break;
2420     case CHIP_CEDAR:
2421     case CHIP_REDWOOD:
2422     case CHIP_JUNIPER:
2423     case CHIP_CYPRESS:
2424     case CHIP_HEMLOCK:
2425         /* set num crtcs */
2426         if (rdev->family == CHIP_CEDAR)
2427             rdev->num_crtc = 4;
2428         else
2429             rdev->num_crtc = 6;
2430         rdev->asic = &evergreen_asic;
2431         rdev->has_uvd = true;
2432         break;
2433     case CHIP_PALM:
2434     case CHIP_SUMO:
2435     case CHIP_SUMO2:
2436         rdev->asic = &sumo_asic;
2437         rdev->has_uvd = true;
2438         break;
2439     case CHIP_BARTS:
2440     case CHIP_TURKS:
2441     case CHIP_CAICOS:
2442         /* set num crtcs */
2443         if (rdev->family == CHIP_CAICOS)
2444             rdev->num_crtc = 4;
2445         else
2446             rdev->num_crtc = 6;
2447         rdev->asic = &btc_asic;
2448         rdev->has_uvd = true;
2449         break;
2450     case CHIP_CAYMAN:
2451         rdev->asic = &cayman_asic;
2452         /* set num crtcs */
2453         rdev->num_crtc = 6;
2454         rdev->has_uvd = true;
2455         break;
2456     case CHIP_ARUBA:
2457         rdev->asic = &trinity_asic;
2458         /* set num crtcs */
2459         rdev->num_crtc = 4;
2460         rdev->has_uvd = true;
2461         rdev->has_vce = true;
2462         rdev->cg_flags =
2463             RADEON_CG_SUPPORT_VCE_MGCG;
2464         break;
2465     case CHIP_TAHITI:
2466     case CHIP_PITCAIRN:
2467     case CHIP_VERDE:
2468     case CHIP_OLAND:
2469     case CHIP_HAINAN:
2470         rdev->asic = &si_asic;
2471         /* set num crtcs */
2472         if (rdev->family == CHIP_HAINAN)
2473             rdev->num_crtc = 0;
2474         else if (rdev->family == CHIP_OLAND)
2475             rdev->num_crtc = 2;
2476         else
2477             rdev->num_crtc = 6;
2478         if (rdev->family == CHIP_HAINAN) {
2479             rdev->has_uvd = false;
2480             rdev->has_vce = false;
2481         } else if (rdev->family == CHIP_OLAND) {
2482             rdev->has_uvd = true;
2483             rdev->has_vce = false;
2484         } else {
2485             rdev->has_uvd = true;
2486             rdev->has_vce = true;
2487         }
2488         switch (rdev->family) {
2489         case CHIP_TAHITI:
2490             rdev->cg_flags =
2491                 RADEON_CG_SUPPORT_GFX_MGCG |
2492                 RADEON_CG_SUPPORT_GFX_MGLS |
2493                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2494                 RADEON_CG_SUPPORT_GFX_CGLS |
2495                 RADEON_CG_SUPPORT_GFX_CGTS |
2496                 RADEON_CG_SUPPORT_GFX_CP_LS |
2497                 RADEON_CG_SUPPORT_MC_MGCG |
2498                 RADEON_CG_SUPPORT_SDMA_MGCG |
2499                 RADEON_CG_SUPPORT_BIF_LS |
2500                 RADEON_CG_SUPPORT_VCE_MGCG |
2501                 RADEON_CG_SUPPORT_UVD_MGCG |
2502                 RADEON_CG_SUPPORT_HDP_LS |
2503                 RADEON_CG_SUPPORT_HDP_MGCG;
2504             rdev->pg_flags = 0;
2505             break;
2506         case CHIP_PITCAIRN:
2507             rdev->cg_flags =
2508                 RADEON_CG_SUPPORT_GFX_MGCG |
2509                 RADEON_CG_SUPPORT_GFX_MGLS |
2510                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2511                 RADEON_CG_SUPPORT_GFX_CGLS |
2512                 RADEON_CG_SUPPORT_GFX_CGTS |
2513                 RADEON_CG_SUPPORT_GFX_CP_LS |
2514                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2515                 RADEON_CG_SUPPORT_MC_LS |
2516                 RADEON_CG_SUPPORT_MC_MGCG |
2517                 RADEON_CG_SUPPORT_SDMA_MGCG |
2518                 RADEON_CG_SUPPORT_BIF_LS |
2519                 RADEON_CG_SUPPORT_VCE_MGCG |
2520                 RADEON_CG_SUPPORT_UVD_MGCG |
2521                 RADEON_CG_SUPPORT_HDP_LS |
2522                 RADEON_CG_SUPPORT_HDP_MGCG;
2523             rdev->pg_flags = 0;
2524             break;
2525         case CHIP_VERDE:
2526             rdev->cg_flags =
2527                 RADEON_CG_SUPPORT_GFX_MGCG |
2528                 RADEON_CG_SUPPORT_GFX_MGLS |
2529                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2530                 RADEON_CG_SUPPORT_GFX_CGLS |
2531                 RADEON_CG_SUPPORT_GFX_CGTS |
2532                 RADEON_CG_SUPPORT_GFX_CP_LS |
2533                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2534                 RADEON_CG_SUPPORT_MC_LS |
2535                 RADEON_CG_SUPPORT_MC_MGCG |
2536                 RADEON_CG_SUPPORT_SDMA_MGCG |
2537                 RADEON_CG_SUPPORT_BIF_LS |
2538                 RADEON_CG_SUPPORT_VCE_MGCG |
2539                 RADEON_CG_SUPPORT_UVD_MGCG |
2540                 RADEON_CG_SUPPORT_HDP_LS |
2541                 RADEON_CG_SUPPORT_HDP_MGCG;
2542             rdev->pg_flags = 0 |
2543                 /*RADEON_PG_SUPPORT_GFX_PG | */
2544                 RADEON_PG_SUPPORT_SDMA;
2545             break;
2546         case CHIP_OLAND:
2547             rdev->cg_flags =
2548                 RADEON_CG_SUPPORT_GFX_MGCG |
2549                 RADEON_CG_SUPPORT_GFX_MGLS |
2550                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2551                 RADEON_CG_SUPPORT_GFX_CGLS |
2552                 RADEON_CG_SUPPORT_GFX_CGTS |
2553                 RADEON_CG_SUPPORT_GFX_CP_LS |
2554                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2555                 RADEON_CG_SUPPORT_MC_LS |
2556                 RADEON_CG_SUPPORT_MC_MGCG |
2557                 RADEON_CG_SUPPORT_SDMA_MGCG |
2558                 RADEON_CG_SUPPORT_BIF_LS |
2559                 RADEON_CG_SUPPORT_UVD_MGCG |
2560                 RADEON_CG_SUPPORT_HDP_LS |
2561                 RADEON_CG_SUPPORT_HDP_MGCG;
2562             rdev->pg_flags = 0;
2563             break;
2564         case CHIP_HAINAN:
2565             rdev->cg_flags =
2566                 RADEON_CG_SUPPORT_GFX_MGCG |
2567                 RADEON_CG_SUPPORT_GFX_MGLS |
2568                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2569                 RADEON_CG_SUPPORT_GFX_CGLS |
2570                 RADEON_CG_SUPPORT_GFX_CGTS |
2571                 RADEON_CG_SUPPORT_GFX_CP_LS |
2572                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2573                 RADEON_CG_SUPPORT_MC_LS |
2574                 RADEON_CG_SUPPORT_MC_MGCG |
2575                 RADEON_CG_SUPPORT_SDMA_MGCG |
2576                 RADEON_CG_SUPPORT_BIF_LS |
2577                 RADEON_CG_SUPPORT_HDP_LS |
2578                 RADEON_CG_SUPPORT_HDP_MGCG;
2579             rdev->pg_flags = 0;
2580             break;
2581         default:
2582             rdev->cg_flags = 0;
2583             rdev->pg_flags = 0;
2584             break;
2585         }
2586         break;
2587     case CHIP_BONAIRE:
2588     case CHIP_HAWAII:
2589         rdev->asic = &ci_asic;
2590         rdev->num_crtc = 6;
2591         rdev->has_uvd = true;
2592         rdev->has_vce = true;
2593         if (rdev->family == CHIP_BONAIRE) {
2594             rdev->cg_flags =
2595                 RADEON_CG_SUPPORT_GFX_MGCG |
2596                 RADEON_CG_SUPPORT_GFX_MGLS |
2597                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2598                 RADEON_CG_SUPPORT_GFX_CGLS |
2599                 RADEON_CG_SUPPORT_GFX_CGTS |
2600                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2601                 RADEON_CG_SUPPORT_GFX_CP_LS |
2602                 RADEON_CG_SUPPORT_MC_LS |
2603                 RADEON_CG_SUPPORT_MC_MGCG |
2604                 RADEON_CG_SUPPORT_SDMA_MGCG |
2605                 RADEON_CG_SUPPORT_SDMA_LS |
2606                 RADEON_CG_SUPPORT_BIF_LS |
2607                 RADEON_CG_SUPPORT_VCE_MGCG |
2608                 RADEON_CG_SUPPORT_UVD_MGCG |
2609                 RADEON_CG_SUPPORT_HDP_LS |
2610                 RADEON_CG_SUPPORT_HDP_MGCG;
2611             rdev->pg_flags = 0;
2612         } else {
2613             rdev->cg_flags =
2614                 RADEON_CG_SUPPORT_GFX_MGCG |
2615                 RADEON_CG_SUPPORT_GFX_MGLS |
2616                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2617                 RADEON_CG_SUPPORT_GFX_CGLS |
2618                 RADEON_CG_SUPPORT_GFX_CGTS |
2619                 RADEON_CG_SUPPORT_GFX_CP_LS |
2620                 RADEON_CG_SUPPORT_MC_LS |
2621                 RADEON_CG_SUPPORT_MC_MGCG |
2622                 RADEON_CG_SUPPORT_SDMA_MGCG |
2623                 RADEON_CG_SUPPORT_SDMA_LS |
2624                 RADEON_CG_SUPPORT_BIF_LS |
2625                 RADEON_CG_SUPPORT_VCE_MGCG |
2626                 RADEON_CG_SUPPORT_UVD_MGCG |
2627                 RADEON_CG_SUPPORT_HDP_LS |
2628                 RADEON_CG_SUPPORT_HDP_MGCG;
2629             rdev->pg_flags = 0;
2630         }
2631         break;
2632     case CHIP_KAVERI:
2633     case CHIP_KABINI:
2634     case CHIP_MULLINS:
2635         rdev->asic = &kv_asic;
2636         /* set num crtcs */
2637         if (rdev->family == CHIP_KAVERI) {
2638             rdev->num_crtc = 4;
2639             rdev->cg_flags =
2640                 RADEON_CG_SUPPORT_GFX_MGCG |
2641                 RADEON_CG_SUPPORT_GFX_MGLS |
2642                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2643                 RADEON_CG_SUPPORT_GFX_CGLS |
2644                 RADEON_CG_SUPPORT_GFX_CGTS |
2645                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2646                 RADEON_CG_SUPPORT_GFX_CP_LS |
2647                 RADEON_CG_SUPPORT_SDMA_MGCG |
2648                 RADEON_CG_SUPPORT_SDMA_LS |
2649                 RADEON_CG_SUPPORT_BIF_LS |
2650                 RADEON_CG_SUPPORT_VCE_MGCG |
2651                 RADEON_CG_SUPPORT_UVD_MGCG |
2652                 RADEON_CG_SUPPORT_HDP_LS |
2653                 RADEON_CG_SUPPORT_HDP_MGCG;
2654             rdev->pg_flags = 0;
2655                 /*RADEON_PG_SUPPORT_GFX_PG |
2656                 RADEON_PG_SUPPORT_GFX_SMG |
2657                 RADEON_PG_SUPPORT_GFX_DMG |
2658                 RADEON_PG_SUPPORT_UVD |
2659                 RADEON_PG_SUPPORT_VCE |
2660                 RADEON_PG_SUPPORT_CP |
2661                 RADEON_PG_SUPPORT_GDS |
2662                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2663                 RADEON_PG_SUPPORT_ACP |
2664                 RADEON_PG_SUPPORT_SAMU;*/
2665         } else {
2666             rdev->num_crtc = 2;
2667             rdev->cg_flags =
2668                 RADEON_CG_SUPPORT_GFX_MGCG |
2669                 RADEON_CG_SUPPORT_GFX_MGLS |
2670                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2671                 RADEON_CG_SUPPORT_GFX_CGLS |
2672                 RADEON_CG_SUPPORT_GFX_CGTS |
2673                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2674                 RADEON_CG_SUPPORT_GFX_CP_LS |
2675                 RADEON_CG_SUPPORT_SDMA_MGCG |
2676                 RADEON_CG_SUPPORT_SDMA_LS |
2677                 RADEON_CG_SUPPORT_BIF_LS |
2678                 RADEON_CG_SUPPORT_VCE_MGCG |
2679                 RADEON_CG_SUPPORT_UVD_MGCG |
2680                 RADEON_CG_SUPPORT_HDP_LS |
2681                 RADEON_CG_SUPPORT_HDP_MGCG;
2682             rdev->pg_flags = 0;
2683                 /*RADEON_PG_SUPPORT_GFX_PG |
2684                 RADEON_PG_SUPPORT_GFX_SMG |
2685                 RADEON_PG_SUPPORT_UVD |
2686                 RADEON_PG_SUPPORT_VCE |
2687                 RADEON_PG_SUPPORT_CP |
2688                 RADEON_PG_SUPPORT_GDS |
2689                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2690                 RADEON_PG_SUPPORT_SAMU;*/
2691         }
2692         rdev->has_uvd = true;
2693         rdev->has_vce = true;
2694         break;
2695     default:
2696         /* FIXME: not supported yet */
2697         return -EINVAL;
2698     }
2699
2700     if (rdev->flags & RADEON_IS_IGP) {
2701         rdev->asic->pm.get_memory_clock = NULL;
2702         rdev->asic->pm.set_memory_clock = NULL;
2703     }
2704
2705     if (!radeon_uvd)
2706         rdev->has_uvd = false;
2707     if (!radeon_vce)
2708         rdev->has_vce = false;
2709
2710     return 0;
2711 }
2712