Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Christian König.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Christian König
0025  */
0026 #include <linux/hdmi.h>
0027 #include <linux/gcd.h>
0028 
0029 #include <drm/radeon_drm.h>
0030 #include "radeon.h"
0031 #include "radeon_asic.h"
0032 #include "radeon_audio.h"
0033 #include "r600.h"
0034 #include "r600d.h"
0035 #include "atom.h"
0036 
0037 /*
0038  * HDMI color format
0039  */
0040 enum r600_hdmi_color_format {
0041     RGB = 0,
0042     YCC_422 = 1,
0043     YCC_444 = 2
0044 };
0045 
0046 /*
0047  * IEC60958 status bits
0048  */
0049 enum r600_hdmi_iec_status_bits {
0050     AUDIO_STATUS_DIG_ENABLE   = 0x01,
0051     AUDIO_STATUS_V            = 0x02,
0052     AUDIO_STATUS_VCFG         = 0x04,
0053     AUDIO_STATUS_EMPHASIS     = 0x08,
0054     AUDIO_STATUS_COPYRIGHT    = 0x10,
0055     AUDIO_STATUS_NONAUDIO     = 0x20,
0056     AUDIO_STATUS_PROFESSIONAL = 0x40,
0057     AUDIO_STATUS_LEVEL        = 0x80
0058 };
0059 
0060 static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev)
0061 {
0062     struct r600_audio_pin status = {};
0063     uint32_t value;
0064 
0065     value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
0066 
0067     /* number of channels */
0068     status.channels = (value & 0x7) + 1;
0069 
0070     /* bits per sample */
0071     switch ((value & 0xF0) >> 4) {
0072     case 0x0:
0073         status.bits_per_sample = 8;
0074         break;
0075     case 0x1:
0076         status.bits_per_sample = 16;
0077         break;
0078     case 0x2:
0079         status.bits_per_sample = 20;
0080         break;
0081     case 0x3:
0082         status.bits_per_sample = 24;
0083         break;
0084     case 0x4:
0085         status.bits_per_sample = 32;
0086         break;
0087     default:
0088         dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n",
0089             (int)value);
0090         status.bits_per_sample = 16;
0091     }
0092 
0093     /* current sampling rate in HZ */
0094     if (value & 0x4000)
0095         status.rate = 44100;
0096     else
0097         status.rate = 48000;
0098     status.rate *= ((value >> 11) & 0x7) + 1;
0099     status.rate /= ((value >> 8) & 0x7) + 1;
0100 
0101     value = RREG32(R600_AUDIO_STATUS_BITS);
0102 
0103     /* iec 60958 status bits */
0104     status.status_bits = value & 0xff;
0105 
0106     /* iec 60958 category code */
0107     status.category_code = (value >> 8) & 0xff;
0108 
0109     return status;
0110 }
0111 
0112 /*
0113  * update all hdmi interfaces with current audio parameters
0114  */
0115 void r600_audio_update_hdmi(struct work_struct *work)
0116 {
0117     struct radeon_device *rdev = container_of(work, struct radeon_device,
0118                           audio_work);
0119     struct drm_device *dev = rdev->ddev;
0120     struct r600_audio_pin audio_status = r600_audio_status(rdev);
0121     struct drm_encoder *encoder;
0122     bool changed = false;
0123 
0124     if (rdev->audio.pin[0].channels != audio_status.channels ||
0125         rdev->audio.pin[0].rate != audio_status.rate ||
0126         rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample ||
0127         rdev->audio.pin[0].status_bits != audio_status.status_bits ||
0128         rdev->audio.pin[0].category_code != audio_status.category_code) {
0129         rdev->audio.pin[0] = audio_status;
0130         changed = true;
0131     }
0132 
0133     list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
0134         if (!radeon_encoder_is_digital(encoder))
0135             continue;
0136         if (changed || r600_hdmi_buffer_status_changed(encoder))
0137             r600_hdmi_update_audio_settings(encoder);
0138     }
0139 }
0140 
0141 /* enable the audio stream */
0142 void r600_audio_enable(struct radeon_device *rdev,
0143                struct r600_audio_pin *pin,
0144                u8 enable_mask)
0145 {
0146     u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
0147 
0148     if (!pin)
0149         return;
0150 
0151     if (enable_mask) {
0152         tmp |= AUDIO_ENABLED;
0153         if (enable_mask & 1)
0154             tmp |= PIN0_AUDIO_ENABLED;
0155         if (enable_mask & 2)
0156             tmp |= PIN1_AUDIO_ENABLED;
0157         if (enable_mask & 4)
0158             tmp |= PIN2_AUDIO_ENABLED;
0159         if (enable_mask & 8)
0160             tmp |= PIN3_AUDIO_ENABLED;
0161     } else {
0162         tmp &= ~(AUDIO_ENABLED |
0163              PIN0_AUDIO_ENABLED |
0164              PIN1_AUDIO_ENABLED |
0165              PIN2_AUDIO_ENABLED |
0166              PIN3_AUDIO_ENABLED);
0167     }
0168 
0169     WREG32(AZ_HOT_PLUG_CONTROL, tmp);
0170 }
0171 
0172 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev)
0173 {
0174     /* only one pin on 6xx-NI */
0175     return &rdev->audio.pin[0];
0176 }
0177 
0178 void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset,
0179     const struct radeon_hdmi_acr *acr)
0180 {
0181     struct drm_device *dev = encoder->dev;
0182     struct radeon_device *rdev = dev->dev_private;
0183 
0184     /* DCE 3.0 uses register that's normally for CRC_CONTROL */
0185     uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :
0186                        HDMI0_ACR_PACKET_CONTROL;
0187     WREG32_P(acr_ctl + offset,
0188         HDMI0_ACR_SOURCE |      /* select SW CTS value */
0189         HDMI0_ACR_AUTO_SEND,    /* allow hw to sent ACR packets when required */
0190         ~(HDMI0_ACR_SOURCE |
0191         HDMI0_ACR_AUTO_SEND));
0192 
0193     WREG32_P(HDMI0_ACR_32_0 + offset,
0194         HDMI0_ACR_CTS_32(acr->cts_32khz),
0195         ~HDMI0_ACR_CTS_32_MASK);
0196     WREG32_P(HDMI0_ACR_32_1 + offset,
0197         HDMI0_ACR_N_32(acr->n_32khz),
0198         ~HDMI0_ACR_N_32_MASK);
0199 
0200     WREG32_P(HDMI0_ACR_44_0 + offset,
0201         HDMI0_ACR_CTS_44(acr->cts_44_1khz),
0202         ~HDMI0_ACR_CTS_44_MASK);
0203     WREG32_P(HDMI0_ACR_44_1 + offset,
0204         HDMI0_ACR_N_44(acr->n_44_1khz),
0205         ~HDMI0_ACR_N_44_MASK);
0206 
0207     WREG32_P(HDMI0_ACR_48_0 + offset,
0208         HDMI0_ACR_CTS_48(acr->cts_48khz),
0209         ~HDMI0_ACR_CTS_48_MASK);
0210     WREG32_P(HDMI0_ACR_48_1 + offset,
0211         HDMI0_ACR_N_48(acr->n_48khz),
0212         ~HDMI0_ACR_N_48_MASK);
0213 }
0214 
0215 /*
0216  * build a HDMI Video Info Frame
0217  */
0218 void r600_set_avi_packet(struct radeon_device *rdev, u32 offset,
0219              unsigned char *buffer, size_t size)
0220 {
0221     uint8_t *frame = buffer + 3;
0222 
0223     WREG32(HDMI0_AVI_INFO0 + offset,
0224         frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
0225     WREG32(HDMI0_AVI_INFO1 + offset,
0226         frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
0227     WREG32(HDMI0_AVI_INFO2 + offset,
0228         frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
0229     WREG32(HDMI0_AVI_INFO3 + offset,
0230         frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));
0231 
0232     WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
0233           HDMI0_AVI_INFO_LINE(2));  /* anything other than 0 */
0234 
0235     WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
0236           HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
0237           HDMI0_AVI_INFO_CONT); /* send AVI info frames every frame/field */
0238 
0239 }
0240 
0241 /*
0242  * build a Audio Info Frame
0243  */
0244 static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
0245                          const void *buffer, size_t size)
0246 {
0247     struct drm_device *dev = encoder->dev;
0248     struct radeon_device *rdev = dev->dev_private;
0249     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0250     struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
0251     uint32_t offset = dig->afmt->offset;
0252     const u8 *frame = buffer + 3;
0253 
0254     WREG32(HDMI0_AUDIO_INFO0 + offset,
0255         frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
0256     WREG32(HDMI0_AUDIO_INFO1 + offset,
0257         frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
0258 }
0259 
0260 /*
0261  * test if audio buffer is filled enough to start playing
0262  */
0263 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
0264 {
0265     struct drm_device *dev = encoder->dev;
0266     struct radeon_device *rdev = dev->dev_private;
0267     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0268     struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
0269     uint32_t offset = dig->afmt->offset;
0270 
0271     return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
0272 }
0273 
0274 /*
0275  * have buffer status changed since last call?
0276  */
0277 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
0278 {
0279     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0280     struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
0281     int status, result;
0282 
0283     if (!dig->afmt || !dig->afmt->enabled)
0284         return 0;
0285 
0286     status = r600_hdmi_is_audio_buffer_filled(encoder);
0287     result = dig->afmt->last_buffer_filled_status != status;
0288     dig->afmt->last_buffer_filled_status = status;
0289 
0290     return result;
0291 }
0292 
0293 /*
0294  * write the audio workaround status to the hardware
0295  */
0296 void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
0297 {
0298     struct drm_device *dev = encoder->dev;
0299     struct radeon_device *rdev = dev->dev_private;
0300     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0301     struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
0302     uint32_t offset = dig->afmt->offset;
0303     bool hdmi_audio_workaround = false; /* FIXME */
0304     u32 value;
0305 
0306     if (!hdmi_audio_workaround ||
0307         r600_hdmi_is_audio_buffer_filled(encoder))
0308         value = 0; /* disable workaround */
0309     else
0310         value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
0311     WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
0312          value, ~HDMI0_AUDIO_TEST_EN);
0313 }
0314 
0315 void r600_hdmi_audio_set_dto(struct radeon_device *rdev,
0316                  struct radeon_crtc *crtc, unsigned int clock)
0317 {
0318     struct radeon_encoder *radeon_encoder;
0319     struct radeon_encoder_atom_dig *dig;
0320 
0321     if (!crtc)
0322         return;
0323 
0324     radeon_encoder = to_radeon_encoder(crtc->encoder);
0325     dig = radeon_encoder->enc_priv;
0326 
0327     if (!dig)
0328         return;
0329 
0330     if (dig->dig_encoder == 0) {
0331         WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100);
0332         WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
0333         WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
0334     } else {
0335         WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100);
0336         WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
0337         WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
0338     }
0339 }
0340 
0341 void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
0342 {
0343     struct drm_device *dev = encoder->dev;
0344     struct radeon_device *rdev = dev->dev_private;
0345 
0346     WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
0347         HDMI0_NULL_SEND |   /* send null packets when required */
0348         HDMI0_GC_SEND |     /* send general control packets */
0349         HDMI0_GC_CONT);     /* send general control packets every frame */
0350 }
0351 
0352 void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset)
0353 {
0354     struct drm_device *dev = encoder->dev;
0355     struct radeon_device *rdev = dev->dev_private;
0356 
0357     WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
0358         HDMI0_AUDIO_SAMPLE_SEND |           /* send audio packets */
0359         HDMI0_AUDIO_DELAY_EN(1) |           /* default audio delay */
0360         HDMI0_AUDIO_PACKETS_PER_LINE(3) |   /* should be suffient for all audio modes and small enough for all hblanks */
0361         HDMI0_60958_CS_UPDATE,              /* allow 60958 channel status fields to be updated */
0362         ~(HDMI0_AUDIO_SAMPLE_SEND |
0363         HDMI0_AUDIO_DELAY_EN_MASK |
0364         HDMI0_AUDIO_PACKETS_PER_LINE_MASK |
0365         HDMI0_60958_CS_UPDATE));
0366 
0367     WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
0368         HDMI0_AUDIO_INFO_SEND |     /* enable audio info frames (frames won't be set until audio is enabled) */
0369         HDMI0_AUDIO_INFO_UPDATE);   /* required for audio info values to be updated */
0370 
0371     WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
0372         HDMI0_AUDIO_INFO_LINE(2),   /* anything other than 0 */
0373         ~HDMI0_AUDIO_INFO_LINE_MASK);
0374 
0375     WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
0376         ~(HDMI0_GENERIC0_SEND |
0377         HDMI0_GENERIC0_CONT |
0378         HDMI0_GENERIC0_UPDATE |
0379         HDMI0_GENERIC1_SEND |
0380         HDMI0_GENERIC1_CONT |
0381         HDMI0_GENERIC0_LINE_MASK |
0382         HDMI0_GENERIC1_LINE_MASK));
0383 
0384     WREG32_P(HDMI0_60958_0 + offset,
0385         HDMI0_60958_CS_CHANNEL_NUMBER_L(1),
0386         ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK |
0387         HDMI0_60958_CS_CLOCK_ACCURACY_MASK));
0388 
0389     WREG32_P(HDMI0_60958_1 + offset,
0390         HDMI0_60958_CS_CHANNEL_NUMBER_R(2),
0391         ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK);
0392 }
0393 
0394 void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
0395 {
0396     struct drm_device *dev = encoder->dev;
0397     struct radeon_device *rdev = dev->dev_private;
0398 
0399     if (mute)
0400         WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);
0401     else
0402         WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);
0403 }
0404 
0405 /**
0406  * r600_hdmi_update_audio_settings - Update audio infoframe
0407  *
0408  * @encoder: drm encoder
0409  *
0410  * Gets info about current audio stream and updates audio infoframe.
0411  */
0412 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
0413 {
0414     struct drm_device *dev = encoder->dev;
0415     struct radeon_device *rdev = dev->dev_private;
0416     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0417     struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
0418     struct r600_audio_pin audio = r600_audio_status(rdev);
0419     uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
0420     struct hdmi_audio_infoframe frame;
0421     uint32_t offset;
0422     uint32_t value;
0423     ssize_t err;
0424 
0425     if (!dig->afmt || !dig->afmt->enabled)
0426         return;
0427     offset = dig->afmt->offset;
0428 
0429     DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
0430          r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
0431           audio.channels, audio.rate, audio.bits_per_sample);
0432     DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
0433           (int)audio.status_bits, (int)audio.category_code);
0434 
0435     err = hdmi_audio_infoframe_init(&frame);
0436     if (err < 0) {
0437         DRM_ERROR("failed to setup audio infoframe\n");
0438         return;
0439     }
0440 
0441     frame.channels = audio.channels;
0442 
0443     err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
0444     if (err < 0) {
0445         DRM_ERROR("failed to pack audio infoframe\n");
0446         return;
0447     }
0448 
0449     value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
0450     if (value & HDMI0_AUDIO_TEST_EN)
0451         WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
0452                value & ~HDMI0_AUDIO_TEST_EN);
0453 
0454     WREG32_OR(HDMI0_CONTROL + offset,
0455           HDMI0_ERROR_ACK);
0456 
0457     WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
0458            ~HDMI0_AUDIO_INFO_SOURCE);
0459 
0460     r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
0461 
0462     WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
0463           HDMI0_AUDIO_INFO_CONT |
0464           HDMI0_AUDIO_INFO_UPDATE);
0465 }
0466 
0467 /*
0468  * enable the HDMI engine
0469  */
0470 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
0471 {
0472     struct drm_device *dev = encoder->dev;
0473     struct radeon_device *rdev = dev->dev_private;
0474     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0475     struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
0476     u32 hdmi = HDMI0_ERROR_ACK;
0477 
0478     if (!dig || !dig->afmt)
0479         return;
0480 
0481     /* Older chipsets require setting HDMI and routing manually */
0482     if (!ASIC_IS_DCE3(rdev)) {
0483         if (enable)
0484             hdmi |= HDMI0_ENABLE;
0485         switch (radeon_encoder->encoder_id) {
0486         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
0487             if (enable) {
0488                 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
0489                 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
0490             } else {
0491                 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
0492             }
0493             break;
0494         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
0495             if (enable) {
0496                 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
0497                 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
0498             } else {
0499                 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
0500             }
0501             break;
0502         case ENCODER_OBJECT_ID_INTERNAL_DDI:
0503             if (enable) {
0504                 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
0505                 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
0506             } else {
0507                 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
0508             }
0509             break;
0510         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
0511             if (enable)
0512                 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
0513             break;
0514         default:
0515             dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
0516                 radeon_encoder->encoder_id);
0517             break;
0518         }
0519         WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
0520     }
0521 
0522     if (rdev->irq.installed) {
0523         /* if irq is available use it */
0524         /* XXX: shouldn't need this on any asics.  Double check DCE2/3 */
0525         if (enable)
0526             radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
0527         else
0528             radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
0529     }
0530 
0531     dig->afmt->enabled = enable;
0532 
0533     DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
0534           enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
0535 }
0536
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!