drm/radeon/r600_dpm.h

0001 /*
0002  * Copyright 2011 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __R600_DPM_H__
0024 #define __R600_DPM_H__
0025
0026 #include "radeon.h"
0027
0028 #define R600_ASI_DFLT                                10000
0029 #define R600_BSP_DFLT                                0x41EB
0030 #define R600_BSU_DFLT                                0x2
0031 #define R600_AH_DFLT                                 5
0032 #define R600_RLP_DFLT                                25
0033 #define R600_RMP_DFLT                                65
0034 #define R600_LHP_DFLT                                40
0035 #define R600_LMP_DFLT                                15
0036 #define R600_TD_DFLT                                 0
0037 #define R600_UTC_DFLT_00                             0x24
0038 #define R600_UTC_DFLT_01                             0x22
0039 #define R600_UTC_DFLT_02                             0x22
0040 #define R600_UTC_DFLT_03                             0x22
0041 #define R600_UTC_DFLT_04                             0x22
0042 #define R600_UTC_DFLT_05                             0x22
0043 #define R600_UTC_DFLT_06                             0x22
0044 #define R600_UTC_DFLT_07                             0x22
0045 #define R600_UTC_DFLT_08                             0x22
0046 #define R600_UTC_DFLT_09                             0x22
0047 #define R600_UTC_DFLT_10                             0x22
0048 #define R600_UTC_DFLT_11                             0x22
0049 #define R600_UTC_DFLT_12                             0x22
0050 #define R600_UTC_DFLT_13                             0x22
0051 #define R600_UTC_DFLT_14                             0x22
0052 #define R600_DTC_DFLT_00                             0x24
0053 #define R600_DTC_DFLT_01                             0x22
0054 #define R600_DTC_DFLT_02                             0x22
0055 #define R600_DTC_DFLT_03                             0x22
0056 #define R600_DTC_DFLT_04                             0x22
0057 #define R600_DTC_DFLT_05                             0x22
0058 #define R600_DTC_DFLT_06                             0x22
0059 #define R600_DTC_DFLT_07                             0x22
0060 #define R600_DTC_DFLT_08                             0x22
0061 #define R600_DTC_DFLT_09                             0x22
0062 #define R600_DTC_DFLT_10                             0x22
0063 #define R600_DTC_DFLT_11                             0x22
0064 #define R600_DTC_DFLT_12                             0x22
0065 #define R600_DTC_DFLT_13                             0x22
0066 #define R600_DTC_DFLT_14                             0x22
0067 #define R600_VRC_DFLT                                0x0000C003
0068 #define R600_VOLTAGERESPONSETIME_DFLT                1000
0069 #define R600_BACKBIASRESPONSETIME_DFLT               1000
0070 #define R600_VRU_DFLT                                0x3
0071 #define R600_SPLLSTEPTIME_DFLT                       0x1000
0072 #define R600_SPLLSTEPUNIT_DFLT                       0x3
0073 #define R600_TPU_DFLT                                0
0074 #define R600_TPC_DFLT                                0x200
0075 #define R600_SSTU_DFLT                               0
0076 #define R600_SST_DFLT                                0x00C8
0077 #define R600_GICST_DFLT                              0x200
0078 #define R600_FCT_DFLT                                0x0400
0079 #define R600_FCTU_DFLT                               0
0080 #define R600_CTXCGTT3DRPHC_DFLT                      0x20
0081 #define R600_CTXCGTT3DRSDC_DFLT                      0x40
0082 #define R600_VDDC3DOORPHC_DFLT                       0x100
0083 #define R600_VDDC3DOORSDC_DFLT                       0x7
0084 #define R600_VDDC3DOORSU_DFLT                        0
0085 #define R600_MPLLLOCKTIME_DFLT                       100
0086 #define R600_MPLLRESETTIME_DFLT                      150
0087 #define R600_VCOSTEPPCT_DFLT                          20
0088 #define R600_ENDINGVCOSTEPPCT_DFLT                    5
0089 #define R600_REFERENCEDIVIDER_DFLT                    4
0090
0091 #define R600_PM_NUMBER_OF_TC 15
0092 #define R600_PM_NUMBER_OF_SCLKS 20
0093 #define R600_PM_NUMBER_OF_MCLKS 4
0094 #define R600_PM_NUMBER_OF_VOLTAGE_LEVELS 4
0095 #define R600_PM_NUMBER_OF_ACTIVITY_LEVELS 3
0096
0097 /* XXX are these ok? */
0098 #define R600_TEMP_RANGE_MIN (90 * 1000)
0099 #define R600_TEMP_RANGE_MAX (120 * 1000)
0100
0101 #define FDO_PWM_MODE_STATIC  1
0102 #define FDO_PWM_MODE_STATIC_RPM 5
0103
0104 enum r600_power_level {
0105     R600_POWER_LEVEL_LOW = 0,
0106     R600_POWER_LEVEL_MEDIUM = 1,
0107     R600_POWER_LEVEL_HIGH = 2,
0108     R600_POWER_LEVEL_CTXSW = 3,
0109 };
0110
0111 enum r600_td {
0112     R600_TD_AUTO,
0113     R600_TD_UP,
0114     R600_TD_DOWN,
0115 };
0116
0117 enum r600_display_watermark {
0118     R600_DISPLAY_WATERMARK_LOW = 0,
0119     R600_DISPLAY_WATERMARK_HIGH = 1,
0120 };
0121
0122 enum r600_display_gap
0123 {
0124     R600_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
0125     R600_PM_DISPLAY_GAP_VBLANK       = 1,
0126     R600_PM_DISPLAY_GAP_WATERMARK    = 2,
0127     R600_PM_DISPLAY_GAP_IGNORE       = 3,
0128 };
0129
0130 extern const u32 r600_utc[R600_PM_NUMBER_OF_TC];
0131 extern const u32 r600_dtc[R600_PM_NUMBER_OF_TC];
0132
0133 void r600_dpm_print_class_info(u32 class, u32 class2);
0134 void r600_dpm_print_cap_info(u32 caps);
0135 void r600_dpm_print_ps_status(struct radeon_device *rdev,
0136                   struct radeon_ps *rps);
0137 u32 r600_dpm_get_vblank_time(struct radeon_device *rdev);
0138 u32 r600_dpm_get_vrefresh(struct radeon_device *rdev);
0139 bool r600_is_uvd_state(u32 class, u32 class2);
0140 void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
0141                 u32 *p, u32 *u);
0142 int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th);
0143 void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable);
0144 void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable);
0145 void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable);
0146 void r600_enable_acpi_pm(struct radeon_device *rdev);
0147 void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable);
0148 bool r600_dynamicpm_enabled(struct radeon_device *rdev);
0149 void r600_enable_sclk_control(struct radeon_device *rdev, bool enable);
0150 void r600_enable_mclk_control(struct radeon_device *rdev, bool enable);
0151 void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable);
0152 void r600_wait_for_spll_change(struct radeon_device *rdev);
0153 void r600_set_bsp(struct radeon_device *rdev, u32 u, u32 p);
0154 void r600_set_at(struct radeon_device *rdev,
0155          u32 l_to_m, u32 m_to_h,
0156          u32 h_to_m, u32 m_to_l);
0157 void r600_set_tc(struct radeon_device *rdev, u32 index, u32 u_t, u32 d_t);
0158 void r600_select_td(struct radeon_device *rdev, enum r600_td td);
0159 void r600_set_vrc(struct radeon_device *rdev, u32 vrv);
0160 void r600_set_tpu(struct radeon_device *rdev, u32 u);
0161 void r600_set_tpc(struct radeon_device *rdev, u32 c);
0162 void r600_set_sstu(struct radeon_device *rdev, u32 u);
0163 void r600_set_sst(struct radeon_device *rdev, u32 t);
0164 void r600_set_git(struct radeon_device *rdev, u32 t);
0165 void r600_set_fctu(struct radeon_device *rdev, u32 u);
0166 void r600_set_fct(struct radeon_device *rdev, u32 t);
0167 void r600_set_ctxcgtt3d_rphc(struct radeon_device *rdev, u32 p);
0168 void r600_set_ctxcgtt3d_rsdc(struct radeon_device *rdev, u32 s);
0169 void r600_set_vddc3d_oorsu(struct radeon_device *rdev, u32 u);
0170 void r600_set_vddc3d_oorphc(struct radeon_device *rdev, u32 p);
0171 void r600_set_vddc3d_oorsdc(struct radeon_device *rdev, u32 s);
0172 void r600_set_mpll_lock_time(struct radeon_device *rdev, u32 lock_time);
0173 void r600_set_mpll_reset_time(struct radeon_device *rdev, u32 reset_time);
0174 void r600_engine_clock_entry_enable(struct radeon_device *rdev,
0175                     u32 index, bool enable);
0176 void r600_engine_clock_entry_enable_pulse_skipping(struct radeon_device *rdev,
0177                            u32 index, bool enable);
0178 void r600_engine_clock_entry_enable_post_divider(struct radeon_device *rdev,
0179                          u32 index, bool enable);
0180 void r600_engine_clock_entry_set_post_divider(struct radeon_device *rdev,
0181                           u32 index, u32 divider);
0182 void r600_engine_clock_entry_set_reference_divider(struct radeon_device *rdev,
0183                            u32 index, u32 divider);
0184 void r600_engine_clock_entry_set_feedback_divider(struct radeon_device *rdev,
0185                           u32 index, u32 divider);
0186 void r600_engine_clock_entry_set_step_time(struct radeon_device *rdev,
0187                        u32 index, u32 step_time);
0188 void r600_vid_rt_set_ssu(struct radeon_device *rdev, u32 u);
0189 void r600_vid_rt_set_vru(struct radeon_device *rdev, u32 u);
0190 void r600_vid_rt_set_vrt(struct radeon_device *rdev, u32 rt);
0191 void r600_voltage_control_enable_pins(struct radeon_device *rdev,
0192                       u64 mask);
0193 void r600_voltage_control_program_voltages(struct radeon_device *rdev,
0194                        enum r600_power_level index, u64 pins);
0195 void r600_voltage_control_deactivate_static_control(struct radeon_device *rdev,
0196                             u64 mask);
0197 void r600_power_level_enable(struct radeon_device *rdev,
0198                  enum r600_power_level index, bool enable);
0199 void r600_power_level_set_voltage_index(struct radeon_device *rdev,
0200                     enum r600_power_level index, u32 voltage_index);
0201 void r600_power_level_set_mem_clock_index(struct radeon_device *rdev,
0202                       enum r600_power_level index, u32 mem_clock_index);
0203 void r600_power_level_set_eng_clock_index(struct radeon_device *rdev,
0204                       enum r600_power_level index, u32 eng_clock_index);
0205 void r600_power_level_set_watermark_id(struct radeon_device *rdev,
0206                        enum r600_power_level index,
0207                        enum r600_display_watermark watermark_id);
0208 void r600_power_level_set_pcie_gen2(struct radeon_device *rdev,
0209                     enum r600_power_level index, bool compatible);
0210 enum r600_power_level r600_power_level_get_current_index(struct radeon_device *rdev);
0211 enum r600_power_level r600_power_level_get_target_index(struct radeon_device *rdev);
0212 void r600_power_level_set_enter_index(struct radeon_device *rdev,
0213                       enum r600_power_level index);
0214 void r600_wait_for_power_level_unequal(struct radeon_device *rdev,
0215                        enum r600_power_level index);
0216 void r600_wait_for_power_level(struct radeon_device *rdev,
0217                    enum r600_power_level index);
0218 void r600_start_dpm(struct radeon_device *rdev);
0219 void r600_stop_dpm(struct radeon_device *rdev);
0220
0221 bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor);
0222
0223 int r600_get_platform_caps(struct radeon_device *rdev);
0224
0225 int r600_parse_extended_power_table(struct radeon_device *rdev);
0226 void r600_free_extended_power_table(struct radeon_device *rdev);
0227
0228 enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev,
0229                            u32 sys_mask,
0230                            enum radeon_pcie_gen asic_gen,
0231                            enum radeon_pcie_gen default_gen);
0232
0233 u16 r600_get_pcie_lane_support(struct radeon_device *rdev,
0234                    u16 asic_lanes,
0235                    u16 default_lanes);
0236 u8 r600_encode_pci_lane_width(u32 lanes);
0237
0238 #endif