drm/radeon/r600_dma.c

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Alex Deucher
0023  */
0024
0025 #include "radeon.h"
0026 #include "radeon_asic.h"
0027 #include "r600.h"
0028 #include "r600d.h"
0029
0030 /*
0031  * DMA
0032  * Starting with R600, the GPU has an asynchronous
0033  * DMA engine.  The programming model is very similar
0034  * to the 3D engine (ring buffer, IBs, etc.), but the
0035  * DMA controller has it's own packet format that is
0036  * different form the PM4 format used by the 3D engine.
0037  * It supports copying data, writing embedded data,
0038  * solid fills, and a number of other things.  It also
0039  * has support for tiling/detiling of buffers.
0040  */
0041
0042 /**
0043  * r600_dma_get_rptr - get the current read pointer
0044  *
0045  * @rdev: radeon_device pointer
0046  * @ring: radeon ring pointer
0047  *
0048  * Get the current rptr from the hardware (r6xx+).
0049  */
0050 uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
0051                struct radeon_ring *ring)
0052 {
0053     u32 rptr;
0054
0055     if (rdev->wb.enabled)
0056         rptr = rdev->wb.wb[ring->rptr_offs/4];
0057     else
0058         rptr = RREG32(DMA_RB_RPTR);
0059
0060     return (rptr & 0x3fffc) >> 2;
0061 }
0062
0063 /**
0064  * r600_dma_get_wptr - get the current write pointer
0065  *
0066  * @rdev: radeon_device pointer
0067  * @ring: radeon ring pointer
0068  *
0069  * Get the current wptr from the hardware (r6xx+).
0070  */
0071 uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
0072                struct radeon_ring *ring)
0073 {
0074     return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2;
0075 }
0076
0077 /**
0078  * r600_dma_set_wptr - commit the write pointer
0079  *
0080  * @rdev: radeon_device pointer
0081  * @ring: radeon ring pointer
0082  *
0083  * Write the wptr back to the hardware (r6xx+).
0084  */
0085 void r600_dma_set_wptr(struct radeon_device *rdev,
0086                struct radeon_ring *ring)
0087 {
0088     WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc);
0089 }
0090
0091 /**
0092  * r600_dma_stop - stop the async dma engine
0093  *
0094  * @rdev: radeon_device pointer
0095  *
0096  * Stop the async dma engine (r6xx-evergreen).
0097  */
0098 void r600_dma_stop(struct radeon_device *rdev)
0099 {
0100     u32 rb_cntl = RREG32(DMA_RB_CNTL);
0101
0102     if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
0103         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
0104
0105     rb_cntl &= ~DMA_RB_ENABLE;
0106     WREG32(DMA_RB_CNTL, rb_cntl);
0107
0108     rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
0109 }
0110
0111 /**
0112  * r600_dma_resume - setup and start the async dma engine
0113  *
0114  * @rdev: radeon_device pointer
0115  *
0116  * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
0117  * Returns 0 for success, error for failure.
0118  */
0119 int r600_dma_resume(struct radeon_device *rdev)
0120 {
0121     struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
0122     u32 rb_cntl, dma_cntl, ib_cntl;
0123     u32 rb_bufsz;
0124     int r;
0125
0126     WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
0127     WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
0128
0129     /* Set ring buffer size in dwords */
0130     rb_bufsz = order_base_2(ring->ring_size / 4);
0131     rb_cntl = rb_bufsz << 1;
0132 #ifdef __BIG_ENDIAN
0133     rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
0134 #endif
0135     WREG32(DMA_RB_CNTL, rb_cntl);
0136
0137     /* Initialize the ring buffer's read and write pointers */
0138     WREG32(DMA_RB_RPTR, 0);
0139     WREG32(DMA_RB_WPTR, 0);
0140
0141     /* set the wb address whether it's enabled or not */
0142     WREG32(DMA_RB_RPTR_ADDR_HI,
0143            upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
0144     WREG32(DMA_RB_RPTR_ADDR_LO,
0145            ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
0146
0147     if (rdev->wb.enabled)
0148         rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
0149
0150     WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
0151
0152     /* enable DMA IBs */
0153     ib_cntl = DMA_IB_ENABLE;
0154 #ifdef __BIG_ENDIAN
0155     ib_cntl |= DMA_IB_SWAP_ENABLE;
0156 #endif
0157     WREG32(DMA_IB_CNTL, ib_cntl);
0158
0159     dma_cntl = RREG32(DMA_CNTL);
0160     dma_cntl &= ~CTXEMPTY_INT_ENABLE;
0161     WREG32(DMA_CNTL, dma_cntl);
0162
0163     if (rdev->family >= CHIP_RV770)
0164         WREG32(DMA_MODE, 1);
0165
0166     ring->wptr = 0;
0167     WREG32(DMA_RB_WPTR, ring->wptr << 2);
0168
0169     WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
0170
0171     ring->ready = true;
0172
0173     r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
0174     if (r) {
0175         ring->ready = false;
0176         return r;
0177     }
0178
0179     if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
0180         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
0181
0182     return 0;
0183 }
0184
0185 /**
0186  * r600_dma_fini - tear down the async dma engine
0187  *
0188  * @rdev: radeon_device pointer
0189  *
0190  * Stop the async dma engine and free the ring (r6xx-evergreen).
0191  */
0192 void r600_dma_fini(struct radeon_device *rdev)
0193 {
0194     r600_dma_stop(rdev);
0195     radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
0196 }
0197
0198 /**
0199  * r600_dma_is_lockup - Check if the DMA engine is locked up
0200  *
0201  * @rdev: radeon_device pointer
0202  * @ring: radeon_ring structure holding ring information
0203  *
0204  * Check if the async DMA engine is locked up.
0205  * Returns true if the engine appears to be locked up, false if not.
0206  */
0207 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
0208 {
0209     u32 reset_mask = r600_gpu_check_soft_reset(rdev);
0210
0211     if (!(reset_mask & RADEON_RESET_DMA)) {
0212         radeon_ring_lockup_update(rdev, ring);
0213         return false;
0214     }
0215     return radeon_ring_test_lockup(rdev, ring);
0216 }
0217
0218
0219 /**
0220  * r600_dma_ring_test - simple async dma engine test
0221  *
0222  * @rdev: radeon_device pointer
0223  * @ring: radeon_ring structure holding ring information
0224  *
0225  * Test the DMA engine by writing using it to write an
0226  * value to memory. (r6xx-SI).
0227  * Returns 0 for success, error for failure.
0228  */
0229 int r600_dma_ring_test(struct radeon_device *rdev,
0230                struct radeon_ring *ring)
0231 {
0232     unsigned i;
0233     int r;
0234     unsigned index;
0235     u32 tmp;
0236     u64 gpu_addr;
0237
0238     if (ring->idx == R600_RING_TYPE_DMA_INDEX)
0239         index = R600_WB_DMA_RING_TEST_OFFSET;
0240     else
0241         index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
0242
0243     gpu_addr = rdev->wb.gpu_addr + index;
0244
0245     tmp = 0xCAFEDEAD;
0246     rdev->wb.wb[index/4] = cpu_to_le32(tmp);
0247
0248     r = radeon_ring_lock(rdev, ring, 4);
0249     if (r) {
0250         DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
0251         return r;
0252     }
0253     radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
0254     radeon_ring_write(ring, lower_32_bits(gpu_addr));
0255     radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);
0256     radeon_ring_write(ring, 0xDEADBEEF);
0257     radeon_ring_unlock_commit(rdev, ring, false);
0258
0259     for (i = 0; i < rdev->usec_timeout; i++) {
0260         tmp = le32_to_cpu(rdev->wb.wb[index/4]);
0261         if (tmp == 0xDEADBEEF)
0262             break;
0263         udelay(1);
0264     }
0265
0266     if (i < rdev->usec_timeout) {
0267         DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
0268     } else {
0269         DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
0270               ring->idx, tmp);
0271         r = -EINVAL;
0272     }
0273     return r;
0274 }
0275
0276 /**
0277  * r600_dma_fence_ring_emit - emit a fence on the DMA ring
0278  *
0279  * @rdev: radeon_device pointer
0280  * @fence: radeon fence object
0281  *
0282  * Add a DMA fence packet to the ring to write
0283  * the fence seq number and DMA trap packet to generate
0284  * an interrupt if needed (r6xx-r7xx).
0285  */
0286 void r600_dma_fence_ring_emit(struct radeon_device *rdev,
0287                   struct radeon_fence *fence)
0288 {
0289     struct radeon_ring *ring = &rdev->ring[fence->ring];
0290     u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
0291
0292     /* write the fence */
0293     radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
0294     radeon_ring_write(ring, addr & 0xfffffffc);
0295     radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
0296     radeon_ring_write(ring, lower_32_bits(fence->seq));
0297     /* generate an interrupt */
0298     radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
0299 }
0300
0301 /**
0302  * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
0303  *
0304  * @rdev: radeon_device pointer
0305  * @ring: radeon_ring structure holding ring information
0306  * @semaphore: radeon semaphore object
0307  * @emit_wait: wait or signal semaphore
0308  *
0309  * Add a DMA semaphore packet to the ring wait on or signal
0310  * other rings (r6xx-SI).
0311  */
0312 bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
0313                   struct radeon_ring *ring,
0314                   struct radeon_semaphore *semaphore,
0315                   bool emit_wait)
0316 {
0317     u64 addr = semaphore->gpu_addr;
0318     u32 s = emit_wait ? 0 : 1;
0319
0320     radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
0321     radeon_ring_write(ring, addr & 0xfffffffc);
0322     radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
0323
0324     return true;
0325 }
0326
0327 /**
0328  * r600_dma_ib_test - test an IB on the DMA engine
0329  *
0330  * @rdev: radeon_device pointer
0331  * @ring: radeon_ring structure holding ring information
0332  *
0333  * Test a simple IB in the DMA ring (r6xx-SI).
0334  * Returns 0 on success, error on failure.
0335  */
0336 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
0337 {
0338     struct radeon_ib ib;
0339     unsigned i;
0340     unsigned index;
0341     int r;
0342     u32 tmp = 0;
0343     u64 gpu_addr;
0344
0345     if (ring->idx == R600_RING_TYPE_DMA_INDEX)
0346         index = R600_WB_DMA_RING_TEST_OFFSET;
0347     else
0348         index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
0349
0350     gpu_addr = rdev->wb.gpu_addr + index;
0351
0352     r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
0353     if (r) {
0354         DRM_ERROR("radeon: failed to get ib (%d).\n", r);
0355         return r;
0356     }
0357
0358     ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
0359     ib.ptr[1] = lower_32_bits(gpu_addr);
0360     ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff;
0361     ib.ptr[3] = 0xDEADBEEF;
0362     ib.length_dw = 4;
0363
0364     r = radeon_ib_schedule(rdev, &ib, NULL, false);
0365     if (r) {
0366         radeon_ib_free(rdev, &ib);
0367         DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
0368         return r;
0369     }
0370     r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
0371         RADEON_USEC_IB_TEST_TIMEOUT));
0372     if (r < 0) {
0373         DRM_ERROR("radeon: fence wait failed (%d).\n", r);
0374         return r;
0375     } else if (r == 0) {
0376         DRM_ERROR("radeon: fence wait timed out.\n");
0377         return -ETIMEDOUT;
0378     }
0379     r = 0;
0380     for (i = 0; i < rdev->usec_timeout; i++) {
0381         tmp = le32_to_cpu(rdev->wb.wb[index/4]);
0382         if (tmp == 0xDEADBEEF)
0383             break;
0384         udelay(1);
0385     }
0386     if (i < rdev->usec_timeout) {
0387         DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
0388     } else {
0389         DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
0390         r = -EINVAL;
0391     }
0392     radeon_ib_free(rdev, &ib);
0393     return r;
0394 }
0395
0396 /**
0397  * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
0398  *
0399  * @rdev: radeon_device pointer
0400  * @ib: IB object to schedule
0401  *
0402  * Schedule an IB in the DMA ring (r6xx-r7xx).
0403  */
0404 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
0405 {
0406     struct radeon_ring *ring = &rdev->ring[ib->ring];
0407
0408     if (rdev->wb.enabled) {
0409         u32 next_rptr = ring->wptr + 4;
0410         while ((next_rptr & 7) != 5)
0411             next_rptr++;
0412         next_rptr += 3;
0413         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
0414         radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
0415         radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
0416         radeon_ring_write(ring, next_rptr);
0417     }
0418
0419     /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
0420      * Pad as necessary with NOPs.
0421      */
0422     while ((ring->wptr & 7) != 5)
0423         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
0424     radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
0425     radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
0426     radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
0427
0428 }
0429
0430 /**
0431  * r600_copy_dma - copy pages using the DMA engine
0432  *
0433  * @rdev: radeon_device pointer
0434  * @src_offset: src GPU address
0435  * @dst_offset: dst GPU address
0436  * @num_gpu_pages: number of GPU pages to xfer
0437  * @resv: reservation object to sync to
0438  *
0439  * Copy GPU paging using the DMA engine (r6xx).
0440  * Used by the radeon ttm implementation to move pages if
0441  * registered as the asic copy callback.
0442  */
0443 struct radeon_fence *r600_copy_dma(struct radeon_device *rdev,
0444                    uint64_t src_offset, uint64_t dst_offset,
0445                    unsigned num_gpu_pages,
0446                    struct dma_resv *resv)
0447 {
0448     struct radeon_fence *fence;
0449     struct radeon_sync sync;
0450     int ring_index = rdev->asic->copy.dma_ring_index;
0451     struct radeon_ring *ring = &rdev->ring[ring_index];
0452     u32 size_in_dw, cur_size_in_dw;
0453     int i, num_loops;
0454     int r = 0;
0455
0456     radeon_sync_create(&sync);
0457
0458     size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
0459     num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
0460     r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
0461     if (r) {
0462         DRM_ERROR("radeon: moving bo (%d).\n", r);
0463         radeon_sync_free(rdev, &sync, NULL);
0464         return ERR_PTR(r);
0465     }
0466
0467     radeon_sync_resv(rdev, &sync, resv, false);
0468     radeon_sync_rings(rdev, &sync, ring->idx);
0469
0470     for (i = 0; i < num_loops; i++) {
0471         cur_size_in_dw = size_in_dw;
0472         if (cur_size_in_dw > 0xFFFE)
0473             cur_size_in_dw = 0xFFFE;
0474         size_in_dw -= cur_size_in_dw;
0475         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
0476         radeon_ring_write(ring, dst_offset & 0xfffffffc);
0477         radeon_ring_write(ring, src_offset & 0xfffffffc);
0478         radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
0479                      (upper_32_bits(src_offset) & 0xff)));
0480         src_offset += cur_size_in_dw * 4;
0481         dst_offset += cur_size_in_dw * 4;
0482     }
0483
0484     r = radeon_fence_emit(rdev, &fence, ring->idx);
0485     if (r) {
0486         radeon_ring_unlock_undo(rdev, ring);
0487         radeon_sync_free(rdev, &sync, NULL);
0488         return ERR_PTR(r);
0489     }
0490
0491     radeon_ring_unlock_commit(rdev, ring, false);
0492     radeon_sync_free(rdev, &sync, fence);
0493
0494     return fence;
0495 }