drm/radeon/r520.c

0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028
0029 #include "radeon.h"
0030 #include "radeon_asic.h"
0031 #include "atom.h"
0032 #include "r520d.h"
0033
0034 /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */
0035
0036 int r520_mc_wait_for_idle(struct radeon_device *rdev)
0037 {
0038     unsigned i;
0039     uint32_t tmp;
0040
0041     for (i = 0; i < rdev->usec_timeout; i++) {
0042         /* read MC_STATUS */
0043         tmp = RREG32_MC(R520_MC_STATUS);
0044         if (tmp & R520_MC_STATUS_IDLE) {
0045             return 0;
0046         }
0047         udelay(1);
0048     }
0049     return -1;
0050 }
0051
0052 static void r520_gpu_init(struct radeon_device *rdev)
0053 {
0054     unsigned pipe_select_current, gb_pipe_select, tmp;
0055
0056     rv515_vga_render_disable(rdev);
0057     /*
0058      * DST_PIPE_CONFIG      0x170C
0059      * GB_TILE_CONFIG       0x4018
0060      * GB_FIFO_SIZE         0x4024
0061      * GB_PIPE_SELECT       0x402C
0062      * GB_PIPE_SELECT2              0x4124
0063      *  Z_PIPE_SHIFT            0
0064      *  Z_PIPE_MASK         0x000000003
0065      * GB_FIFO_SIZE2                0x4128
0066      *  SC_SFIFO_SIZE_SHIFT     0
0067      *  SC_SFIFO_SIZE_MASK      0x000000003
0068      *  SC_MFIFO_SIZE_SHIFT     2
0069      *  SC_MFIFO_SIZE_MASK      0x00000000C
0070      *  FG_SFIFO_SIZE_SHIFT     4
0071      *  FG_SFIFO_SIZE_MASK      0x000000030
0072      *  ZB_MFIFO_SIZE_SHIFT     6
0073      *  ZB_MFIFO_SIZE_MASK      0x0000000C0
0074      * GA_ENHANCE           0x4274
0075      * SU_REG_DEST          0x42C8
0076      */
0077     /* workaround for RV530 */
0078     if (rdev->family == CHIP_RV530) {
0079         WREG32(0x4128, 0xFF);
0080     }
0081     r420_pipes_init(rdev);
0082     gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
0083     tmp = RREG32(R300_DST_PIPE_CONFIG);
0084     pipe_select_current = (tmp >> 2) & 3;
0085     tmp = (1 << pipe_select_current) |
0086           (((gb_pipe_select >> 8) & 0xF) << 4);
0087     WREG32_PLL(0x000D, tmp);
0088     if (r520_mc_wait_for_idle(rdev)) {
0089         pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n");
0090     }
0091 }
0092
0093 static void r520_vram_get_type(struct radeon_device *rdev)
0094 {
0095     uint32_t tmp;
0096
0097     rdev->mc.vram_width = 128;
0098     rdev->mc.vram_is_ddr = true;
0099     tmp = RREG32_MC(R520_MC_CNTL0);
0100     switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
0101     case 0:
0102         rdev->mc.vram_width = 32;
0103         break;
0104     case 1:
0105         rdev->mc.vram_width = 64;
0106         break;
0107     case 2:
0108         rdev->mc.vram_width = 128;
0109         break;
0110     case 3:
0111         rdev->mc.vram_width = 256;
0112         break;
0113     default:
0114         rdev->mc.vram_width = 128;
0115         break;
0116     }
0117     if (tmp & R520_MC_CHANNEL_SIZE)
0118         rdev->mc.vram_width *= 2;
0119 }
0120
0121 static void r520_mc_init(struct radeon_device *rdev)
0122 {
0123
0124     r520_vram_get_type(rdev);
0125     r100_vram_init_sizes(rdev);
0126     radeon_vram_location(rdev, &rdev->mc, 0);
0127     rdev->mc.gtt_base_align = 0;
0128     if (!(rdev->flags & RADEON_IS_AGP))
0129         radeon_gtt_location(rdev, &rdev->mc);
0130     radeon_update_bandwidth_info(rdev);
0131 }
0132
0133 static void r520_mc_program(struct radeon_device *rdev)
0134 {
0135     struct rv515_mc_save save;
0136
0137     /* Stops all mc clients */
0138     rv515_mc_stop(rdev, &save);
0139
0140     /* Wait for mc idle */
0141     if (r520_mc_wait_for_idle(rdev))
0142         dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
0143     /* Write VRAM size in case we are limiting it */
0144     WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
0145     /* Program MC, should be a 32bits limited address space */
0146     WREG32_MC(R_000004_MC_FB_LOCATION,
0147             S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
0148             S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
0149     WREG32(R_000134_HDP_FB_LOCATION,
0150         S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
0151     if (rdev->flags & RADEON_IS_AGP) {
0152         WREG32_MC(R_000005_MC_AGP_LOCATION,
0153             S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
0154             S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
0155         WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
0156         WREG32_MC(R_000007_AGP_BASE_2,
0157             S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
0158     } else {
0159         WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
0160         WREG32_MC(R_000006_AGP_BASE, 0);
0161         WREG32_MC(R_000007_AGP_BASE_2, 0);
0162     }
0163
0164     rv515_mc_resume(rdev, &save);
0165 }
0166
0167 static int r520_startup(struct radeon_device *rdev)
0168 {
0169     int r;
0170
0171     r520_mc_program(rdev);
0172     /* Resume clock */
0173     rv515_clock_startup(rdev);
0174     /* Initialize GPU configuration (# pipes, ...) */
0175     r520_gpu_init(rdev);
0176     /* Initialize GART (initialize after TTM so we can allocate
0177      * memory through TTM but finalize after TTM) */
0178     if (rdev->flags & RADEON_IS_PCIE) {
0179         r = rv370_pcie_gart_enable(rdev);
0180         if (r)
0181             return r;
0182     }
0183
0184     /* allocate wb buffer */
0185     r = radeon_wb_init(rdev);
0186     if (r)
0187         return r;
0188
0189     r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
0190     if (r) {
0191         dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
0192         return r;
0193     }
0194
0195     /* Enable IRQ */
0196     if (!rdev->irq.installed) {
0197         r = radeon_irq_kms_init(rdev);
0198         if (r)
0199             return r;
0200     }
0201
0202     rs600_irq_set(rdev);
0203     rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
0204     /* 1M ring buffer */
0205     r = r100_cp_init(rdev, 1024 * 1024);
0206     if (r) {
0207         dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
0208         return r;
0209     }
0210
0211     r = radeon_ib_pool_init(rdev);
0212     if (r) {
0213         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
0214         return r;
0215     }
0216
0217     return 0;
0218 }
0219
0220 int r520_resume(struct radeon_device *rdev)
0221 {
0222     int r;
0223
0224     /* Make sur GART are not working */
0225     if (rdev->flags & RADEON_IS_PCIE)
0226         rv370_pcie_gart_disable(rdev);
0227     /* Resume clock before doing reset */
0228     rv515_clock_startup(rdev);
0229     /* Reset gpu before posting otherwise ATOM will enter infinite loop */
0230     if (radeon_asic_reset(rdev)) {
0231         dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
0232             RREG32(R_000E40_RBBM_STATUS),
0233             RREG32(R_0007C0_CP_STAT));
0234     }
0235     /* post */
0236     atom_asic_init(rdev->mode_info.atom_context);
0237     /* Resume clock after posting */
0238     rv515_clock_startup(rdev);
0239     /* Initialize surface registers */
0240     radeon_surface_init(rdev);
0241
0242     rdev->accel_working = true;
0243     r = r520_startup(rdev);
0244     if (r) {
0245         rdev->accel_working = false;
0246     }
0247     return r;
0248 }
0249
0250 int r520_init(struct radeon_device *rdev)
0251 {
0252     int r;
0253
0254     /* Initialize scratch registers */
0255     radeon_scratch_init(rdev);
0256     /* Initialize surface registers */
0257     radeon_surface_init(rdev);
0258     /* restore some register to sane defaults */
0259     r100_restore_sanity(rdev);
0260     /* TODO: disable VGA need to use VGA request */
0261     /* BIOS*/
0262     if (!radeon_get_bios(rdev)) {
0263         if (ASIC_IS_AVIVO(rdev))
0264             return -EINVAL;
0265     }
0266     if (rdev->is_atom_bios) {
0267         r = radeon_atombios_init(rdev);
0268         if (r)
0269             return r;
0270     } else {
0271         dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
0272         return -EINVAL;
0273     }
0274     /* Reset gpu before posting otherwise ATOM will enter infinite loop */
0275     if (radeon_asic_reset(rdev)) {
0276         dev_warn(rdev->dev,
0277             "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
0278             RREG32(R_000E40_RBBM_STATUS),
0279             RREG32(R_0007C0_CP_STAT));
0280     }
0281     /* check if cards are posted or not */
0282     if (radeon_boot_test_post_card(rdev) == false)
0283         return -EINVAL;
0284
0285     if (!radeon_card_posted(rdev) && rdev->bios) {
0286         DRM_INFO("GPU not posted. posting now...\n");
0287         atom_asic_init(rdev->mode_info.atom_context);
0288     }
0289     /* Initialize clocks */
0290     radeon_get_clock_info(rdev->ddev);
0291     /* initialize AGP */
0292     if (rdev->flags & RADEON_IS_AGP) {
0293         r = radeon_agp_init(rdev);
0294         if (r) {
0295             radeon_agp_disable(rdev);
0296         }
0297     }
0298     /* initialize memory controller */
0299     r520_mc_init(rdev);
0300     rv515_debugfs(rdev);
0301     /* Fence driver */
0302     radeon_fence_driver_init(rdev);
0303     /* Memory manager */
0304     r = radeon_bo_init(rdev);
0305     if (r)
0306         return r;
0307     r = rv370_pcie_gart_init(rdev);
0308     if (r)
0309         return r;
0310     rv515_set_safe_registers(rdev);
0311
0312     /* Initialize power management */
0313     radeon_pm_init(rdev);
0314
0315     rdev->accel_working = true;
0316     r = r520_startup(rdev);
0317     if (r) {
0318         /* Somethings want wront with the accel init stop accel */
0319         dev_err(rdev->dev, "Disabling GPU acceleration\n");
0320         r100_cp_fini(rdev);
0321         radeon_wb_fini(rdev);
0322         radeon_ib_pool_fini(rdev);
0323         radeon_irq_kms_fini(rdev);
0324         rv370_pcie_gart_fini(rdev);
0325         radeon_agp_fini(rdev);
0326         rdev->accel_working = false;
0327     }
0328     return 0;
0329 }