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0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028 
0029 #include <linux/pci.h>
0030 #include <linux/seq_file.h>
0031 #include <linux/slab.h>
0032 
0033 #include <drm/drm_device.h>
0034 #include <drm/drm_file.h>
0035 
0036 #include "atom.h"
0037 #include "r100d.h"
0038 #include "r420_reg_safe.h"
0039 #include "r420d.h"
0040 #include "radeon.h"
0041 #include "radeon_asic.h"
0042 #include "radeon_reg.h"
0043 
0044 void r420_pm_init_profile(struct radeon_device *rdev)
0045 {
0046     /* default */
0047     rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
0048     rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
0049     rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
0050     rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
0051     /* low sh */
0052     rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
0053     rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
0054     rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
0055     rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
0056     /* mid sh */
0057     rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
0058     rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
0059     rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
0060     rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
0061     /* high sh */
0062     rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
0063     rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
0064     rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
0065     rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
0066     /* low mh */
0067     rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
0068     rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
0069     rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
0070     rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
0071     /* mid mh */
0072     rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
0073     rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
0074     rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
0075     rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
0076     /* high mh */
0077     rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
0078     rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
0079     rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
0080     rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
0081 }
0082 
0083 static void r420_set_reg_safe(struct radeon_device *rdev)
0084 {
0085     rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
0086     rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
0087 }
0088 
0089 void r420_pipes_init(struct radeon_device *rdev)
0090 {
0091     unsigned tmp;
0092     unsigned gb_pipe_select;
0093     unsigned num_pipes;
0094 
0095     /* GA_ENHANCE workaround TCL deadlock issue */
0096     WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
0097            (1 << 2) | (1 << 3));
0098     /* add idle wait as per freedesktop.org bug 24041 */
0099     if (r100_gui_wait_for_idle(rdev)) {
0100         pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
0101     }
0102     /* get max number of pipes */
0103     gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
0104     num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
0105 
0106     /* SE chips have 1 pipe */
0107     if ((rdev->pdev->device == 0x5e4c) ||
0108         (rdev->pdev->device == 0x5e4f))
0109         num_pipes = 1;
0110 
0111     rdev->num_gb_pipes = num_pipes;
0112     tmp = 0;
0113     switch (num_pipes) {
0114     default:
0115         /* force to 1 pipe */
0116         num_pipes = 1;
0117         fallthrough;
0118     case 1:
0119         tmp = (0 << 1);
0120         break;
0121     case 2:
0122         tmp = (3 << 1);
0123         break;
0124     case 3:
0125         tmp = (6 << 1);
0126         break;
0127     case 4:
0128         tmp = (7 << 1);
0129         break;
0130     }
0131     WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
0132     /* Sub pixel 1/12 so we can have 4K rendering according to doc */
0133     tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
0134     WREG32(R300_GB_TILE_CONFIG, tmp);
0135     if (r100_gui_wait_for_idle(rdev)) {
0136         pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
0137     }
0138 
0139     tmp = RREG32(R300_DST_PIPE_CONFIG);
0140     WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
0141 
0142     WREG32(R300_RB2D_DSTCACHE_MODE,
0143            RREG32(R300_RB2D_DSTCACHE_MODE) |
0144            R300_DC_AUTOFLUSH_ENABLE |
0145            R300_DC_DC_DISABLE_IGNORE_PE);
0146 
0147     if (r100_gui_wait_for_idle(rdev)) {
0148         pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
0149     }
0150 
0151     if (rdev->family == CHIP_RV530) {
0152         tmp = RREG32(RV530_GB_PIPE_SELECT2);
0153         if ((tmp & 3) == 3)
0154             rdev->num_z_pipes = 2;
0155         else
0156             rdev->num_z_pipes = 1;
0157     } else
0158         rdev->num_z_pipes = 1;
0159 
0160     DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
0161          rdev->num_gb_pipes, rdev->num_z_pipes);
0162 }
0163 
0164 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
0165 {
0166     unsigned long flags;
0167     u32 r;
0168 
0169     spin_lock_irqsave(&rdev->mc_idx_lock, flags);
0170     WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
0171     r = RREG32(R_0001FC_MC_IND_DATA);
0172     spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
0173     return r;
0174 }
0175 
0176 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
0177 {
0178     unsigned long flags;
0179 
0180     spin_lock_irqsave(&rdev->mc_idx_lock, flags);
0181     WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
0182         S_0001F8_MC_IND_WR_EN(1));
0183     WREG32(R_0001FC_MC_IND_DATA, v);
0184     spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
0185 }
0186 
0187 static void r420_debugfs(struct radeon_device *rdev)
0188 {
0189     r100_debugfs_rbbm_init(rdev);
0190     r420_debugfs_pipes_info_init(rdev);
0191 }
0192 
0193 static void r420_clock_resume(struct radeon_device *rdev)
0194 {
0195     u32 sclk_cntl;
0196 
0197     if (radeon_dynclks != -1 && radeon_dynclks)
0198         radeon_atom_set_clock_gating(rdev, 1);
0199     sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
0200     sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
0201     if (rdev->family == CHIP_R420)
0202         sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
0203     WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
0204 }
0205 
0206 static void r420_cp_errata_init(struct radeon_device *rdev)
0207 {
0208     int r;
0209     struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
0210 
0211     /* RV410 and R420 can lock up if CP DMA to host memory happens
0212      * while the 2D engine is busy.
0213      *
0214      * The proper workaround is to queue a RESYNC at the beginning
0215      * of the CP init, apparently.
0216      */
0217     radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
0218     r = radeon_ring_lock(rdev, ring, 8);
0219     WARN_ON(r);
0220     radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
0221     radeon_ring_write(ring, rdev->config.r300.resync_scratch);
0222     radeon_ring_write(ring, 0xDEADBEEF);
0223     radeon_ring_unlock_commit(rdev, ring, false);
0224 }
0225 
0226 static void r420_cp_errata_fini(struct radeon_device *rdev)
0227 {
0228     int r;
0229     struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
0230 
0231     /* Catch the RESYNC we dispatched all the way back,
0232      * at the very beginning of the CP init.
0233      */
0234     r = radeon_ring_lock(rdev, ring, 8);
0235     WARN_ON(r);
0236     radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
0237     radeon_ring_write(ring, R300_RB3D_DC_FINISH);
0238     radeon_ring_unlock_commit(rdev, ring, false);
0239     radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
0240 }
0241 
0242 static int r420_startup(struct radeon_device *rdev)
0243 {
0244     int r;
0245 
0246     /* set common regs */
0247     r100_set_common_regs(rdev);
0248     /* program mc */
0249     r300_mc_program(rdev);
0250     /* Resume clock */
0251     r420_clock_resume(rdev);
0252     /* Initialize GART (initialize after TTM so we can allocate
0253      * memory through TTM but finalize after TTM) */
0254     if (rdev->flags & RADEON_IS_PCIE) {
0255         r = rv370_pcie_gart_enable(rdev);
0256         if (r)
0257             return r;
0258     }
0259     if (rdev->flags & RADEON_IS_PCI) {
0260         r = r100_pci_gart_enable(rdev);
0261         if (r)
0262             return r;
0263     }
0264     r420_pipes_init(rdev);
0265 
0266     /* allocate wb buffer */
0267     r = radeon_wb_init(rdev);
0268     if (r)
0269         return r;
0270 
0271     r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
0272     if (r) {
0273         dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
0274         return r;
0275     }
0276 
0277     /* Enable IRQ */
0278     if (!rdev->irq.installed) {
0279         r = radeon_irq_kms_init(rdev);
0280         if (r)
0281             return r;
0282     }
0283 
0284     r100_irq_set(rdev);
0285     rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
0286     /* 1M ring buffer */
0287     r = r100_cp_init(rdev, 1024 * 1024);
0288     if (r) {
0289         dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
0290         return r;
0291     }
0292     r420_cp_errata_init(rdev);
0293 
0294     r = radeon_ib_pool_init(rdev);
0295     if (r) {
0296         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
0297         return r;
0298     }
0299 
0300     return 0;
0301 }
0302 
0303 int r420_resume(struct radeon_device *rdev)
0304 {
0305     int r;
0306 
0307     /* Make sur GART are not working */
0308     if (rdev->flags & RADEON_IS_PCIE)
0309         rv370_pcie_gart_disable(rdev);
0310     if (rdev->flags & RADEON_IS_PCI)
0311         r100_pci_gart_disable(rdev);
0312     /* Resume clock before doing reset */
0313     r420_clock_resume(rdev);
0314     /* Reset gpu before posting otherwise ATOM will enter infinite loop */
0315     if (radeon_asic_reset(rdev)) {
0316         dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
0317             RREG32(R_000E40_RBBM_STATUS),
0318             RREG32(R_0007C0_CP_STAT));
0319     }
0320     /* check if cards are posted or not */
0321     if (rdev->is_atom_bios) {
0322         atom_asic_init(rdev->mode_info.atom_context);
0323     } else {
0324         radeon_combios_asic_init(rdev->ddev);
0325     }
0326     /* Resume clock after posting */
0327     r420_clock_resume(rdev);
0328     /* Initialize surface registers */
0329     radeon_surface_init(rdev);
0330 
0331     rdev->accel_working = true;
0332     r = r420_startup(rdev);
0333     if (r) {
0334         rdev->accel_working = false;
0335     }
0336     return r;
0337 }
0338 
0339 int r420_suspend(struct radeon_device *rdev)
0340 {
0341     radeon_pm_suspend(rdev);
0342     r420_cp_errata_fini(rdev);
0343     r100_cp_disable(rdev);
0344     radeon_wb_disable(rdev);
0345     r100_irq_disable(rdev);
0346     if (rdev->flags & RADEON_IS_PCIE)
0347         rv370_pcie_gart_disable(rdev);
0348     if (rdev->flags & RADEON_IS_PCI)
0349         r100_pci_gart_disable(rdev);
0350     return 0;
0351 }
0352 
0353 void r420_fini(struct radeon_device *rdev)
0354 {
0355     radeon_pm_fini(rdev);
0356     r100_cp_fini(rdev);
0357     radeon_wb_fini(rdev);
0358     radeon_ib_pool_fini(rdev);
0359     radeon_gem_fini(rdev);
0360     if (rdev->flags & RADEON_IS_PCIE)
0361         rv370_pcie_gart_fini(rdev);
0362     if (rdev->flags & RADEON_IS_PCI)
0363         r100_pci_gart_fini(rdev);
0364     radeon_agp_fini(rdev);
0365     radeon_irq_kms_fini(rdev);
0366     radeon_fence_driver_fini(rdev);
0367     radeon_bo_fini(rdev);
0368     if (rdev->is_atom_bios) {
0369         radeon_atombios_fini(rdev);
0370     } else {
0371         radeon_combios_fini(rdev);
0372     }
0373     kfree(rdev->bios);
0374     rdev->bios = NULL;
0375 }
0376 
0377 int r420_init(struct radeon_device *rdev)
0378 {
0379     int r;
0380 
0381     /* Initialize scratch registers */
0382     radeon_scratch_init(rdev);
0383     /* Initialize surface registers */
0384     radeon_surface_init(rdev);
0385     /* TODO: disable VGA need to use VGA request */
0386     /* restore some register to sane defaults */
0387     r100_restore_sanity(rdev);
0388     /* BIOS*/
0389     if (!radeon_get_bios(rdev)) {
0390         if (ASIC_IS_AVIVO(rdev))
0391             return -EINVAL;
0392     }
0393     if (rdev->is_atom_bios) {
0394         r = radeon_atombios_init(rdev);
0395         if (r) {
0396             return r;
0397         }
0398     } else {
0399         r = radeon_combios_init(rdev);
0400         if (r) {
0401             return r;
0402         }
0403     }
0404     /* Reset gpu before posting otherwise ATOM will enter infinite loop */
0405     if (radeon_asic_reset(rdev)) {
0406         dev_warn(rdev->dev,
0407             "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
0408             RREG32(R_000E40_RBBM_STATUS),
0409             RREG32(R_0007C0_CP_STAT));
0410     }
0411     /* check if cards are posted or not */
0412     if (radeon_boot_test_post_card(rdev) == false)
0413         return -EINVAL;
0414 
0415     /* Initialize clocks */
0416     radeon_get_clock_info(rdev->ddev);
0417     /* initialize AGP */
0418     if (rdev->flags & RADEON_IS_AGP) {
0419         r = radeon_agp_init(rdev);
0420         if (r) {
0421             radeon_agp_disable(rdev);
0422         }
0423     }
0424     /* initialize memory controller */
0425     r300_mc_init(rdev);
0426     r420_debugfs(rdev);
0427     /* Fence driver */
0428     radeon_fence_driver_init(rdev);
0429     /* Memory manager */
0430     r = radeon_bo_init(rdev);
0431     if (r) {
0432         return r;
0433     }
0434     if (rdev->family == CHIP_R420)
0435         r100_enable_bm(rdev);
0436 
0437     if (rdev->flags & RADEON_IS_PCIE) {
0438         r = rv370_pcie_gart_init(rdev);
0439         if (r)
0440             return r;
0441     }
0442     if (rdev->flags & RADEON_IS_PCI) {
0443         r = r100_pci_gart_init(rdev);
0444         if (r)
0445             return r;
0446     }
0447     r420_set_reg_safe(rdev);
0448 
0449     /* Initialize power management */
0450     radeon_pm_init(rdev);
0451 
0452     rdev->accel_working = true;
0453     r = r420_startup(rdev);
0454     if (r) {
0455         /* Somethings want wront with the accel init stop accel */
0456         dev_err(rdev->dev, "Disabling GPU acceleration\n");
0457         r100_cp_fini(rdev);
0458         radeon_wb_fini(rdev);
0459         radeon_ib_pool_fini(rdev);
0460         radeon_irq_kms_fini(rdev);
0461         if (rdev->flags & RADEON_IS_PCIE)
0462             rv370_pcie_gart_fini(rdev);
0463         if (rdev->flags & RADEON_IS_PCI)
0464             r100_pci_gart_fini(rdev);
0465         radeon_agp_fini(rdev);
0466         rdev->accel_working = false;
0467     }
0468     return 0;
0469 }
0470 
0471 /*
0472  * Debugfs info
0473  */
0474 #if defined(CONFIG_DEBUG_FS)
0475 static int r420_debugfs_pipes_info_show(struct seq_file *m, void *unused)
0476 {
0477     struct radeon_device *rdev = (struct radeon_device *)m->private;
0478     uint32_t tmp;
0479 
0480     tmp = RREG32(R400_GB_PIPE_SELECT);
0481     seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
0482     tmp = RREG32(R300_GB_TILE_CONFIG);
0483     seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
0484     tmp = RREG32(R300_DST_PIPE_CONFIG);
0485     seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
0486     return 0;
0487 }
0488 
0489 DEFINE_SHOW_ATTRIBUTE(r420_debugfs_pipes_info);
0490 #endif
0491 
0492 void r420_debugfs_pipes_info_init(struct radeon_device *rdev)
0493 {
0494 #if defined(CONFIG_DEBUG_FS)
0495     struct dentry *root = rdev->ddev->primary->debugfs_root;
0496 
0497     debugfs_create_file("r420_pipes_info", 0444, root, rdev,
0498                 &r420_debugfs_pipes_info_fops);
0499 #endif
0500 }
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