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0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028 
0029 #include <linux/pci.h>
0030 #include <linux/seq_file.h>
0031 #include <linux/slab.h>
0032 
0033 #include <drm/drm.h>
0034 #include <drm/drm_crtc_helper.h>
0035 #include <drm/drm_device.h>
0036 #include <drm/drm_file.h>
0037 #include <drm/radeon_drm.h>
0038 
0039 #include "r100_track.h"
0040 #include "r300_reg_safe.h"
0041 #include "r300d.h"
0042 #include "radeon.h"
0043 #include "radeon_asic.h"
0044 #include "radeon_reg.h"
0045 #include "rv350d.h"
0046 
0047 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
0048  *
0049  * GPU Errata:
0050  * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
0051  *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
0052  *   However, scheduling such write to the ring seems harmless, i suspect
0053  *   the CP read collide with the flush somehow, or maybe the MC, hard to
0054  *   tell. (Jerome Glisse)
0055  */
0056 
0057 /*
0058  * Indirect registers accessor
0059  */
0060 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
0061 {
0062     unsigned long flags;
0063     uint32_t r;
0064 
0065     spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
0066     WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
0067     r = RREG32(RADEON_PCIE_DATA);
0068     spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
0069     return r;
0070 }
0071 
0072 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
0073 {
0074     unsigned long flags;
0075 
0076     spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
0077     WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
0078     WREG32(RADEON_PCIE_DATA, (v));
0079     spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
0080 }
0081 
0082 /*
0083  * rv370,rv380 PCIE GART
0084  */
0085 static void rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
0086 
0087 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
0088 {
0089     uint32_t tmp;
0090     int i;
0091 
0092     /* Workaround HW bug do flush 2 times */
0093     for (i = 0; i < 2; i++) {
0094         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
0095         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
0096         (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
0097         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
0098     }
0099     mb();
0100 }
0101 
0102 #define R300_PTE_UNSNOOPED (1 << 0)
0103 #define R300_PTE_WRITEABLE (1 << 2)
0104 #define R300_PTE_READABLE  (1 << 3)
0105 
0106 uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags)
0107 {
0108     addr = (lower_32_bits(addr) >> 8) |
0109         ((upper_32_bits(addr) & 0xff) << 24);
0110     if (flags & RADEON_GART_PAGE_READ)
0111         addr |= R300_PTE_READABLE;
0112     if (flags & RADEON_GART_PAGE_WRITE)
0113         addr |= R300_PTE_WRITEABLE;
0114     if (!(flags & RADEON_GART_PAGE_SNOOP))
0115         addr |= R300_PTE_UNSNOOPED;
0116     return addr;
0117 }
0118 
0119 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
0120                   uint64_t entry)
0121 {
0122     void __iomem *ptr = rdev->gart.ptr;
0123 
0124     /* on x86 we want this to be CPU endian, on powerpc
0125      * on powerpc without HW swappers, it'll get swapped on way
0126      * into VRAM - so no need for cpu_to_le32 on VRAM tables */
0127     writel(entry, ((void __iomem *)ptr) + (i * 4));
0128 }
0129 
0130 int rv370_pcie_gart_init(struct radeon_device *rdev)
0131 {
0132     int r;
0133 
0134     if (rdev->gart.robj) {
0135         WARN(1, "RV370 PCIE GART already initialized\n");
0136         return 0;
0137     }
0138     /* Initialize common gart structure */
0139     r = radeon_gart_init(rdev);
0140     if (r)
0141         return r;
0142     rv370_debugfs_pcie_gart_info_init(rdev);
0143 
0144     rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
0145     rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
0146     rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
0147     rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
0148     return radeon_gart_table_vram_alloc(rdev);
0149 }
0150 
0151 int rv370_pcie_gart_enable(struct radeon_device *rdev)
0152 {
0153     uint32_t table_addr;
0154     uint32_t tmp;
0155     int r;
0156 
0157     if (rdev->gart.robj == NULL) {
0158         dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
0159         return -EINVAL;
0160     }
0161     r = radeon_gart_table_vram_pin(rdev);
0162     if (r)
0163         return r;
0164     /* discard memory request outside of configured range */
0165     tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
0166     WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
0167     WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
0168     tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
0169     WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
0170     WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
0171     WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
0172     table_addr = rdev->gart.table_addr;
0173     WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
0174     /* FIXME: setup default page */
0175     WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
0176     WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
0177     /* Clear error */
0178     WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
0179     tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
0180     tmp |= RADEON_PCIE_TX_GART_EN;
0181     tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
0182     WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
0183     rv370_pcie_gart_tlb_flush(rdev);
0184     DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
0185          (unsigned)(rdev->mc.gtt_size >> 20),
0186          (unsigned long long)table_addr);
0187     rdev->gart.ready = true;
0188     return 0;
0189 }
0190 
0191 void rv370_pcie_gart_disable(struct radeon_device *rdev)
0192 {
0193     u32 tmp;
0194 
0195     WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
0196     WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
0197     WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
0198     WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
0199     tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
0200     tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
0201     WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
0202     radeon_gart_table_vram_unpin(rdev);
0203 }
0204 
0205 void rv370_pcie_gart_fini(struct radeon_device *rdev)
0206 {
0207     radeon_gart_fini(rdev);
0208     rv370_pcie_gart_disable(rdev);
0209     radeon_gart_table_vram_free(rdev);
0210 }
0211 
0212 void r300_fence_ring_emit(struct radeon_device *rdev,
0213               struct radeon_fence *fence)
0214 {
0215     struct radeon_ring *ring = &rdev->ring[fence->ring];
0216 
0217     /* Who ever call radeon_fence_emit should call ring_lock and ask
0218      * for enough space (today caller are ib schedule and buffer move) */
0219     /* Write SC register so SC & US assert idle */
0220     radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
0221     radeon_ring_write(ring, 0);
0222     radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
0223     radeon_ring_write(ring, 0);
0224     /* Flush 3D cache */
0225     radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
0226     radeon_ring_write(ring, R300_RB3D_DC_FLUSH);
0227     radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
0228     radeon_ring_write(ring, R300_ZC_FLUSH);
0229     /* Wait until IDLE & CLEAN */
0230     radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
0231     radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN |
0232                  RADEON_WAIT_2D_IDLECLEAN |
0233                  RADEON_WAIT_DMA_GUI_IDLE));
0234     radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
0235     radeon_ring_write(ring, rdev->config.r300.hdp_cntl |
0236                 RADEON_HDP_READ_BUFFER_INVALIDATE);
0237     radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
0238     radeon_ring_write(ring, rdev->config.r300.hdp_cntl);
0239     /* Emit fence sequence & fire IRQ */
0240     radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
0241     radeon_ring_write(ring, fence->seq);
0242     radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
0243     radeon_ring_write(ring, RADEON_SW_INT_FIRE);
0244 }
0245 
0246 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
0247 {
0248     unsigned gb_tile_config;
0249     int r;
0250 
0251     /* Sub pixel 1/12 so we can have 4K rendering according to doc */
0252     gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
0253     switch(rdev->num_gb_pipes) {
0254     case 2:
0255         gb_tile_config |= R300_PIPE_COUNT_R300;
0256         break;
0257     case 3:
0258         gb_tile_config |= R300_PIPE_COUNT_R420_3P;
0259         break;
0260     case 4:
0261         gb_tile_config |= R300_PIPE_COUNT_R420;
0262         break;
0263     case 1:
0264     default:
0265         gb_tile_config |= R300_PIPE_COUNT_RV350;
0266         break;
0267     }
0268 
0269     r = radeon_ring_lock(rdev, ring, 64);
0270     if (r) {
0271         return;
0272     }
0273     radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
0274     radeon_ring_write(ring,
0275               RADEON_ISYNC_ANY2D_IDLE3D |
0276               RADEON_ISYNC_ANY3D_IDLE2D |
0277               RADEON_ISYNC_WAIT_IDLEGUI |
0278               RADEON_ISYNC_CPSCRATCH_IDLEGUI);
0279     radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));
0280     radeon_ring_write(ring, gb_tile_config);
0281     radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
0282     radeon_ring_write(ring,
0283               RADEON_WAIT_2D_IDLECLEAN |
0284               RADEON_WAIT_3D_IDLECLEAN);
0285     radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
0286     radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
0287     radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));
0288     radeon_ring_write(ring, 0);
0289     radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));
0290     radeon_ring_write(ring, 0);
0291     radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
0292     radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
0293     radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
0294     radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
0295     radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
0296     radeon_ring_write(ring,
0297               RADEON_WAIT_2D_IDLECLEAN |
0298               RADEON_WAIT_3D_IDLECLEAN);
0299     radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));
0300     radeon_ring_write(ring, 0);
0301     radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
0302     radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
0303     radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
0304     radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
0305     radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));
0306     radeon_ring_write(ring,
0307               ((6 << R300_MS_X0_SHIFT) |
0308                (6 << R300_MS_Y0_SHIFT) |
0309                (6 << R300_MS_X1_SHIFT) |
0310                (6 << R300_MS_Y1_SHIFT) |
0311                (6 << R300_MS_X2_SHIFT) |
0312                (6 << R300_MS_Y2_SHIFT) |
0313                (6 << R300_MSBD0_Y_SHIFT) |
0314                (6 << R300_MSBD0_X_SHIFT)));
0315     radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));
0316     radeon_ring_write(ring,
0317               ((6 << R300_MS_X3_SHIFT) |
0318                (6 << R300_MS_Y3_SHIFT) |
0319                (6 << R300_MS_X4_SHIFT) |
0320                (6 << R300_MS_Y4_SHIFT) |
0321                (6 << R300_MS_X5_SHIFT) |
0322                (6 << R300_MS_Y5_SHIFT) |
0323                (6 << R300_MSBD1_SHIFT)));
0324     radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));
0325     radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
0326     radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));
0327     radeon_ring_write(ring,
0328               R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
0329     radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));
0330     radeon_ring_write(ring,
0331               R300_GEOMETRY_ROUND_NEAREST |
0332               R300_COLOR_ROUND_NEAREST);
0333     radeon_ring_unlock_commit(rdev, ring, false);
0334 }
0335 
0336 static void r300_errata(struct radeon_device *rdev)
0337 {
0338     rdev->pll_errata = 0;
0339 
0340     if (rdev->family == CHIP_R300 &&
0341         (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
0342         rdev->pll_errata |= CHIP_ERRATA_R300_CG;
0343     }
0344 }
0345 
0346 int r300_mc_wait_for_idle(struct radeon_device *rdev)
0347 {
0348     unsigned i;
0349     uint32_t tmp;
0350 
0351     for (i = 0; i < rdev->usec_timeout; i++) {
0352         /* read MC_STATUS */
0353         tmp = RREG32(RADEON_MC_STATUS);
0354         if (tmp & R300_MC_IDLE) {
0355             return 0;
0356         }
0357         udelay(1);
0358     }
0359     return -1;
0360 }
0361 
0362 static void r300_gpu_init(struct radeon_device *rdev)
0363 {
0364     uint32_t gb_tile_config, tmp;
0365 
0366     if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
0367         (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
0368         /* r300,r350 */
0369         rdev->num_gb_pipes = 2;
0370     } else {
0371         /* rv350,rv370,rv380,r300 AD, r350 AH */
0372         rdev->num_gb_pipes = 1;
0373     }
0374     rdev->num_z_pipes = 1;
0375     gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
0376     switch (rdev->num_gb_pipes) {
0377     case 2:
0378         gb_tile_config |= R300_PIPE_COUNT_R300;
0379         break;
0380     case 3:
0381         gb_tile_config |= R300_PIPE_COUNT_R420_3P;
0382         break;
0383     case 4:
0384         gb_tile_config |= R300_PIPE_COUNT_R420;
0385         break;
0386     default:
0387     case 1:
0388         gb_tile_config |= R300_PIPE_COUNT_RV350;
0389         break;
0390     }
0391     WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
0392 
0393     if (r100_gui_wait_for_idle(rdev)) {
0394         pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
0395     }
0396 
0397     tmp = RREG32(R300_DST_PIPE_CONFIG);
0398     WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
0399 
0400     WREG32(R300_RB2D_DSTCACHE_MODE,
0401            R300_DC_AUTOFLUSH_ENABLE |
0402            R300_DC_DC_DISABLE_IGNORE_PE);
0403 
0404     if (r100_gui_wait_for_idle(rdev)) {
0405         pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
0406     }
0407     if (r300_mc_wait_for_idle(rdev)) {
0408         pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n");
0409     }
0410     DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized\n",
0411          rdev->num_gb_pipes, rdev->num_z_pipes);
0412 }
0413 
0414 int r300_asic_reset(struct radeon_device *rdev, bool hard)
0415 {
0416     struct r100_mc_save save;
0417     u32 status, tmp;
0418     int ret = 0;
0419 
0420     status = RREG32(R_000E40_RBBM_STATUS);
0421     if (!G_000E40_GUI_ACTIVE(status)) {
0422         return 0;
0423     }
0424     r100_mc_stop(rdev, &save);
0425     status = RREG32(R_000E40_RBBM_STATUS);
0426     dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
0427     /* stop CP */
0428     WREG32(RADEON_CP_CSQ_CNTL, 0);
0429     tmp = RREG32(RADEON_CP_RB_CNTL);
0430     WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
0431     WREG32(RADEON_CP_RB_RPTR_WR, 0);
0432     WREG32(RADEON_CP_RB_WPTR, 0);
0433     WREG32(RADEON_CP_RB_CNTL, tmp);
0434     /* save PCI state */
0435     pci_save_state(rdev->pdev);
0436     /* disable bus mastering */
0437     r100_bm_disable(rdev);
0438     WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
0439                     S_0000F0_SOFT_RESET_GA(1));
0440     RREG32(R_0000F0_RBBM_SOFT_RESET);
0441     mdelay(500);
0442     WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
0443     mdelay(1);
0444     status = RREG32(R_000E40_RBBM_STATUS);
0445     dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
0446     /* resetting the CP seems to be problematic sometimes it end up
0447      * hard locking the computer, but it's necessary for successful
0448      * reset more test & playing is needed on R3XX/R4XX to find a
0449      * reliable (if any solution)
0450      */
0451     WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
0452     RREG32(R_0000F0_RBBM_SOFT_RESET);
0453     mdelay(500);
0454     WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
0455     mdelay(1);
0456     status = RREG32(R_000E40_RBBM_STATUS);
0457     dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
0458     /* restore PCI & busmastering */
0459     pci_restore_state(rdev->pdev);
0460     r100_enable_bm(rdev);
0461     /* Check if GPU is idle */
0462     if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
0463         dev_err(rdev->dev, "failed to reset GPU\n");
0464         ret = -1;
0465     } else
0466         dev_info(rdev->dev, "GPU reset succeed\n");
0467     r100_mc_resume(rdev, &save);
0468     return ret;
0469 }
0470 
0471 /*
0472  * r300,r350,rv350,rv380 VRAM info
0473  */
0474 void r300_mc_init(struct radeon_device *rdev)
0475 {
0476     u64 base;
0477     u32 tmp;
0478 
0479     /* DDR for all card after R300 & IGP */
0480     rdev->mc.vram_is_ddr = true;
0481     tmp = RREG32(RADEON_MEM_CNTL);
0482     tmp &= R300_MEM_NUM_CHANNELS_MASK;
0483     switch (tmp) {
0484     case 0: rdev->mc.vram_width = 64; break;
0485     case 1: rdev->mc.vram_width = 128; break;
0486     case 2: rdev->mc.vram_width = 256; break;
0487     default:  rdev->mc.vram_width = 128; break;
0488     }
0489     r100_vram_init_sizes(rdev);
0490     base = rdev->mc.aper_base;
0491     if (rdev->flags & RADEON_IS_IGP)
0492         base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
0493     radeon_vram_location(rdev, &rdev->mc, base);
0494     rdev->mc.gtt_base_align = 0;
0495     if (!(rdev->flags & RADEON_IS_AGP))
0496         radeon_gtt_location(rdev, &rdev->mc);
0497     radeon_update_bandwidth_info(rdev);
0498 }
0499 
0500 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
0501 {
0502     uint32_t link_width_cntl, mask;
0503 
0504     if (rdev->flags & RADEON_IS_IGP)
0505         return;
0506 
0507     if (!(rdev->flags & RADEON_IS_PCIE))
0508         return;
0509 
0510     /* FIXME wait for idle */
0511 
0512     switch (lanes) {
0513     case 0:
0514         mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
0515         break;
0516     case 1:
0517         mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
0518         break;
0519     case 2:
0520         mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
0521         break;
0522     case 4:
0523         mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
0524         break;
0525     case 8:
0526         mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
0527         break;
0528     case 12:
0529         mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
0530         break;
0531     case 16:
0532     default:
0533         mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
0534         break;
0535     }
0536 
0537     link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
0538 
0539     if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
0540         (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
0541         return;
0542 
0543     link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
0544                  RADEON_PCIE_LC_RECONFIG_NOW |
0545                  RADEON_PCIE_LC_RECONFIG_LATER |
0546                  RADEON_PCIE_LC_SHORT_RECONFIG_EN);
0547     link_width_cntl |= mask;
0548     WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
0549     WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
0550                              RADEON_PCIE_LC_RECONFIG_NOW));
0551 
0552     /* wait for lane set to complete */
0553     link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
0554     while (link_width_cntl == 0xffffffff)
0555         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
0556 
0557 }
0558 
0559 int rv370_get_pcie_lanes(struct radeon_device *rdev)
0560 {
0561     u32 link_width_cntl;
0562 
0563     if (rdev->flags & RADEON_IS_IGP)
0564         return 0;
0565 
0566     if (!(rdev->flags & RADEON_IS_PCIE))
0567         return 0;
0568 
0569     /* FIXME wait for idle */
0570 
0571     link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
0572 
0573     switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
0574     case RADEON_PCIE_LC_LINK_WIDTH_X0:
0575         return 0;
0576     case RADEON_PCIE_LC_LINK_WIDTH_X1:
0577         return 1;
0578     case RADEON_PCIE_LC_LINK_WIDTH_X2:
0579         return 2;
0580     case RADEON_PCIE_LC_LINK_WIDTH_X4:
0581         return 4;
0582     case RADEON_PCIE_LC_LINK_WIDTH_X8:
0583         return 8;
0584     case RADEON_PCIE_LC_LINK_WIDTH_X16:
0585     default:
0586         return 16;
0587     }
0588 }
0589 
0590 #if defined(CONFIG_DEBUG_FS)
0591 static int rv370_debugfs_pcie_gart_info_show(struct seq_file *m, void *unused)
0592 {
0593     struct radeon_device *rdev = (struct radeon_device *)m->private;
0594     uint32_t tmp;
0595 
0596     tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
0597     seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
0598     tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
0599     seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
0600     tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
0601     seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
0602     tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
0603     seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
0604     tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
0605     seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
0606     tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
0607     seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
0608     tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
0609     seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
0610     return 0;
0611 }
0612 
0613 DEFINE_SHOW_ATTRIBUTE(rv370_debugfs_pcie_gart_info);
0614 #endif
0615 
0616 static void rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
0617 {
0618 #if defined(CONFIG_DEBUG_FS)
0619     struct dentry *root = rdev->ddev->primary->debugfs_root;
0620 
0621     debugfs_create_file("rv370_pcie_gart_info", 0444, root, rdev,
0622                 &rv370_debugfs_pcie_gart_info_fops);
0623 #endif
0624 }
0625 
0626 static int r300_packet0_check(struct radeon_cs_parser *p,
0627         struct radeon_cs_packet *pkt,
0628         unsigned idx, unsigned reg)
0629 {
0630     struct radeon_bo_list *reloc;
0631     struct r100_cs_track *track;
0632     volatile uint32_t *ib;
0633     uint32_t tmp, tile_flags = 0;
0634     unsigned i;
0635     int r;
0636     u32 idx_value;
0637 
0638     ib = p->ib.ptr;
0639     track = (struct r100_cs_track *)p->track;
0640     idx_value = radeon_get_ib_value(p, idx);
0641 
0642     switch(reg) {
0643     case AVIVO_D1MODE_VLINE_START_END:
0644     case RADEON_CRTC_GUI_TRIG_VLINE:
0645         r = r100_cs_packet_parse_vline(p);
0646         if (r) {
0647             DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
0648                     idx, reg);
0649             radeon_cs_dump_packet(p, pkt);
0650             return r;
0651         }
0652         break;
0653     case RADEON_DST_PITCH_OFFSET:
0654     case RADEON_SRC_PITCH_OFFSET:
0655         r = r100_reloc_pitch_offset(p, pkt, idx, reg);
0656         if (r)
0657             return r;
0658         break;
0659     case R300_RB3D_COLOROFFSET0:
0660     case R300_RB3D_COLOROFFSET1:
0661     case R300_RB3D_COLOROFFSET2:
0662     case R300_RB3D_COLOROFFSET3:
0663         i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
0664         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0665         if (r) {
0666             DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
0667                     idx, reg);
0668             radeon_cs_dump_packet(p, pkt);
0669             return r;
0670         }
0671         track->cb[i].robj = reloc->robj;
0672         track->cb[i].offset = idx_value;
0673         track->cb_dirty = true;
0674         ib[idx] = idx_value + ((u32)reloc->gpu_offset);
0675         break;
0676     case R300_ZB_DEPTHOFFSET:
0677         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0678         if (r) {
0679             DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
0680                     idx, reg);
0681             radeon_cs_dump_packet(p, pkt);
0682             return r;
0683         }
0684         track->zb.robj = reloc->robj;
0685         track->zb.offset = idx_value;
0686         track->zb_dirty = true;
0687         ib[idx] = idx_value + ((u32)reloc->gpu_offset);
0688         break;
0689     case R300_TX_OFFSET_0:
0690     case R300_TX_OFFSET_0+4:
0691     case R300_TX_OFFSET_0+8:
0692     case R300_TX_OFFSET_0+12:
0693     case R300_TX_OFFSET_0+16:
0694     case R300_TX_OFFSET_0+20:
0695     case R300_TX_OFFSET_0+24:
0696     case R300_TX_OFFSET_0+28:
0697     case R300_TX_OFFSET_0+32:
0698     case R300_TX_OFFSET_0+36:
0699     case R300_TX_OFFSET_0+40:
0700     case R300_TX_OFFSET_0+44:
0701     case R300_TX_OFFSET_0+48:
0702     case R300_TX_OFFSET_0+52:
0703     case R300_TX_OFFSET_0+56:
0704     case R300_TX_OFFSET_0+60:
0705         i = (reg - R300_TX_OFFSET_0) >> 2;
0706         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0707         if (r) {
0708             DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
0709                     idx, reg);
0710             radeon_cs_dump_packet(p, pkt);
0711             return r;
0712         }
0713 
0714         if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
0715             ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
0716                   ((idx_value & ~31) + (u32)reloc->gpu_offset);
0717         } else {
0718             if (reloc->tiling_flags & RADEON_TILING_MACRO)
0719                 tile_flags |= R300_TXO_MACRO_TILE;
0720             if (reloc->tiling_flags & RADEON_TILING_MICRO)
0721                 tile_flags |= R300_TXO_MICRO_TILE;
0722             else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
0723                 tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
0724 
0725             tmp = idx_value + ((u32)reloc->gpu_offset);
0726             tmp |= tile_flags;
0727             ib[idx] = tmp;
0728         }
0729         track->textures[i].robj = reloc->robj;
0730         track->tex_dirty = true;
0731         break;
0732     /* Tracked registers */
0733     case 0x2084:
0734         /* VAP_VF_CNTL */
0735         track->vap_vf_cntl = idx_value;
0736         break;
0737     case 0x20B4:
0738         /* VAP_VTX_SIZE */
0739         track->vtx_size = idx_value & 0x7F;
0740         break;
0741     case 0x2134:
0742         /* VAP_VF_MAX_VTX_INDX */
0743         track->max_indx = idx_value & 0x00FFFFFFUL;
0744         break;
0745     case 0x2088:
0746         /* VAP_ALT_NUM_VERTICES - only valid on r500 */
0747         if (p->rdev->family < CHIP_RV515)
0748             goto fail;
0749         track->vap_alt_nverts = idx_value & 0xFFFFFF;
0750         break;
0751     case 0x43E4:
0752         /* SC_SCISSOR1 */
0753         track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
0754         if (p->rdev->family < CHIP_RV515) {
0755             track->maxy -= 1440;
0756         }
0757         track->cb_dirty = true;
0758         track->zb_dirty = true;
0759         break;
0760     case 0x4E00:
0761         /* RB3D_CCTL */
0762         if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
0763             p->rdev->cmask_filp != p->filp) {
0764             DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
0765             return -EINVAL;
0766         }
0767         track->num_cb = ((idx_value >> 5) & 0x3) + 1;
0768         track->cb_dirty = true;
0769         break;
0770     case 0x4E38:
0771     case 0x4E3C:
0772     case 0x4E40:
0773     case 0x4E44:
0774         /* RB3D_COLORPITCH0 */
0775         /* RB3D_COLORPITCH1 */
0776         /* RB3D_COLORPITCH2 */
0777         /* RB3D_COLORPITCH3 */
0778         if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
0779             r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0780             if (r) {
0781                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
0782                       idx, reg);
0783                 radeon_cs_dump_packet(p, pkt);
0784                 return r;
0785             }
0786 
0787             if (reloc->tiling_flags & RADEON_TILING_MACRO)
0788                 tile_flags |= R300_COLOR_TILE_ENABLE;
0789             if (reloc->tiling_flags & RADEON_TILING_MICRO)
0790                 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
0791             else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
0792                 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
0793 
0794             tmp = idx_value & ~(0x7 << 16);
0795             tmp |= tile_flags;
0796             ib[idx] = tmp;
0797         }
0798         i = (reg - 0x4E38) >> 2;
0799         track->cb[i].pitch = idx_value & 0x3FFE;
0800         switch (((idx_value >> 21) & 0xF)) {
0801         case 9:
0802         case 11:
0803         case 12:
0804             track->cb[i].cpp = 1;
0805             break;
0806         case 3:
0807         case 4:
0808         case 13:
0809         case 15:
0810             track->cb[i].cpp = 2;
0811             break;
0812         case 5:
0813             if (p->rdev->family < CHIP_RV515) {
0814                 DRM_ERROR("Invalid color buffer format (%d)!\n",
0815                       ((idx_value >> 21) & 0xF));
0816                 return -EINVAL;
0817             }
0818             fallthrough;
0819         case 6:
0820             track->cb[i].cpp = 4;
0821             break;
0822         case 10:
0823             track->cb[i].cpp = 8;
0824             break;
0825         case 7:
0826             track->cb[i].cpp = 16;
0827             break;
0828         default:
0829             DRM_ERROR("Invalid color buffer format (%d) !\n",
0830                   ((idx_value >> 21) & 0xF));
0831             return -EINVAL;
0832         }
0833         track->cb_dirty = true;
0834         break;
0835     case 0x4F00:
0836         /* ZB_CNTL */
0837         if (idx_value & 2) {
0838             track->z_enabled = true;
0839         } else {
0840             track->z_enabled = false;
0841         }
0842         track->zb_dirty = true;
0843         break;
0844     case 0x4F10:
0845         /* ZB_FORMAT */
0846         switch ((idx_value & 0xF)) {
0847         case 0:
0848         case 1:
0849             track->zb.cpp = 2;
0850             break;
0851         case 2:
0852             track->zb.cpp = 4;
0853             break;
0854         default:
0855             DRM_ERROR("Invalid z buffer format (%d) !\n",
0856                   (idx_value & 0xF));
0857             return -EINVAL;
0858         }
0859         track->zb_dirty = true;
0860         break;
0861     case 0x4F24:
0862         /* ZB_DEPTHPITCH */
0863         if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
0864             r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0865             if (r) {
0866                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
0867                       idx, reg);
0868                 radeon_cs_dump_packet(p, pkt);
0869                 return r;
0870             }
0871 
0872             if (reloc->tiling_flags & RADEON_TILING_MACRO)
0873                 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
0874             if (reloc->tiling_flags & RADEON_TILING_MICRO)
0875                 tile_flags |= R300_DEPTHMICROTILE_TILED;
0876             else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
0877                 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
0878 
0879             tmp = idx_value & ~(0x7 << 16);
0880             tmp |= tile_flags;
0881             ib[idx] = tmp;
0882         }
0883         track->zb.pitch = idx_value & 0x3FFC;
0884         track->zb_dirty = true;
0885         break;
0886     case 0x4104:
0887         /* TX_ENABLE */
0888         for (i = 0; i < 16; i++) {
0889             bool enabled;
0890 
0891             enabled = !!(idx_value & (1 << i));
0892             track->textures[i].enabled = enabled;
0893         }
0894         track->tex_dirty = true;
0895         break;
0896     case 0x44C0:
0897     case 0x44C4:
0898     case 0x44C8:
0899     case 0x44CC:
0900     case 0x44D0:
0901     case 0x44D4:
0902     case 0x44D8:
0903     case 0x44DC:
0904     case 0x44E0:
0905     case 0x44E4:
0906     case 0x44E8:
0907     case 0x44EC:
0908     case 0x44F0:
0909     case 0x44F4:
0910     case 0x44F8:
0911     case 0x44FC:
0912         /* TX_FORMAT1_[0-15] */
0913         i = (reg - 0x44C0) >> 2;
0914         tmp = (idx_value >> 25) & 0x3;
0915         track->textures[i].tex_coord_type = tmp;
0916         switch ((idx_value & 0x1F)) {
0917         case R300_TX_FORMAT_X8:
0918         case R300_TX_FORMAT_Y4X4:
0919         case R300_TX_FORMAT_Z3Y3X2:
0920             track->textures[i].cpp = 1;
0921             track->textures[i].compress_format = R100_TRACK_COMP_NONE;
0922             break;
0923         case R300_TX_FORMAT_X16:
0924         case R300_TX_FORMAT_FL_I16:
0925         case R300_TX_FORMAT_Y8X8:
0926         case R300_TX_FORMAT_Z5Y6X5:
0927         case R300_TX_FORMAT_Z6Y5X5:
0928         case R300_TX_FORMAT_W4Z4Y4X4:
0929         case R300_TX_FORMAT_W1Z5Y5X5:
0930         case R300_TX_FORMAT_D3DMFT_CxV8U8:
0931         case R300_TX_FORMAT_B8G8_B8G8:
0932         case R300_TX_FORMAT_G8R8_G8B8:
0933             track->textures[i].cpp = 2;
0934             track->textures[i].compress_format = R100_TRACK_COMP_NONE;
0935             break;
0936         case R300_TX_FORMAT_Y16X16:
0937         case R300_TX_FORMAT_FL_I16A16:
0938         case R300_TX_FORMAT_Z11Y11X10:
0939         case R300_TX_FORMAT_Z10Y11X11:
0940         case R300_TX_FORMAT_W8Z8Y8X8:
0941         case R300_TX_FORMAT_W2Z10Y10X10:
0942         case 0x17:
0943         case R300_TX_FORMAT_FL_I32:
0944         case 0x1e:
0945             track->textures[i].cpp = 4;
0946             track->textures[i].compress_format = R100_TRACK_COMP_NONE;
0947             break;
0948         case R300_TX_FORMAT_W16Z16Y16X16:
0949         case R300_TX_FORMAT_FL_R16G16B16A16:
0950         case R300_TX_FORMAT_FL_I32A32:
0951             track->textures[i].cpp = 8;
0952             track->textures[i].compress_format = R100_TRACK_COMP_NONE;
0953             break;
0954         case R300_TX_FORMAT_FL_R32G32B32A32:
0955             track->textures[i].cpp = 16;
0956             track->textures[i].compress_format = R100_TRACK_COMP_NONE;
0957             break;
0958         case R300_TX_FORMAT_DXT1:
0959             track->textures[i].cpp = 1;
0960             track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
0961             break;
0962         case R300_TX_FORMAT_ATI2N:
0963             if (p->rdev->family < CHIP_R420) {
0964                 DRM_ERROR("Invalid texture format %u\n",
0965                       (idx_value & 0x1F));
0966                 return -EINVAL;
0967             }
0968             /* The same rules apply as for DXT3/5. */
0969             fallthrough;
0970         case R300_TX_FORMAT_DXT3:
0971         case R300_TX_FORMAT_DXT5:
0972             track->textures[i].cpp = 1;
0973             track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
0974             break;
0975         default:
0976             DRM_ERROR("Invalid texture format %u\n",
0977                   (idx_value & 0x1F));
0978             return -EINVAL;
0979         }
0980         track->tex_dirty = true;
0981         break;
0982     case 0x4400:
0983     case 0x4404:
0984     case 0x4408:
0985     case 0x440C:
0986     case 0x4410:
0987     case 0x4414:
0988     case 0x4418:
0989     case 0x441C:
0990     case 0x4420:
0991     case 0x4424:
0992     case 0x4428:
0993     case 0x442C:
0994     case 0x4430:
0995     case 0x4434:
0996     case 0x4438:
0997     case 0x443C:
0998         /* TX_FILTER0_[0-15] */
0999         i = (reg - 0x4400) >> 2;
1000         tmp = idx_value & 0x7;
1001         if (tmp == 2 || tmp == 4 || tmp == 6) {
1002             track->textures[i].roundup_w = false;
1003         }
1004         tmp = (idx_value >> 3) & 0x7;
1005         if (tmp == 2 || tmp == 4 || tmp == 6) {
1006             track->textures[i].roundup_h = false;
1007         }
1008         track->tex_dirty = true;
1009         break;
1010     case 0x4500:
1011     case 0x4504:
1012     case 0x4508:
1013     case 0x450C:
1014     case 0x4510:
1015     case 0x4514:
1016     case 0x4518:
1017     case 0x451C:
1018     case 0x4520:
1019     case 0x4524:
1020     case 0x4528:
1021     case 0x452C:
1022     case 0x4530:
1023     case 0x4534:
1024     case 0x4538:
1025     case 0x453C:
1026         /* TX_FORMAT2_[0-15] */
1027         i = (reg - 0x4500) >> 2;
1028         tmp = idx_value & 0x3FFF;
1029         track->textures[i].pitch = tmp + 1;
1030         if (p->rdev->family >= CHIP_RV515) {
1031             tmp = ((idx_value >> 15) & 1) << 11;
1032             track->textures[i].width_11 = tmp;
1033             tmp = ((idx_value >> 16) & 1) << 11;
1034             track->textures[i].height_11 = tmp;
1035 
1036             /* ATI1N */
1037             if (idx_value & (1 << 14)) {
1038                 /* The same rules apply as for DXT1. */
1039                 track->textures[i].compress_format =
1040                     R100_TRACK_COMP_DXT1;
1041             }
1042         } else if (idx_value & (1 << 14)) {
1043             DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1044             return -EINVAL;
1045         }
1046         track->tex_dirty = true;
1047         break;
1048     case 0x4480:
1049     case 0x4484:
1050     case 0x4488:
1051     case 0x448C:
1052     case 0x4490:
1053     case 0x4494:
1054     case 0x4498:
1055     case 0x449C:
1056     case 0x44A0:
1057     case 0x44A4:
1058     case 0x44A8:
1059     case 0x44AC:
1060     case 0x44B0:
1061     case 0x44B4:
1062     case 0x44B8:
1063     case 0x44BC:
1064         /* TX_FORMAT0_[0-15] */
1065         i = (reg - 0x4480) >> 2;
1066         tmp = idx_value & 0x7FF;
1067         track->textures[i].width = tmp + 1;
1068         tmp = (idx_value >> 11) & 0x7FF;
1069         track->textures[i].height = tmp + 1;
1070         tmp = (idx_value >> 26) & 0xF;
1071         track->textures[i].num_levels = tmp;
1072         tmp = idx_value & (1 << 31);
1073         track->textures[i].use_pitch = !!tmp;
1074         tmp = (idx_value >> 22) & 0xF;
1075         track->textures[i].txdepth = tmp;
1076         track->tex_dirty = true;
1077         break;
1078     case R300_ZB_ZPASS_ADDR:
1079         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1080         if (r) {
1081             DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1082                     idx, reg);
1083             radeon_cs_dump_packet(p, pkt);
1084             return r;
1085         }
1086         ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1087         break;
1088     case 0x4e0c:
1089         /* RB3D_COLOR_CHANNEL_MASK */
1090         track->color_channel_mask = idx_value;
1091         track->cb_dirty = true;
1092         break;
1093     case 0x43a4:
1094         /* SC_HYPERZ_EN */
1095         /* r300c emits this register - we need to disable hyperz for it
1096          * without complaining */
1097         if (p->rdev->hyperz_filp != p->filp) {
1098             if (idx_value & 0x1)
1099                 ib[idx] = idx_value & ~1;
1100         }
1101         break;
1102     case 0x4f1c:
1103         /* ZB_BW_CNTL */
1104         track->zb_cb_clear = !!(idx_value & (1 << 5));
1105         track->cb_dirty = true;
1106         track->zb_dirty = true;
1107         if (p->rdev->hyperz_filp != p->filp) {
1108             if (idx_value & (R300_HIZ_ENABLE |
1109                      R300_RD_COMP_ENABLE |
1110                      R300_WR_COMP_ENABLE |
1111                      R300_FAST_FILL_ENABLE))
1112                 goto fail;
1113         }
1114         break;
1115     case 0x4e04:
1116         /* RB3D_BLENDCNTL */
1117         track->blend_read_enable = !!(idx_value & (1 << 2));
1118         track->cb_dirty = true;
1119         break;
1120     case R300_RB3D_AARESOLVE_OFFSET:
1121         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1122         if (r) {
1123             DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1124                   idx, reg);
1125             radeon_cs_dump_packet(p, pkt);
1126             return r;
1127         }
1128         track->aa.robj = reloc->robj;
1129         track->aa.offset = idx_value;
1130         track->aa_dirty = true;
1131         ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1132         break;
1133     case R300_RB3D_AARESOLVE_PITCH:
1134         track->aa.pitch = idx_value & 0x3FFE;
1135         track->aa_dirty = true;
1136         break;
1137     case R300_RB3D_AARESOLVE_CTL:
1138         track->aaresolve = idx_value & 0x1;
1139         track->aa_dirty = true;
1140         break;
1141     case 0x4f30: /* ZB_MASK_OFFSET */
1142     case 0x4f34: /* ZB_ZMASK_PITCH */
1143     case 0x4f44: /* ZB_HIZ_OFFSET */
1144     case 0x4f54: /* ZB_HIZ_PITCH */
1145         if (idx_value && (p->rdev->hyperz_filp != p->filp))
1146             goto fail;
1147         break;
1148     case 0x4028:
1149         if (idx_value && (p->rdev->hyperz_filp != p->filp))
1150             goto fail;
1151         /* GB_Z_PEQ_CONFIG */
1152         if (p->rdev->family >= CHIP_RV350)
1153             break;
1154         goto fail;
1155         break;
1156     case 0x4be8:
1157         /* valid register only on RV530 */
1158         if (p->rdev->family == CHIP_RV530)
1159             break;
1160         fallthrough;
1161         /* fallthrough do not move */
1162     default:
1163         goto fail;
1164     }
1165     return 0;
1166 fail:
1167     pr_err("Forbidden register 0x%04X in cs at %d (val=%08x)\n",
1168            reg, idx, idx_value);
1169     return -EINVAL;
1170 }
1171 
1172 static int r300_packet3_check(struct radeon_cs_parser *p,
1173                   struct radeon_cs_packet *pkt)
1174 {
1175     struct radeon_bo_list *reloc;
1176     struct r100_cs_track *track;
1177     volatile uint32_t *ib;
1178     unsigned idx;
1179     int r;
1180 
1181     ib = p->ib.ptr;
1182     idx = pkt->idx + 1;
1183     track = (struct r100_cs_track *)p->track;
1184     switch(pkt->opcode) {
1185     case PACKET3_3D_LOAD_VBPNTR:
1186         r = r100_packet3_load_vbpntr(p, pkt, idx);
1187         if (r)
1188             return r;
1189         break;
1190     case PACKET3_INDX_BUFFER:
1191         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1192         if (r) {
1193             DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1194             radeon_cs_dump_packet(p, pkt);
1195             return r;
1196         }
1197         ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1198         r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1199         if (r) {
1200             return r;
1201         }
1202         break;
1203     /* Draw packet */
1204     case PACKET3_3D_DRAW_IMMD:
1205         /* Number of dwords is vtx_size * (num_vertices - 1)
1206          * PRIM_WALK must be equal to 3 vertex data in embedded
1207          * in cmd stream */
1208         if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1209             DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1210             return -EINVAL;
1211         }
1212         track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1213         track->immd_dwords = pkt->count - 1;
1214         r = r100_cs_track_check(p->rdev, track);
1215         if (r) {
1216             return r;
1217         }
1218         break;
1219     case PACKET3_3D_DRAW_IMMD_2:
1220         /* Number of dwords is vtx_size * (num_vertices - 1)
1221          * PRIM_WALK must be equal to 3 vertex data in embedded
1222          * in cmd stream */
1223         if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1224             DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1225             return -EINVAL;
1226         }
1227         track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1228         track->immd_dwords = pkt->count;
1229         r = r100_cs_track_check(p->rdev, track);
1230         if (r) {
1231             return r;
1232         }
1233         break;
1234     case PACKET3_3D_DRAW_VBUF:
1235         track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1236         r = r100_cs_track_check(p->rdev, track);
1237         if (r) {
1238             return r;
1239         }
1240         break;
1241     case PACKET3_3D_DRAW_VBUF_2:
1242         track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1243         r = r100_cs_track_check(p->rdev, track);
1244         if (r) {
1245             return r;
1246         }
1247         break;
1248     case PACKET3_3D_DRAW_INDX:
1249         track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1250         r = r100_cs_track_check(p->rdev, track);
1251         if (r) {
1252             return r;
1253         }
1254         break;
1255     case PACKET3_3D_DRAW_INDX_2:
1256         track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1257         r = r100_cs_track_check(p->rdev, track);
1258         if (r) {
1259             return r;
1260         }
1261         break;
1262     case PACKET3_3D_CLEAR_HIZ:
1263     case PACKET3_3D_CLEAR_ZMASK:
1264         if (p->rdev->hyperz_filp != p->filp)
1265             return -EINVAL;
1266         break;
1267     case PACKET3_3D_CLEAR_CMASK:
1268         if (p->rdev->cmask_filp != p->filp)
1269             return -EINVAL;
1270         break;
1271     case PACKET3_NOP:
1272         break;
1273     default:
1274         DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1275         return -EINVAL;
1276     }
1277     return 0;
1278 }
1279 
1280 int r300_cs_parse(struct radeon_cs_parser *p)
1281 {
1282     struct radeon_cs_packet pkt;
1283     struct r100_cs_track *track;
1284     int r;
1285 
1286     track = kzalloc(sizeof(*track), GFP_KERNEL);
1287     if (track == NULL)
1288         return -ENOMEM;
1289     r100_cs_track_clear(p->rdev, track);
1290     p->track = track;
1291     do {
1292         r = radeon_cs_packet_parse(p, &pkt, p->idx);
1293         if (r) {
1294             return r;
1295         }
1296         p->idx += pkt.count + 2;
1297         switch (pkt.type) {
1298         case RADEON_PACKET_TYPE0:
1299             r = r100_cs_parse_packet0(p, &pkt,
1300                           p->rdev->config.r300.reg_safe_bm,
1301                           p->rdev->config.r300.reg_safe_bm_size,
1302                           &r300_packet0_check);
1303             break;
1304         case RADEON_PACKET_TYPE2:
1305             break;
1306         case RADEON_PACKET_TYPE3:
1307             r = r300_packet3_check(p, &pkt);
1308             break;
1309         default:
1310             DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1311             return -EINVAL;
1312         }
1313         if (r) {
1314             return r;
1315         }
1316     } while (p->idx < p->chunk_ib->length_dw);
1317     return 0;
1318 }
1319 
1320 void r300_set_reg_safe(struct radeon_device *rdev)
1321 {
1322     rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1323     rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1324 }
1325 
1326 void r300_mc_program(struct radeon_device *rdev)
1327 {
1328     struct r100_mc_save save;
1329 
1330     r100_debugfs_mc_info_init(rdev);
1331 
1332     /* Stops all mc clients */
1333     r100_mc_stop(rdev, &save);
1334     if (rdev->flags & RADEON_IS_AGP) {
1335         WREG32(R_00014C_MC_AGP_LOCATION,
1336             S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1337             S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1338         WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1339         WREG32(R_00015C_AGP_BASE_2,
1340             upper_32_bits(rdev->mc.agp_base) & 0xff);
1341     } else {
1342         WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1343         WREG32(R_000170_AGP_BASE, 0);
1344         WREG32(R_00015C_AGP_BASE_2, 0);
1345     }
1346     /* Wait for mc idle */
1347     if (r300_mc_wait_for_idle(rdev))
1348         DRM_INFO("Failed to wait MC idle before programming MC.\n");
1349     /* Program MC, should be a 32bits limited address space */
1350     WREG32(R_000148_MC_FB_LOCATION,
1351         S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1352         S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1353     r100_mc_resume(rdev, &save);
1354 }
1355 
1356 void r300_clock_startup(struct radeon_device *rdev)
1357 {
1358     u32 tmp;
1359 
1360     if (radeon_dynclks != -1 && radeon_dynclks)
1361         radeon_legacy_set_clock_gating(rdev, 1);
1362     /* We need to force on some of the block */
1363     tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1364     tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1365     if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1366         tmp |= S_00000D_FORCE_VAP(1);
1367     WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1368 }
1369 
1370 static int r300_startup(struct radeon_device *rdev)
1371 {
1372     int r;
1373 
1374     /* set common regs */
1375     r100_set_common_regs(rdev);
1376     /* program mc */
1377     r300_mc_program(rdev);
1378     /* Resume clock */
1379     r300_clock_startup(rdev);
1380     /* Initialize GPU configuration (# pipes, ...) */
1381     r300_gpu_init(rdev);
1382     /* Initialize GART (initialize after TTM so we can allocate
1383      * memory through TTM but finalize after TTM) */
1384     if (rdev->flags & RADEON_IS_PCIE) {
1385         r = rv370_pcie_gart_enable(rdev);
1386         if (r)
1387             return r;
1388     }
1389 
1390     if (rdev->family == CHIP_R300 ||
1391         rdev->family == CHIP_R350 ||
1392         rdev->family == CHIP_RV350)
1393         r100_enable_bm(rdev);
1394 
1395     if (rdev->flags & RADEON_IS_PCI) {
1396         r = r100_pci_gart_enable(rdev);
1397         if (r)
1398             return r;
1399     }
1400 
1401     /* allocate wb buffer */
1402     r = radeon_wb_init(rdev);
1403     if (r)
1404         return r;
1405 
1406     r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1407     if (r) {
1408         dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1409         return r;
1410     }
1411 
1412     /* Enable IRQ */
1413     if (!rdev->irq.installed) {
1414         r = radeon_irq_kms_init(rdev);
1415         if (r)
1416             return r;
1417     }
1418 
1419     r100_irq_set(rdev);
1420     rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1421     /* 1M ring buffer */
1422     r = r100_cp_init(rdev, 1024 * 1024);
1423     if (r) {
1424         dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1425         return r;
1426     }
1427 
1428     r = radeon_ib_pool_init(rdev);
1429     if (r) {
1430         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1431         return r;
1432     }
1433 
1434     return 0;
1435 }
1436 
1437 int r300_resume(struct radeon_device *rdev)
1438 {
1439     int r;
1440 
1441     /* Make sur GART are not working */
1442     if (rdev->flags & RADEON_IS_PCIE)
1443         rv370_pcie_gart_disable(rdev);
1444     if (rdev->flags & RADEON_IS_PCI)
1445         r100_pci_gart_disable(rdev);
1446     /* Resume clock before doing reset */
1447     r300_clock_startup(rdev);
1448     /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1449     if (radeon_asic_reset(rdev)) {
1450         dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1451             RREG32(R_000E40_RBBM_STATUS),
1452             RREG32(R_0007C0_CP_STAT));
1453     }
1454     /* post */
1455     radeon_combios_asic_init(rdev->ddev);
1456     /* Resume clock after posting */
1457     r300_clock_startup(rdev);
1458     /* Initialize surface registers */
1459     radeon_surface_init(rdev);
1460 
1461     rdev->accel_working = true;
1462     r = r300_startup(rdev);
1463     if (r) {
1464         rdev->accel_working = false;
1465     }
1466     return r;
1467 }
1468 
1469 int r300_suspend(struct radeon_device *rdev)
1470 {
1471     radeon_pm_suspend(rdev);
1472     r100_cp_disable(rdev);
1473     radeon_wb_disable(rdev);
1474     r100_irq_disable(rdev);
1475     if (rdev->flags & RADEON_IS_PCIE)
1476         rv370_pcie_gart_disable(rdev);
1477     if (rdev->flags & RADEON_IS_PCI)
1478         r100_pci_gart_disable(rdev);
1479     return 0;
1480 }
1481 
1482 void r300_fini(struct radeon_device *rdev)
1483 {
1484     radeon_pm_fini(rdev);
1485     r100_cp_fini(rdev);
1486     radeon_wb_fini(rdev);
1487     radeon_ib_pool_fini(rdev);
1488     radeon_gem_fini(rdev);
1489     if (rdev->flags & RADEON_IS_PCIE)
1490         rv370_pcie_gart_fini(rdev);
1491     if (rdev->flags & RADEON_IS_PCI)
1492         r100_pci_gart_fini(rdev);
1493     radeon_agp_fini(rdev);
1494     radeon_irq_kms_fini(rdev);
1495     radeon_fence_driver_fini(rdev);
1496     radeon_bo_fini(rdev);
1497     radeon_atombios_fini(rdev);
1498     kfree(rdev->bios);
1499     rdev->bios = NULL;
1500 }
1501 
1502 int r300_init(struct radeon_device *rdev)
1503 {
1504     int r;
1505 
1506     /* Disable VGA */
1507     r100_vga_render_disable(rdev);
1508     /* Initialize scratch registers */
1509     radeon_scratch_init(rdev);
1510     /* Initialize surface registers */
1511     radeon_surface_init(rdev);
1512     /* TODO: disable VGA need to use VGA request */
1513     /* restore some register to sane defaults */
1514     r100_restore_sanity(rdev);
1515     /* BIOS*/
1516     if (!radeon_get_bios(rdev)) {
1517         if (ASIC_IS_AVIVO(rdev))
1518             return -EINVAL;
1519     }
1520     if (rdev->is_atom_bios) {
1521         dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1522         return -EINVAL;
1523     } else {
1524         r = radeon_combios_init(rdev);
1525         if (r)
1526             return r;
1527     }
1528     /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1529     if (radeon_asic_reset(rdev)) {
1530         dev_warn(rdev->dev,
1531             "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1532             RREG32(R_000E40_RBBM_STATUS),
1533             RREG32(R_0007C0_CP_STAT));
1534     }
1535     /* check if cards are posted or not */
1536     if (radeon_boot_test_post_card(rdev) == false)
1537         return -EINVAL;
1538     /* Set asic errata */
1539     r300_errata(rdev);
1540     /* Initialize clocks */
1541     radeon_get_clock_info(rdev->ddev);
1542     /* initialize AGP */
1543     if (rdev->flags & RADEON_IS_AGP) {
1544         r = radeon_agp_init(rdev);
1545         if (r) {
1546             radeon_agp_disable(rdev);
1547         }
1548     }
1549     /* initialize memory controller */
1550     r300_mc_init(rdev);
1551     /* Fence driver */
1552     radeon_fence_driver_init(rdev);
1553     /* Memory manager */
1554     r = radeon_bo_init(rdev);
1555     if (r)
1556         return r;
1557     if (rdev->flags & RADEON_IS_PCIE) {
1558         r = rv370_pcie_gart_init(rdev);
1559         if (r)
1560             return r;
1561     }
1562     if (rdev->flags & RADEON_IS_PCI) {
1563         r = r100_pci_gart_init(rdev);
1564         if (r)
1565             return r;
1566     }
1567     r300_set_reg_safe(rdev);
1568 
1569     /* Initialize power management */
1570     radeon_pm_init(rdev);
1571 
1572     rdev->accel_working = true;
1573     r = r300_startup(rdev);
1574     if (r) {
1575         /* Something went wrong with the accel init, so stop accel */
1576         dev_err(rdev->dev, "Disabling GPU acceleration\n");
1577         r100_cp_fini(rdev);
1578         radeon_wb_fini(rdev);
1579         radeon_ib_pool_fini(rdev);
1580         radeon_irq_kms_fini(rdev);
1581         if (rdev->flags & RADEON_IS_PCIE)
1582             rv370_pcie_gart_fini(rdev);
1583         if (rdev->flags & RADEON_IS_PCI)
1584             r100_pci_gart_fini(rdev);
1585         radeon_agp_fini(rdev);
1586         rdev->accel_working = false;
1587     }
1588     return 0;
1589 }
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