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0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028 #ifndef __R100D_H__
0029 #define __R100D_H__
0030 
0031 #define CP_PACKET0          0x00000000
0032 #define     PACKET0_BASE_INDEX_SHIFT    0
0033 #define     PACKET0_BASE_INDEX_MASK     (0x1ffff << 0)
0034 #define     PACKET0_COUNT_SHIFT     16
0035 #define     PACKET0_COUNT_MASK      (0x3fff << 16)
0036 #define CP_PACKET1          0x40000000
0037 #define CP_PACKET2          0x80000000
0038 #define     PACKET2_PAD_SHIFT       0
0039 #define     PACKET2_PAD_MASK        (0x3fffffff << 0)
0040 #define CP_PACKET3          0xC0000000
0041 #define     PACKET3_IT_OPCODE_SHIFT     8
0042 #define     PACKET3_IT_OPCODE_MASK      (0xff << 8)
0043 #define     PACKET3_COUNT_SHIFT     16
0044 #define     PACKET3_COUNT_MASK      (0x3fff << 16)
0045 /* PACKET3 op code */
0046 #define     PACKET3_NOP         0x10
0047 #define     PACKET3_3D_DRAW_VBUF        0x28
0048 #define     PACKET3_3D_DRAW_IMMD        0x29
0049 #define     PACKET3_3D_DRAW_INDX        0x2A
0050 #define     PACKET3_3D_LOAD_VBPNTR      0x2F
0051 #define     PACKET3_3D_CLEAR_ZMASK      0x32
0052 #define     PACKET3_INDX_BUFFER     0x33
0053 #define     PACKET3_3D_DRAW_VBUF_2      0x34
0054 #define     PACKET3_3D_DRAW_IMMD_2      0x35
0055 #define     PACKET3_3D_DRAW_INDX_2      0x36
0056 #define     PACKET3_3D_CLEAR_HIZ        0x37
0057 #define     PACKET3_BITBLT_MULTI        0x9B
0058 
0059 #define PACKET0(reg, n) (CP_PACKET0 |                   \
0060              REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) |  \
0061              REG_SET(PACKET0_COUNT, (n)))
0062 #define PACKET2(v)  (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
0063 #define PACKET3(op, n)  (CP_PACKET3 |                   \
0064              REG_SET(PACKET3_IT_OPCODE, (op)) |     \
0065              REG_SET(PACKET3_COUNT, (n)))
0066 
0067 /* Registers */
0068 #define R_0000F0_RBBM_SOFT_RESET                     0x0000F0
0069 #define   S_0000F0_SOFT_RESET_CP(x)                    (((x) & 0x1) << 0)
0070 #define   G_0000F0_SOFT_RESET_CP(x)                    (((x) >> 0) & 0x1)
0071 #define   C_0000F0_SOFT_RESET_CP                       0xFFFFFFFE
0072 #define   S_0000F0_SOFT_RESET_HI(x)                    (((x) & 0x1) << 1)
0073 #define   G_0000F0_SOFT_RESET_HI(x)                    (((x) >> 1) & 0x1)
0074 #define   C_0000F0_SOFT_RESET_HI                       0xFFFFFFFD
0075 #define   S_0000F0_SOFT_RESET_SE(x)                    (((x) & 0x1) << 2)
0076 #define   G_0000F0_SOFT_RESET_SE(x)                    (((x) >> 2) & 0x1)
0077 #define   C_0000F0_SOFT_RESET_SE                       0xFFFFFFFB
0078 #define   S_0000F0_SOFT_RESET_RE(x)                    (((x) & 0x1) << 3)
0079 #define   G_0000F0_SOFT_RESET_RE(x)                    (((x) >> 3) & 0x1)
0080 #define   C_0000F0_SOFT_RESET_RE                       0xFFFFFFF7
0081 #define   S_0000F0_SOFT_RESET_PP(x)                    (((x) & 0x1) << 4)
0082 #define   G_0000F0_SOFT_RESET_PP(x)                    (((x) >> 4) & 0x1)
0083 #define   C_0000F0_SOFT_RESET_PP                       0xFFFFFFEF
0084 #define   S_0000F0_SOFT_RESET_E2(x)                    (((x) & 0x1) << 5)
0085 #define   G_0000F0_SOFT_RESET_E2(x)                    (((x) >> 5) & 0x1)
0086 #define   C_0000F0_SOFT_RESET_E2                       0xFFFFFFDF
0087 #define   S_0000F0_SOFT_RESET_RB(x)                    (((x) & 0x1) << 6)
0088 #define   G_0000F0_SOFT_RESET_RB(x)                    (((x) >> 6) & 0x1)
0089 #define   C_0000F0_SOFT_RESET_RB                       0xFFFFFFBF
0090 #define   S_0000F0_SOFT_RESET_HDP(x)                   (((x) & 0x1) << 7)
0091 #define   G_0000F0_SOFT_RESET_HDP(x)                   (((x) >> 7) & 0x1)
0092 #define   C_0000F0_SOFT_RESET_HDP                      0xFFFFFF7F
0093 #define   S_0000F0_SOFT_RESET_MC(x)                    (((x) & 0x1) << 8)
0094 #define   G_0000F0_SOFT_RESET_MC(x)                    (((x) >> 8) & 0x1)
0095 #define   C_0000F0_SOFT_RESET_MC                       0xFFFFFEFF
0096 #define   S_0000F0_SOFT_RESET_AIC(x)                   (((x) & 0x1) << 9)
0097 #define   G_0000F0_SOFT_RESET_AIC(x)                   (((x) >> 9) & 0x1)
0098 #define   C_0000F0_SOFT_RESET_AIC                      0xFFFFFDFF
0099 #define   S_0000F0_SOFT_RESET_VIP(x)                   (((x) & 0x1) << 10)
0100 #define   G_0000F0_SOFT_RESET_VIP(x)                   (((x) >> 10) & 0x1)
0101 #define   C_0000F0_SOFT_RESET_VIP                      0xFFFFFBFF
0102 #define   S_0000F0_SOFT_RESET_DISP(x)                  (((x) & 0x1) << 11)
0103 #define   G_0000F0_SOFT_RESET_DISP(x)                  (((x) >> 11) & 0x1)
0104 #define   C_0000F0_SOFT_RESET_DISP                     0xFFFFF7FF
0105 #define   S_0000F0_SOFT_RESET_CG(x)                    (((x) & 0x1) << 12)
0106 #define   G_0000F0_SOFT_RESET_CG(x)                    (((x) >> 12) & 0x1)
0107 #define   C_0000F0_SOFT_RESET_CG                       0xFFFFEFFF
0108 #define R_000030_BUS_CNTL                            0x000030
0109 #define   S_000030_BUS_DBL_RESYNC(x)                   (((x) & 0x1) << 0)
0110 #define   G_000030_BUS_DBL_RESYNC(x)                   (((x) >> 0) & 0x1)
0111 #define   C_000030_BUS_DBL_RESYNC                      0xFFFFFFFE
0112 #define   S_000030_BUS_MSTR_RESET(x)                   (((x) & 0x1) << 1)
0113 #define   G_000030_BUS_MSTR_RESET(x)                   (((x) >> 1) & 0x1)
0114 #define   C_000030_BUS_MSTR_RESET                      0xFFFFFFFD
0115 #define   S_000030_BUS_FLUSH_BUF(x)                    (((x) & 0x1) << 2)
0116 #define   G_000030_BUS_FLUSH_BUF(x)                    (((x) >> 2) & 0x1)
0117 #define   C_000030_BUS_FLUSH_BUF                       0xFFFFFFFB
0118 #define   S_000030_BUS_STOP_REQ_DIS(x)                 (((x) & 0x1) << 3)
0119 #define   G_000030_BUS_STOP_REQ_DIS(x)                 (((x) >> 3) & 0x1)
0120 #define   C_000030_BUS_STOP_REQ_DIS                    0xFFFFFFF7
0121 #define   S_000030_BUS_PM4_READ_COMBINE_EN(x)          (((x) & 0x1) << 4)
0122 #define   G_000030_BUS_PM4_READ_COMBINE_EN(x)          (((x) >> 4) & 0x1)
0123 #define   C_000030_BUS_PM4_READ_COMBINE_EN             0xFFFFFFEF
0124 #define   S_000030_BUS_WRT_COMBINE_EN(x)               (((x) & 0x1) << 5)
0125 #define   G_000030_BUS_WRT_COMBINE_EN(x)               (((x) >> 5) & 0x1)
0126 #define   C_000030_BUS_WRT_COMBINE_EN                  0xFFFFFFDF
0127 #define   S_000030_BUS_MASTER_DIS(x)                   (((x) & 0x1) << 6)
0128 #define   G_000030_BUS_MASTER_DIS(x)                   (((x) >> 6) & 0x1)
0129 #define   C_000030_BUS_MASTER_DIS                      0xFFFFFFBF
0130 #define   S_000030_BIOS_ROM_WRT_EN(x)                  (((x) & 0x1) << 7)
0131 #define   G_000030_BIOS_ROM_WRT_EN(x)                  (((x) >> 7) & 0x1)
0132 #define   C_000030_BIOS_ROM_WRT_EN                     0xFFFFFF7F
0133 #define   S_000030_BM_DAC_CRIPPLE(x)                   (((x) & 0x1) << 8)
0134 #define   G_000030_BM_DAC_CRIPPLE(x)                   (((x) >> 8) & 0x1)
0135 #define   C_000030_BM_DAC_CRIPPLE                      0xFFFFFEFF
0136 #define   S_000030_BUS_NON_PM4_READ_COMBINE_EN(x)      (((x) & 0x1) << 9)
0137 #define   G_000030_BUS_NON_PM4_READ_COMBINE_EN(x)      (((x) >> 9) & 0x1)
0138 #define   C_000030_BUS_NON_PM4_READ_COMBINE_EN         0xFFFFFDFF
0139 #define   S_000030_BUS_XFERD_DISCARD_EN(x)             (((x) & 0x1) << 10)
0140 #define   G_000030_BUS_XFERD_DISCARD_EN(x)             (((x) >> 10) & 0x1)
0141 #define   C_000030_BUS_XFERD_DISCARD_EN                0xFFFFFBFF
0142 #define   S_000030_BUS_SGL_READ_DISABLE(x)             (((x) & 0x1) << 11)
0143 #define   G_000030_BUS_SGL_READ_DISABLE(x)             (((x) >> 11) & 0x1)
0144 #define   C_000030_BUS_SGL_READ_DISABLE                0xFFFFF7FF
0145 #define   S_000030_BIOS_DIS_ROM(x)                     (((x) & 0x1) << 12)
0146 #define   G_000030_BIOS_DIS_ROM(x)                     (((x) >> 12) & 0x1)
0147 #define   C_000030_BIOS_DIS_ROM                        0xFFFFEFFF
0148 #define   S_000030_BUS_PCI_READ_RETRY_EN(x)            (((x) & 0x1) << 13)
0149 #define   G_000030_BUS_PCI_READ_RETRY_EN(x)            (((x) >> 13) & 0x1)
0150 #define   C_000030_BUS_PCI_READ_RETRY_EN               0xFFFFDFFF
0151 #define   S_000030_BUS_AGP_AD_STEPPING_EN(x)           (((x) & 0x1) << 14)
0152 #define   G_000030_BUS_AGP_AD_STEPPING_EN(x)           (((x) >> 14) & 0x1)
0153 #define   C_000030_BUS_AGP_AD_STEPPING_EN              0xFFFFBFFF
0154 #define   S_000030_BUS_PCI_WRT_RETRY_EN(x)             (((x) & 0x1) << 15)
0155 #define   G_000030_BUS_PCI_WRT_RETRY_EN(x)             (((x) >> 15) & 0x1)
0156 #define   C_000030_BUS_PCI_WRT_RETRY_EN                0xFFFF7FFF
0157 #define   S_000030_BUS_RETRY_WS(x)                     (((x) & 0xF) << 16)
0158 #define   G_000030_BUS_RETRY_WS(x)                     (((x) >> 16) & 0xF)
0159 #define   C_000030_BUS_RETRY_WS                        0xFFF0FFFF
0160 #define   S_000030_BUS_MSTR_RD_MULT(x)                 (((x) & 0x1) << 20)
0161 #define   G_000030_BUS_MSTR_RD_MULT(x)                 (((x) >> 20) & 0x1)
0162 #define   C_000030_BUS_MSTR_RD_MULT                    0xFFEFFFFF
0163 #define   S_000030_BUS_MSTR_RD_LINE(x)                 (((x) & 0x1) << 21)
0164 #define   G_000030_BUS_MSTR_RD_LINE(x)                 (((x) >> 21) & 0x1)
0165 #define   C_000030_BUS_MSTR_RD_LINE                    0xFFDFFFFF
0166 #define   S_000030_BUS_SUSPEND(x)                      (((x) & 0x1) << 22)
0167 #define   G_000030_BUS_SUSPEND(x)                      (((x) >> 22) & 0x1)
0168 #define   C_000030_BUS_SUSPEND                         0xFFBFFFFF
0169 #define   S_000030_LAT_16X(x)                          (((x) & 0x1) << 23)
0170 #define   G_000030_LAT_16X(x)                          (((x) >> 23) & 0x1)
0171 #define   C_000030_LAT_16X                             0xFF7FFFFF
0172 #define   S_000030_BUS_RD_DISCARD_EN(x)                (((x) & 0x1) << 24)
0173 #define   G_000030_BUS_RD_DISCARD_EN(x)                (((x) >> 24) & 0x1)
0174 #define   C_000030_BUS_RD_DISCARD_EN                   0xFEFFFFFF
0175 #define   S_000030_ENFRCWRDY(x)                        (((x) & 0x1) << 25)
0176 #define   G_000030_ENFRCWRDY(x)                        (((x) >> 25) & 0x1)
0177 #define   C_000030_ENFRCWRDY                           0xFDFFFFFF
0178 #define   S_000030_BUS_MSTR_WS(x)                      (((x) & 0x1) << 26)
0179 #define   G_000030_BUS_MSTR_WS(x)                      (((x) >> 26) & 0x1)
0180 #define   C_000030_BUS_MSTR_WS                         0xFBFFFFFF
0181 #define   S_000030_BUS_PARKING_DIS(x)                  (((x) & 0x1) << 27)
0182 #define   G_000030_BUS_PARKING_DIS(x)                  (((x) >> 27) & 0x1)
0183 #define   C_000030_BUS_PARKING_DIS                     0xF7FFFFFF
0184 #define   S_000030_BUS_MSTR_DISCONNECT_EN(x)           (((x) & 0x1) << 28)
0185 #define   G_000030_BUS_MSTR_DISCONNECT_EN(x)           (((x) >> 28) & 0x1)
0186 #define   C_000030_BUS_MSTR_DISCONNECT_EN              0xEFFFFFFF
0187 #define   S_000030_SERR_EN(x)                          (((x) & 0x1) << 29)
0188 #define   G_000030_SERR_EN(x)                          (((x) >> 29) & 0x1)
0189 #define   C_000030_SERR_EN                             0xDFFFFFFF
0190 #define   S_000030_BUS_READ_BURST(x)                   (((x) & 0x1) << 30)
0191 #define   G_000030_BUS_READ_BURST(x)                   (((x) >> 30) & 0x1)
0192 #define   C_000030_BUS_READ_BURST                      0xBFFFFFFF
0193 #define   S_000030_BUS_RDY_READ_DLY(x)                 (((x) & 0x1) << 31)
0194 #define   G_000030_BUS_RDY_READ_DLY(x)                 (((x) >> 31) & 0x1)
0195 #define   C_000030_BUS_RDY_READ_DLY                    0x7FFFFFFF
0196 #define R_000040_GEN_INT_CNTL                        0x000040
0197 #define   S_000040_CRTC_VBLANK(x)                      (((x) & 0x1) << 0)
0198 #define   G_000040_CRTC_VBLANK(x)                      (((x) >> 0) & 0x1)
0199 #define   C_000040_CRTC_VBLANK                         0xFFFFFFFE
0200 #define   S_000040_CRTC_VLINE(x)                       (((x) & 0x1) << 1)
0201 #define   G_000040_CRTC_VLINE(x)                       (((x) >> 1) & 0x1)
0202 #define   C_000040_CRTC_VLINE                          0xFFFFFFFD
0203 #define   S_000040_CRTC_VSYNC(x)                       (((x) & 0x1) << 2)
0204 #define   G_000040_CRTC_VSYNC(x)                       (((x) >> 2) & 0x1)
0205 #define   C_000040_CRTC_VSYNC                          0xFFFFFFFB
0206 #define   S_000040_SNAPSHOT(x)                         (((x) & 0x1) << 3)
0207 #define   G_000040_SNAPSHOT(x)                         (((x) >> 3) & 0x1)
0208 #define   C_000040_SNAPSHOT                            0xFFFFFFF7
0209 #define   S_000040_FP_DETECT(x)                        (((x) & 0x1) << 4)
0210 #define   G_000040_FP_DETECT(x)                        (((x) >> 4) & 0x1)
0211 #define   C_000040_FP_DETECT                           0xFFFFFFEF
0212 #define   S_000040_CRTC2_VLINE(x)                      (((x) & 0x1) << 5)
0213 #define   G_000040_CRTC2_VLINE(x)                      (((x) >> 5) & 0x1)
0214 #define   C_000040_CRTC2_VLINE                         0xFFFFFFDF
0215 #define   S_000040_DMA_VIPH0_INT_EN(x)                 (((x) & 0x1) << 12)
0216 #define   G_000040_DMA_VIPH0_INT_EN(x)                 (((x) >> 12) & 0x1)
0217 #define   C_000040_DMA_VIPH0_INT_EN                    0xFFFFEFFF
0218 #define   S_000040_CRTC2_VSYNC(x)                      (((x) & 0x1) << 6)
0219 #define   G_000040_CRTC2_VSYNC(x)                      (((x) >> 6) & 0x1)
0220 #define   C_000040_CRTC2_VSYNC                         0xFFFFFFBF
0221 #define   S_000040_SNAPSHOT2(x)                        (((x) & 0x1) << 7)
0222 #define   G_000040_SNAPSHOT2(x)                        (((x) >> 7) & 0x1)
0223 #define   C_000040_SNAPSHOT2                           0xFFFFFF7F
0224 #define   S_000040_CRTC2_VBLANK(x)                     (((x) & 0x1) << 9)
0225 #define   G_000040_CRTC2_VBLANK(x)                     (((x) >> 9) & 0x1)
0226 #define   C_000040_CRTC2_VBLANK                        0xFFFFFDFF
0227 #define   S_000040_FP2_DETECT(x)                       (((x) & 0x1) << 10)
0228 #define   G_000040_FP2_DETECT(x)                       (((x) >> 10) & 0x1)
0229 #define   C_000040_FP2_DETECT                          0xFFFFFBFF
0230 #define   S_000040_VSYNC_DIFF_OVER_LIMIT(x)            (((x) & 0x1) << 11)
0231 #define   G_000040_VSYNC_DIFF_OVER_LIMIT(x)            (((x) >> 11) & 0x1)
0232 #define   C_000040_VSYNC_DIFF_OVER_LIMIT               0xFFFFF7FF
0233 #define   S_000040_DMA_VIPH1_INT_EN(x)                 (((x) & 0x1) << 13)
0234 #define   G_000040_DMA_VIPH1_INT_EN(x)                 (((x) >> 13) & 0x1)
0235 #define   C_000040_DMA_VIPH1_INT_EN                    0xFFFFDFFF
0236 #define   S_000040_DMA_VIPH2_INT_EN(x)                 (((x) & 0x1) << 14)
0237 #define   G_000040_DMA_VIPH2_INT_EN(x)                 (((x) >> 14) & 0x1)
0238 #define   C_000040_DMA_VIPH2_INT_EN                    0xFFFFBFFF
0239 #define   S_000040_DMA_VIPH3_INT_EN(x)                 (((x) & 0x1) << 15)
0240 #define   G_000040_DMA_VIPH3_INT_EN(x)                 (((x) >> 15) & 0x1)
0241 #define   C_000040_DMA_VIPH3_INT_EN                    0xFFFF7FFF
0242 #define   S_000040_I2C_INT_EN(x)                       (((x) & 0x1) << 17)
0243 #define   G_000040_I2C_INT_EN(x)                       (((x) >> 17) & 0x1)
0244 #define   C_000040_I2C_INT_EN                          0xFFFDFFFF
0245 #define   S_000040_GUI_IDLE(x)                         (((x) & 0x1) << 19)
0246 #define   G_000040_GUI_IDLE(x)                         (((x) >> 19) & 0x1)
0247 #define   C_000040_GUI_IDLE                            0xFFF7FFFF
0248 #define   S_000040_VIPH_INT_EN(x)                      (((x) & 0x1) << 24)
0249 #define   G_000040_VIPH_INT_EN(x)                      (((x) >> 24) & 0x1)
0250 #define   C_000040_VIPH_INT_EN                         0xFEFFFFFF
0251 #define   S_000040_SW_INT_EN(x)                        (((x) & 0x1) << 25)
0252 #define   G_000040_SW_INT_EN(x)                        (((x) >> 25) & 0x1)
0253 #define   C_000040_SW_INT_EN                           0xFDFFFFFF
0254 #define   S_000040_GEYSERVILLE(x)                      (((x) & 0x1) << 27)
0255 #define   G_000040_GEYSERVILLE(x)                      (((x) >> 27) & 0x1)
0256 #define   C_000040_GEYSERVILLE                         0xF7FFFFFF
0257 #define   S_000040_HDCP_AUTHORIZED_INT(x)              (((x) & 0x1) << 28)
0258 #define   G_000040_HDCP_AUTHORIZED_INT(x)              (((x) >> 28) & 0x1)
0259 #define   C_000040_HDCP_AUTHORIZED_INT                 0xEFFFFFFF
0260 #define   S_000040_DVI_I2C_INT(x)                      (((x) & 0x1) << 29)
0261 #define   G_000040_DVI_I2C_INT(x)                      (((x) >> 29) & 0x1)
0262 #define   C_000040_DVI_I2C_INT                         0xDFFFFFFF
0263 #define   S_000040_GUIDMA(x)                           (((x) & 0x1) << 30)
0264 #define   G_000040_GUIDMA(x)                           (((x) >> 30) & 0x1)
0265 #define   C_000040_GUIDMA                              0xBFFFFFFF
0266 #define   S_000040_VIDDMA(x)                           (((x) & 0x1) << 31)
0267 #define   G_000040_VIDDMA(x)                           (((x) >> 31) & 0x1)
0268 #define   C_000040_VIDDMA                              0x7FFFFFFF
0269 #define R_000044_GEN_INT_STATUS                      0x000044
0270 #define   S_000044_CRTC_VBLANK_STAT(x)                 (((x) & 0x1) << 0)
0271 #define   G_000044_CRTC_VBLANK_STAT(x)                 (((x) >> 0) & 0x1)
0272 #define   C_000044_CRTC_VBLANK_STAT                    0xFFFFFFFE
0273 #define   S_000044_CRTC_VBLANK_STAT_AK(x)              (((x) & 0x1) << 0)
0274 #define   G_000044_CRTC_VBLANK_STAT_AK(x)              (((x) >> 0) & 0x1)
0275 #define   C_000044_CRTC_VBLANK_STAT_AK                 0xFFFFFFFE
0276 #define   S_000044_CRTC_VLINE_STAT(x)                  (((x) & 0x1) << 1)
0277 #define   G_000044_CRTC_VLINE_STAT(x)                  (((x) >> 1) & 0x1)
0278 #define   C_000044_CRTC_VLINE_STAT                     0xFFFFFFFD
0279 #define   S_000044_CRTC_VLINE_STAT_AK(x)               (((x) & 0x1) << 1)
0280 #define   G_000044_CRTC_VLINE_STAT_AK(x)               (((x) >> 1) & 0x1)
0281 #define   C_000044_CRTC_VLINE_STAT_AK                  0xFFFFFFFD
0282 #define   S_000044_CRTC_VSYNC_STAT(x)                  (((x) & 0x1) << 2)
0283 #define   G_000044_CRTC_VSYNC_STAT(x)                  (((x) >> 2) & 0x1)
0284 #define   C_000044_CRTC_VSYNC_STAT                     0xFFFFFFFB
0285 #define   S_000044_CRTC_VSYNC_STAT_AK(x)               (((x) & 0x1) << 2)
0286 #define   G_000044_CRTC_VSYNC_STAT_AK(x)               (((x) >> 2) & 0x1)
0287 #define   C_000044_CRTC_VSYNC_STAT_AK                  0xFFFFFFFB
0288 #define   S_000044_SNAPSHOT_STAT(x)                    (((x) & 0x1) << 3)
0289 #define   G_000044_SNAPSHOT_STAT(x)                    (((x) >> 3) & 0x1)
0290 #define   C_000044_SNAPSHOT_STAT                       0xFFFFFFF7
0291 #define   S_000044_SNAPSHOT_STAT_AK(x)                 (((x) & 0x1) << 3)
0292 #define   G_000044_SNAPSHOT_STAT_AK(x)                 (((x) >> 3) & 0x1)
0293 #define   C_000044_SNAPSHOT_STAT_AK                    0xFFFFFFF7
0294 #define   S_000044_FP_DETECT_STAT(x)                   (((x) & 0x1) << 4)
0295 #define   G_000044_FP_DETECT_STAT(x)                   (((x) >> 4) & 0x1)
0296 #define   C_000044_FP_DETECT_STAT                      0xFFFFFFEF
0297 #define   S_000044_FP_DETECT_STAT_AK(x)                (((x) & 0x1) << 4)
0298 #define   G_000044_FP_DETECT_STAT_AK(x)                (((x) >> 4) & 0x1)
0299 #define   C_000044_FP_DETECT_STAT_AK                   0xFFFFFFEF
0300 #define   S_000044_CRTC2_VLINE_STAT(x)                 (((x) & 0x1) << 5)
0301 #define   G_000044_CRTC2_VLINE_STAT(x)                 (((x) >> 5) & 0x1)
0302 #define   C_000044_CRTC2_VLINE_STAT                    0xFFFFFFDF
0303 #define   S_000044_CRTC2_VLINE_STAT_AK(x)              (((x) & 0x1) << 5)
0304 #define   G_000044_CRTC2_VLINE_STAT_AK(x)              (((x) >> 5) & 0x1)
0305 #define   C_000044_CRTC2_VLINE_STAT_AK                 0xFFFFFFDF
0306 #define   S_000044_CRTC2_VSYNC_STAT(x)                 (((x) & 0x1) << 6)
0307 #define   G_000044_CRTC2_VSYNC_STAT(x)                 (((x) >> 6) & 0x1)
0308 #define   C_000044_CRTC2_VSYNC_STAT                    0xFFFFFFBF
0309 #define   S_000044_CRTC2_VSYNC_STAT_AK(x)              (((x) & 0x1) << 6)
0310 #define   G_000044_CRTC2_VSYNC_STAT_AK(x)              (((x) >> 6) & 0x1)
0311 #define   C_000044_CRTC2_VSYNC_STAT_AK                 0xFFFFFFBF
0312 #define   S_000044_SNAPSHOT2_STAT(x)                   (((x) & 0x1) << 7)
0313 #define   G_000044_SNAPSHOT2_STAT(x)                   (((x) >> 7) & 0x1)
0314 #define   C_000044_SNAPSHOT2_STAT                      0xFFFFFF7F
0315 #define   S_000044_SNAPSHOT2_STAT_AK(x)                (((x) & 0x1) << 7)
0316 #define   G_000044_SNAPSHOT2_STAT_AK(x)                (((x) >> 7) & 0x1)
0317 #define   C_000044_SNAPSHOT2_STAT_AK                   0xFFFFFF7F
0318 #define   S_000044_CAP0_INT_ACTIVE(x)                  (((x) & 0x1) << 8)
0319 #define   G_000044_CAP0_INT_ACTIVE(x)                  (((x) >> 8) & 0x1)
0320 #define   C_000044_CAP0_INT_ACTIVE                     0xFFFFFEFF
0321 #define   S_000044_CRTC2_VBLANK_STAT(x)                (((x) & 0x1) << 9)
0322 #define   G_000044_CRTC2_VBLANK_STAT(x)                (((x) >> 9) & 0x1)
0323 #define   C_000044_CRTC2_VBLANK_STAT                   0xFFFFFDFF
0324 #define   S_000044_CRTC2_VBLANK_STAT_AK(x)             (((x) & 0x1) << 9)
0325 #define   G_000044_CRTC2_VBLANK_STAT_AK(x)             (((x) >> 9) & 0x1)
0326 #define   C_000044_CRTC2_VBLANK_STAT_AK                0xFFFFFDFF
0327 #define   S_000044_FP2_DETECT_STAT(x)                  (((x) & 0x1) << 10)
0328 #define   G_000044_FP2_DETECT_STAT(x)                  (((x) >> 10) & 0x1)
0329 #define   C_000044_FP2_DETECT_STAT                     0xFFFFFBFF
0330 #define   S_000044_FP2_DETECT_STAT_AK(x)               (((x) & 0x1) << 10)
0331 #define   G_000044_FP2_DETECT_STAT_AK(x)               (((x) >> 10) & 0x1)
0332 #define   C_000044_FP2_DETECT_STAT_AK                  0xFFFFFBFF
0333 #define   S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x)       (((x) & 0x1) << 11)
0334 #define   G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x)       (((x) >> 11) & 0x1)
0335 #define   C_000044_VSYNC_DIFF_OVER_LIMIT_STAT          0xFFFFF7FF
0336 #define   S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x)    (((x) & 0x1) << 11)
0337 #define   G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x)    (((x) >> 11) & 0x1)
0338 #define   C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK       0xFFFFF7FF
0339 #define   S_000044_DMA_VIPH0_INT(x)                    (((x) & 0x1) << 12)
0340 #define   G_000044_DMA_VIPH0_INT(x)                    (((x) >> 12) & 0x1)
0341 #define   C_000044_DMA_VIPH0_INT                       0xFFFFEFFF
0342 #define   S_000044_DMA_VIPH0_INT_AK(x)                 (((x) & 0x1) << 12)
0343 #define   G_000044_DMA_VIPH0_INT_AK(x)                 (((x) >> 12) & 0x1)
0344 #define   C_000044_DMA_VIPH0_INT_AK                    0xFFFFEFFF
0345 #define   S_000044_DMA_VIPH1_INT(x)                    (((x) & 0x1) << 13)
0346 #define   G_000044_DMA_VIPH1_INT(x)                    (((x) >> 13) & 0x1)
0347 #define   C_000044_DMA_VIPH1_INT                       0xFFFFDFFF
0348 #define   S_000044_DMA_VIPH1_INT_AK(x)                 (((x) & 0x1) << 13)
0349 #define   G_000044_DMA_VIPH1_INT_AK(x)                 (((x) >> 13) & 0x1)
0350 #define   C_000044_DMA_VIPH1_INT_AK                    0xFFFFDFFF
0351 #define   S_000044_DMA_VIPH2_INT(x)                    (((x) & 0x1) << 14)
0352 #define   G_000044_DMA_VIPH2_INT(x)                    (((x) >> 14) & 0x1)
0353 #define   C_000044_DMA_VIPH2_INT                       0xFFFFBFFF
0354 #define   S_000044_DMA_VIPH2_INT_AK(x)                 (((x) & 0x1) << 14)
0355 #define   G_000044_DMA_VIPH2_INT_AK(x)                 (((x) >> 14) & 0x1)
0356 #define   C_000044_DMA_VIPH2_INT_AK                    0xFFFFBFFF
0357 #define   S_000044_DMA_VIPH3_INT(x)                    (((x) & 0x1) << 15)
0358 #define   G_000044_DMA_VIPH3_INT(x)                    (((x) >> 15) & 0x1)
0359 #define   C_000044_DMA_VIPH3_INT                       0xFFFF7FFF
0360 #define   S_000044_DMA_VIPH3_INT_AK(x)                 (((x) & 0x1) << 15)
0361 #define   G_000044_DMA_VIPH3_INT_AK(x)                 (((x) >> 15) & 0x1)
0362 #define   C_000044_DMA_VIPH3_INT_AK                    0xFFFF7FFF
0363 #define   S_000044_I2C_INT(x)                          (((x) & 0x1) << 17)
0364 #define   G_000044_I2C_INT(x)                          (((x) >> 17) & 0x1)
0365 #define   C_000044_I2C_INT                             0xFFFDFFFF
0366 #define   S_000044_I2C_INT_AK(x)                       (((x) & 0x1) << 17)
0367 #define   G_000044_I2C_INT_AK(x)                       (((x) >> 17) & 0x1)
0368 #define   C_000044_I2C_INT_AK                          0xFFFDFFFF
0369 #define   S_000044_GUI_IDLE_STAT(x)                    (((x) & 0x1) << 19)
0370 #define   G_000044_GUI_IDLE_STAT(x)                    (((x) >> 19) & 0x1)
0371 #define   C_000044_GUI_IDLE_STAT                       0xFFF7FFFF
0372 #define   S_000044_GUI_IDLE_STAT_AK(x)                 (((x) & 0x1) << 19)
0373 #define   G_000044_GUI_IDLE_STAT_AK(x)                 (((x) >> 19) & 0x1)
0374 #define   C_000044_GUI_IDLE_STAT_AK                    0xFFF7FFFF
0375 #define   S_000044_VIPH_INT(x)                         (((x) & 0x1) << 24)
0376 #define   G_000044_VIPH_INT(x)                         (((x) >> 24) & 0x1)
0377 #define   C_000044_VIPH_INT                            0xFEFFFFFF
0378 #define   S_000044_SW_INT(x)                           (((x) & 0x1) << 25)
0379 #define   G_000044_SW_INT(x)                           (((x) >> 25) & 0x1)
0380 #define   C_000044_SW_INT                              0xFDFFFFFF
0381 #define   S_000044_SW_INT_AK(x)                        (((x) & 0x1) << 25)
0382 #define   G_000044_SW_INT_AK(x)                        (((x) >> 25) & 0x1)
0383 #define   C_000044_SW_INT_AK                           0xFDFFFFFF
0384 #define   S_000044_SW_INT_SET(x)                       (((x) & 0x1) << 26)
0385 #define   G_000044_SW_INT_SET(x)                       (((x) >> 26) & 0x1)
0386 #define   C_000044_SW_INT_SET                          0xFBFFFFFF
0387 #define   S_000044_GEYSERVILLE_STAT(x)                 (((x) & 0x1) << 27)
0388 #define   G_000044_GEYSERVILLE_STAT(x)                 (((x) >> 27) & 0x1)
0389 #define   C_000044_GEYSERVILLE_STAT                    0xF7FFFFFF
0390 #define   S_000044_GEYSERVILLE_STAT_AK(x)              (((x) & 0x1) << 27)
0391 #define   G_000044_GEYSERVILLE_STAT_AK(x)              (((x) >> 27) & 0x1)
0392 #define   C_000044_GEYSERVILLE_STAT_AK                 0xF7FFFFFF
0393 #define   S_000044_HDCP_AUTHORIZED_INT_STAT(x)         (((x) & 0x1) << 28)
0394 #define   G_000044_HDCP_AUTHORIZED_INT_STAT(x)         (((x) >> 28) & 0x1)
0395 #define   C_000044_HDCP_AUTHORIZED_INT_STAT            0xEFFFFFFF
0396 #define   S_000044_HDCP_AUTHORIZED_INT_AK(x)           (((x) & 0x1) << 28)
0397 #define   G_000044_HDCP_AUTHORIZED_INT_AK(x)           (((x) >> 28) & 0x1)
0398 #define   C_000044_HDCP_AUTHORIZED_INT_AK              0xEFFFFFFF
0399 #define   S_000044_DVI_I2C_INT_STAT(x)                 (((x) & 0x1) << 29)
0400 #define   G_000044_DVI_I2C_INT_STAT(x)                 (((x) >> 29) & 0x1)
0401 #define   C_000044_DVI_I2C_INT_STAT                    0xDFFFFFFF
0402 #define   S_000044_DVI_I2C_INT_AK(x)                   (((x) & 0x1) << 29)
0403 #define   G_000044_DVI_I2C_INT_AK(x)                   (((x) >> 29) & 0x1)
0404 #define   C_000044_DVI_I2C_INT_AK                      0xDFFFFFFF
0405 #define   S_000044_GUIDMA_STAT(x)                      (((x) & 0x1) << 30)
0406 #define   G_000044_GUIDMA_STAT(x)                      (((x) >> 30) & 0x1)
0407 #define   C_000044_GUIDMA_STAT                         0xBFFFFFFF
0408 #define   S_000044_GUIDMA_AK(x)                        (((x) & 0x1) << 30)
0409 #define   G_000044_GUIDMA_AK(x)                        (((x) >> 30) & 0x1)
0410 #define   C_000044_GUIDMA_AK                           0xBFFFFFFF
0411 #define   S_000044_VIDDMA_STAT(x)                      (((x) & 0x1) << 31)
0412 #define   G_000044_VIDDMA_STAT(x)                      (((x) >> 31) & 0x1)
0413 #define   C_000044_VIDDMA_STAT                         0x7FFFFFFF
0414 #define   S_000044_VIDDMA_AK(x)                        (((x) & 0x1) << 31)
0415 #define   G_000044_VIDDMA_AK(x)                        (((x) >> 31) & 0x1)
0416 #define   C_000044_VIDDMA_AK                           0x7FFFFFFF
0417 #define R_000050_CRTC_GEN_CNTL                       0x000050
0418 #define   S_000050_CRTC_DBL_SCAN_EN(x)                 (((x) & 0x1) << 0)
0419 #define   G_000050_CRTC_DBL_SCAN_EN(x)                 (((x) >> 0) & 0x1)
0420 #define   C_000050_CRTC_DBL_SCAN_EN                    0xFFFFFFFE
0421 #define   S_000050_CRTC_INTERLACE_EN(x)                (((x) & 0x1) << 1)
0422 #define   G_000050_CRTC_INTERLACE_EN(x)                (((x) >> 1) & 0x1)
0423 #define   C_000050_CRTC_INTERLACE_EN                   0xFFFFFFFD
0424 #define   S_000050_CRTC_C_SYNC_EN(x)                   (((x) & 0x1) << 4)
0425 #define   G_000050_CRTC_C_SYNC_EN(x)                   (((x) >> 4) & 0x1)
0426 #define   C_000050_CRTC_C_SYNC_EN                      0xFFFFFFEF
0427 #define   S_000050_CRTC_PIX_WIDTH(x)                   (((x) & 0xF) << 8)
0428 #define   G_000050_CRTC_PIX_WIDTH(x)                   (((x) >> 8) & 0xF)
0429 #define   C_000050_CRTC_PIX_WIDTH                      0xFFFFF0FF
0430 #define   S_000050_CRTC_ICON_EN(x)                     (((x) & 0x1) << 15)
0431 #define   G_000050_CRTC_ICON_EN(x)                     (((x) >> 15) & 0x1)
0432 #define   C_000050_CRTC_ICON_EN                        0xFFFF7FFF
0433 #define   S_000050_CRTC_CUR_EN(x)                      (((x) & 0x1) << 16)
0434 #define   G_000050_CRTC_CUR_EN(x)                      (((x) >> 16) & 0x1)
0435 #define   C_000050_CRTC_CUR_EN                         0xFFFEFFFF
0436 #define   S_000050_CRTC_VSTAT_MODE(x)                  (((x) & 0x3) << 17)
0437 #define   G_000050_CRTC_VSTAT_MODE(x)                  (((x) >> 17) & 0x3)
0438 #define   C_000050_CRTC_VSTAT_MODE                     0xFFF9FFFF
0439 #define   S_000050_CRTC_CUR_MODE(x)                    (((x) & 0x7) << 20)
0440 #define   G_000050_CRTC_CUR_MODE(x)                    (((x) >> 20) & 0x7)
0441 #define   C_000050_CRTC_CUR_MODE                       0xFF8FFFFF
0442 #define   S_000050_CRTC_EXT_DISP_EN(x)                 (((x) & 0x1) << 24)
0443 #define   G_000050_CRTC_EXT_DISP_EN(x)                 (((x) >> 24) & 0x1)
0444 #define   C_000050_CRTC_EXT_DISP_EN                    0xFEFFFFFF
0445 #define   S_000050_CRTC_EN(x)                          (((x) & 0x1) << 25)
0446 #define   G_000050_CRTC_EN(x)                          (((x) >> 25) & 0x1)
0447 #define   C_000050_CRTC_EN                             0xFDFFFFFF
0448 #define   S_000050_CRTC_DISP_REQ_EN_B(x)               (((x) & 0x1) << 26)
0449 #define   G_000050_CRTC_DISP_REQ_EN_B(x)               (((x) >> 26) & 0x1)
0450 #define   C_000050_CRTC_DISP_REQ_EN_B                  0xFBFFFFFF
0451 #define R_000054_CRTC_EXT_CNTL                       0x000054
0452 #define   S_000054_CRTC_VGA_XOVERSCAN(x)               (((x) & 0x1) << 0)
0453 #define   G_000054_CRTC_VGA_XOVERSCAN(x)               (((x) >> 0) & 0x1)
0454 #define   C_000054_CRTC_VGA_XOVERSCAN                  0xFFFFFFFE
0455 #define   S_000054_VGA_BLINK_RATE(x)                   (((x) & 0x3) << 1)
0456 #define   G_000054_VGA_BLINK_RATE(x)                   (((x) >> 1) & 0x3)
0457 #define   C_000054_VGA_BLINK_RATE                      0xFFFFFFF9
0458 #define   S_000054_VGA_ATI_LINEAR(x)                   (((x) & 0x1) << 3)
0459 #define   G_000054_VGA_ATI_LINEAR(x)                   (((x) >> 3) & 0x1)
0460 #define   C_000054_VGA_ATI_LINEAR                      0xFFFFFFF7
0461 #define   S_000054_VGA_128KAP_PAGING(x)                (((x) & 0x1) << 4)
0462 #define   G_000054_VGA_128KAP_PAGING(x)                (((x) >> 4) & 0x1)
0463 #define   C_000054_VGA_128KAP_PAGING                   0xFFFFFFEF
0464 #define   S_000054_VGA_TEXT_132(x)                     (((x) & 0x1) << 5)
0465 #define   G_000054_VGA_TEXT_132(x)                     (((x) >> 5) & 0x1)
0466 #define   C_000054_VGA_TEXT_132                        0xFFFFFFDF
0467 #define   S_000054_VGA_XCRT_CNT_EN(x)                  (((x) & 0x1) << 6)
0468 #define   G_000054_VGA_XCRT_CNT_EN(x)                  (((x) >> 6) & 0x1)
0469 #define   C_000054_VGA_XCRT_CNT_EN                     0xFFFFFFBF
0470 #define   S_000054_CRTC_HSYNC_DIS(x)                   (((x) & 0x1) << 8)
0471 #define   G_000054_CRTC_HSYNC_DIS(x)                   (((x) >> 8) & 0x1)
0472 #define   C_000054_CRTC_HSYNC_DIS                      0xFFFFFEFF
0473 #define   S_000054_CRTC_VSYNC_DIS(x)                   (((x) & 0x1) << 9)
0474 #define   G_000054_CRTC_VSYNC_DIS(x)                   (((x) >> 9) & 0x1)
0475 #define   C_000054_CRTC_VSYNC_DIS                      0xFFFFFDFF
0476 #define   S_000054_CRTC_DISPLAY_DIS(x)                 (((x) & 0x1) << 10)
0477 #define   G_000054_CRTC_DISPLAY_DIS(x)                 (((x) >> 10) & 0x1)
0478 #define   C_000054_CRTC_DISPLAY_DIS                    0xFFFFFBFF
0479 #define   S_000054_CRTC_SYNC_TRISTATE(x)               (((x) & 0x1) << 11)
0480 #define   G_000054_CRTC_SYNC_TRISTATE(x)               (((x) >> 11) & 0x1)
0481 #define   C_000054_CRTC_SYNC_TRISTATE                  0xFFFFF7FF
0482 #define   S_000054_CRTC_HSYNC_TRISTATE(x)              (((x) & 0x1) << 12)
0483 #define   G_000054_CRTC_HSYNC_TRISTATE(x)              (((x) >> 12) & 0x1)
0484 #define   C_000054_CRTC_HSYNC_TRISTATE                 0xFFFFEFFF
0485 #define   S_000054_CRTC_VSYNC_TRISTATE(x)              (((x) & 0x1) << 13)
0486 #define   G_000054_CRTC_VSYNC_TRISTATE(x)              (((x) >> 13) & 0x1)
0487 #define   C_000054_CRTC_VSYNC_TRISTATE                 0xFFFFDFFF
0488 #define   S_000054_CRT_ON(x)                           (((x) & 0x1) << 15)
0489 #define   G_000054_CRT_ON(x)                           (((x) >> 15) & 0x1)
0490 #define   C_000054_CRT_ON                              0xFFFF7FFF
0491 #define   S_000054_VGA_CUR_B_TEST(x)                   (((x) & 0x1) << 17)
0492 #define   G_000054_VGA_CUR_B_TEST(x)                   (((x) >> 17) & 0x1)
0493 #define   C_000054_VGA_CUR_B_TEST                      0xFFFDFFFF
0494 #define   S_000054_VGA_PACK_DIS(x)                     (((x) & 0x1) << 18)
0495 #define   G_000054_VGA_PACK_DIS(x)                     (((x) >> 18) & 0x1)
0496 #define   C_000054_VGA_PACK_DIS                        0xFFFBFFFF
0497 #define   S_000054_VGA_MEM_PS_EN(x)                    (((x) & 0x1) << 19)
0498 #define   G_000054_VGA_MEM_PS_EN(x)                    (((x) >> 19) & 0x1)
0499 #define   C_000054_VGA_MEM_PS_EN                       0xFFF7FFFF
0500 #define   S_000054_VCRTC_IDX_MASTER(x)                 (((x) & 0x7F) << 24)
0501 #define   G_000054_VCRTC_IDX_MASTER(x)                 (((x) >> 24) & 0x7F)
0502 #define   C_000054_VCRTC_IDX_MASTER                    0x80FFFFFF
0503 #define R_000148_MC_FB_LOCATION                      0x000148
0504 #define   S_000148_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
0505 #define   G_000148_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
0506 #define   C_000148_MC_FB_START                         0xFFFF0000
0507 #define   S_000148_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
0508 #define   G_000148_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
0509 #define   C_000148_MC_FB_TOP                           0x0000FFFF
0510 #define R_00014C_MC_AGP_LOCATION                     0x00014C
0511 #define   S_00014C_MC_AGP_START(x)                     (((x) & 0xFFFF) << 0)
0512 #define   G_00014C_MC_AGP_START(x)                     (((x) >> 0) & 0xFFFF)
0513 #define   C_00014C_MC_AGP_START                        0xFFFF0000
0514 #define   S_00014C_MC_AGP_TOP(x)                       (((x) & 0xFFFF) << 16)
0515 #define   G_00014C_MC_AGP_TOP(x)                       (((x) >> 16) & 0xFFFF)
0516 #define   C_00014C_MC_AGP_TOP                          0x0000FFFF
0517 #define R_000170_AGP_BASE                            0x000170
0518 #define   S_000170_AGP_BASE_ADDR(x)                    (((x) & 0xFFFFFFFF) << 0)
0519 #define   G_000170_AGP_BASE_ADDR(x)                    (((x) >> 0) & 0xFFFFFFFF)
0520 #define   C_000170_AGP_BASE_ADDR                       0x00000000
0521 #define R_00023C_DISPLAY_BASE_ADDR                   0x00023C
0522 #define   S_00023C_DISPLAY_BASE_ADDR(x)                (((x) & 0xFFFFFFFF) << 0)
0523 #define   G_00023C_DISPLAY_BASE_ADDR(x)                (((x) >> 0) & 0xFFFFFFFF)
0524 #define   C_00023C_DISPLAY_BASE_ADDR                   0x00000000
0525 #define R_000260_CUR_OFFSET                          0x000260
0526 #define   S_000260_CUR_OFFSET(x)                       (((x) & 0x7FFFFFF) << 0)
0527 #define   G_000260_CUR_OFFSET(x)                       (((x) >> 0) & 0x7FFFFFF)
0528 #define   C_000260_CUR_OFFSET                          0xF8000000
0529 #define   S_000260_CUR_LOCK(x)                         (((x) & 0x1) << 31)
0530 #define   G_000260_CUR_LOCK(x)                         (((x) >> 31) & 0x1)
0531 #define   C_000260_CUR_LOCK                            0x7FFFFFFF
0532 #define R_00033C_CRTC2_DISPLAY_BASE_ADDR             0x00033C
0533 #define   S_00033C_CRTC2_DISPLAY_BASE_ADDR(x)          (((x) & 0xFFFFFFFF) << 0)
0534 #define   G_00033C_CRTC2_DISPLAY_BASE_ADDR(x)          (((x) >> 0) & 0xFFFFFFFF)
0535 #define   C_00033C_CRTC2_DISPLAY_BASE_ADDR             0x00000000
0536 #define R_000360_CUR2_OFFSET                         0x000360
0537 #define   S_000360_CUR2_OFFSET(x)                      (((x) & 0x7FFFFFF) << 0)
0538 #define   G_000360_CUR2_OFFSET(x)                      (((x) >> 0) & 0x7FFFFFF)
0539 #define   C_000360_CUR2_OFFSET                         0xF8000000
0540 #define   S_000360_CUR2_LOCK(x)                        (((x) & 0x1) << 31)
0541 #define   G_000360_CUR2_LOCK(x)                        (((x) >> 31) & 0x1)
0542 #define   C_000360_CUR2_LOCK                           0x7FFFFFFF
0543 #define R_0003C2_GENMO_WT                            0x0003C2
0544 #define   S_0003C2_GENMO_MONO_ADDRESS_B(x)             (((x) & 0x1) << 0)
0545 #define   G_0003C2_GENMO_MONO_ADDRESS_B(x)             (((x) >> 0) & 0x1)
0546 #define   C_0003C2_GENMO_MONO_ADDRESS_B                0xFE
0547 #define   S_0003C2_VGA_RAM_EN(x)                       (((x) & 0x1) << 1)
0548 #define   G_0003C2_VGA_RAM_EN(x)                       (((x) >> 1) & 0x1)
0549 #define   C_0003C2_VGA_RAM_EN                          0xFD
0550 #define   S_0003C2_VGA_CKSEL(x)                        (((x) & 0x3) << 2)
0551 #define   G_0003C2_VGA_CKSEL(x)                        (((x) >> 2) & 0x3)
0552 #define   C_0003C2_VGA_CKSEL                           0xF3
0553 #define   S_0003C2_ODD_EVEN_MD_PGSEL(x)                (((x) & 0x1) << 5)
0554 #define   G_0003C2_ODD_EVEN_MD_PGSEL(x)                (((x) >> 5) & 0x1)
0555 #define   C_0003C2_ODD_EVEN_MD_PGSEL                   0xDF
0556 #define   S_0003C2_VGA_HSYNC_POL(x)                    (((x) & 0x1) << 6)
0557 #define   G_0003C2_VGA_HSYNC_POL(x)                    (((x) >> 6) & 0x1)
0558 #define   C_0003C2_VGA_HSYNC_POL                       0xBF
0559 #define   S_0003C2_VGA_VSYNC_POL(x)                    (((x) & 0x1) << 7)
0560 #define   G_0003C2_VGA_VSYNC_POL(x)                    (((x) >> 7) & 0x1)
0561 #define   C_0003C2_VGA_VSYNC_POL                       0x7F
0562 #define R_0003F8_CRTC2_GEN_CNTL                      0x0003F8
0563 #define   S_0003F8_CRTC2_DBL_SCAN_EN(x)                (((x) & 0x1) << 0)
0564 #define   G_0003F8_CRTC2_DBL_SCAN_EN(x)                (((x) >> 0) & 0x1)
0565 #define   C_0003F8_CRTC2_DBL_SCAN_EN                   0xFFFFFFFE
0566 #define   S_0003F8_CRTC2_INTERLACE_EN(x)               (((x) & 0x1) << 1)
0567 #define   G_0003F8_CRTC2_INTERLACE_EN(x)               (((x) >> 1) & 0x1)
0568 #define   C_0003F8_CRTC2_INTERLACE_EN                  0xFFFFFFFD
0569 #define   S_0003F8_CRTC2_SYNC_TRISTATE(x)              (((x) & 0x1) << 4)
0570 #define   G_0003F8_CRTC2_SYNC_TRISTATE(x)              (((x) >> 4) & 0x1)
0571 #define   C_0003F8_CRTC2_SYNC_TRISTATE                 0xFFFFFFEF
0572 #define   S_0003F8_CRTC2_HSYNC_TRISTATE(x)             (((x) & 0x1) << 5)
0573 #define   G_0003F8_CRTC2_HSYNC_TRISTATE(x)             (((x) >> 5) & 0x1)
0574 #define   C_0003F8_CRTC2_HSYNC_TRISTATE                0xFFFFFFDF
0575 #define   S_0003F8_CRTC2_VSYNC_TRISTATE(x)             (((x) & 0x1) << 6)
0576 #define   G_0003F8_CRTC2_VSYNC_TRISTATE(x)             (((x) >> 6) & 0x1)
0577 #define   C_0003F8_CRTC2_VSYNC_TRISTATE                0xFFFFFFBF
0578 #define   S_0003F8_CRT2_ON(x)                          (((x) & 0x1) << 7)
0579 #define   G_0003F8_CRT2_ON(x)                          (((x) >> 7) & 0x1)
0580 #define   C_0003F8_CRT2_ON                             0xFFFFFF7F
0581 #define   S_0003F8_CRTC2_PIX_WIDTH(x)                  (((x) & 0xF) << 8)
0582 #define   G_0003F8_CRTC2_PIX_WIDTH(x)                  (((x) >> 8) & 0xF)
0583 #define   C_0003F8_CRTC2_PIX_WIDTH                     0xFFFFF0FF
0584 #define   S_0003F8_CRTC2_ICON_EN(x)                    (((x) & 0x1) << 15)
0585 #define   G_0003F8_CRTC2_ICON_EN(x)                    (((x) >> 15) & 0x1)
0586 #define   C_0003F8_CRTC2_ICON_EN                       0xFFFF7FFF
0587 #define   S_0003F8_CRTC2_CUR_EN(x)                     (((x) & 0x1) << 16)
0588 #define   G_0003F8_CRTC2_CUR_EN(x)                     (((x) >> 16) & 0x1)
0589 #define   C_0003F8_CRTC2_CUR_EN                        0xFFFEFFFF
0590 #define   S_0003F8_CRTC2_CUR_MODE(x)                   (((x) & 0x7) << 20)
0591 #define   G_0003F8_CRTC2_CUR_MODE(x)                   (((x) >> 20) & 0x7)
0592 #define   C_0003F8_CRTC2_CUR_MODE                      0xFF8FFFFF
0593 #define   S_0003F8_CRTC2_DISPLAY_DIS(x)                (((x) & 0x1) << 23)
0594 #define   G_0003F8_CRTC2_DISPLAY_DIS(x)                (((x) >> 23) & 0x1)
0595 #define   C_0003F8_CRTC2_DISPLAY_DIS                   0xFF7FFFFF
0596 #define   S_0003F8_CRTC2_EN(x)                         (((x) & 0x1) << 25)
0597 #define   G_0003F8_CRTC2_EN(x)                         (((x) >> 25) & 0x1)
0598 #define   C_0003F8_CRTC2_EN                            0xFDFFFFFF
0599 #define   S_0003F8_CRTC2_DISP_REQ_EN_B(x)              (((x) & 0x1) << 26)
0600 #define   G_0003F8_CRTC2_DISP_REQ_EN_B(x)              (((x) >> 26) & 0x1)
0601 #define   C_0003F8_CRTC2_DISP_REQ_EN_B                 0xFBFFFFFF
0602 #define   S_0003F8_CRTC2_C_SYNC_EN(x)                  (((x) & 0x1) << 27)
0603 #define   G_0003F8_CRTC2_C_SYNC_EN(x)                  (((x) >> 27) & 0x1)
0604 #define   C_0003F8_CRTC2_C_SYNC_EN                     0xF7FFFFFF
0605 #define   S_0003F8_CRTC2_HSYNC_DIS(x)                  (((x) & 0x1) << 28)
0606 #define   G_0003F8_CRTC2_HSYNC_DIS(x)                  (((x) >> 28) & 0x1)
0607 #define   C_0003F8_CRTC2_HSYNC_DIS                     0xEFFFFFFF
0608 #define   S_0003F8_CRTC2_VSYNC_DIS(x)                  (((x) & 0x1) << 29)
0609 #define   G_0003F8_CRTC2_VSYNC_DIS(x)                  (((x) >> 29) & 0x1)
0610 #define   C_0003F8_CRTC2_VSYNC_DIS                     0xDFFFFFFF
0611 #define R_000420_OV0_SCALE_CNTL                      0x000420
0612 #define   S_000420_OV0_NO_READ_BEHIND_SCAN(x)          (((x) & 0x1) << 1)
0613 #define   G_000420_OV0_NO_READ_BEHIND_SCAN(x)          (((x) >> 1) & 0x1)
0614 #define   C_000420_OV0_NO_READ_BEHIND_SCAN             0xFFFFFFFD
0615 #define   S_000420_OV0_HORZ_PICK_NEAREST(x)            (((x) & 0x1) << 2)
0616 #define   G_000420_OV0_HORZ_PICK_NEAREST(x)            (((x) >> 2) & 0x1)
0617 #define   C_000420_OV0_HORZ_PICK_NEAREST               0xFFFFFFFB
0618 #define   S_000420_OV0_VERT_PICK_NEAREST(x)            (((x) & 0x1) << 3)
0619 #define   G_000420_OV0_VERT_PICK_NEAREST(x)            (((x) >> 3) & 0x1)
0620 #define   C_000420_OV0_VERT_PICK_NEAREST               0xFFFFFFF7
0621 #define   S_000420_OV0_SIGNED_UV(x)                    (((x) & 0x1) << 4)
0622 #define   G_000420_OV0_SIGNED_UV(x)                    (((x) >> 4) & 0x1)
0623 #define   C_000420_OV0_SIGNED_UV                       0xFFFFFFEF
0624 #define   S_000420_OV0_GAMMA_SEL(x)                    (((x) & 0x7) << 5)
0625 #define   G_000420_OV0_GAMMA_SEL(x)                    (((x) >> 5) & 0x7)
0626 #define   C_000420_OV0_GAMMA_SEL                       0xFFFFFF1F
0627 #define   S_000420_OV0_SURFACE_FORMAT(x)               (((x) & 0xF) << 8)
0628 #define   G_000420_OV0_SURFACE_FORMAT(x)               (((x) >> 8) & 0xF)
0629 #define   C_000420_OV0_SURFACE_FORMAT                  0xFFFFF0FF
0630 #define   S_000420_OV0_ADAPTIVE_DEINT(x)               (((x) & 0x1) << 12)
0631 #define   G_000420_OV0_ADAPTIVE_DEINT(x)               (((x) >> 12) & 0x1)
0632 #define   C_000420_OV0_ADAPTIVE_DEINT                  0xFFFFEFFF
0633 #define   S_000420_OV0_CRTC_SEL(x)                     (((x) & 0x1) << 14)
0634 #define   G_000420_OV0_CRTC_SEL(x)                     (((x) >> 14) & 0x1)
0635 #define   C_000420_OV0_CRTC_SEL                        0xFFFFBFFF
0636 #define   S_000420_OV0_BURST_PER_PLANE(x)              (((x) & 0x7F) << 16)
0637 #define   G_000420_OV0_BURST_PER_PLANE(x)              (((x) >> 16) & 0x7F)
0638 #define   C_000420_OV0_BURST_PER_PLANE                 0xFF80FFFF
0639 #define   S_000420_OV0_DOUBLE_BUFFER_REGS(x)           (((x) & 0x1) << 24)
0640 #define   G_000420_OV0_DOUBLE_BUFFER_REGS(x)           (((x) >> 24) & 0x1)
0641 #define   C_000420_OV0_DOUBLE_BUFFER_REGS              0xFEFFFFFF
0642 #define   S_000420_OV0_BANDWIDTH(x)                    (((x) & 0x1) << 26)
0643 #define   G_000420_OV0_BANDWIDTH(x)                    (((x) >> 26) & 0x1)
0644 #define   C_000420_OV0_BANDWIDTH                       0xFBFFFFFF
0645 #define   S_000420_OV0_LIN_TRANS_BYPASS(x)             (((x) & 0x1) << 28)
0646 #define   G_000420_OV0_LIN_TRANS_BYPASS(x)             (((x) >> 28) & 0x1)
0647 #define   C_000420_OV0_LIN_TRANS_BYPASS                0xEFFFFFFF
0648 #define   S_000420_OV0_INT_EMU(x)                      (((x) & 0x1) << 29)
0649 #define   G_000420_OV0_INT_EMU(x)                      (((x) >> 29) & 0x1)
0650 #define   C_000420_OV0_INT_EMU                         0xDFFFFFFF
0651 #define   S_000420_OV0_OVERLAY_EN(x)                   (((x) & 0x1) << 30)
0652 #define   G_000420_OV0_OVERLAY_EN(x)                   (((x) >> 30) & 0x1)
0653 #define   C_000420_OV0_OVERLAY_EN                      0xBFFFFFFF
0654 #define   S_000420_OV0_SOFT_RESET(x)                   (((x) & 0x1) << 31)
0655 #define   G_000420_OV0_SOFT_RESET(x)                   (((x) >> 31) & 0x1)
0656 #define   C_000420_OV0_SOFT_RESET                      0x7FFFFFFF
0657 #define R_00070C_CP_RB_RPTR_ADDR                     0x00070C
0658 #define   S_00070C_RB_RPTR_SWAP(x)                     (((x) & 0x3) << 0)
0659 #define   G_00070C_RB_RPTR_SWAP(x)                     (((x) >> 0) & 0x3)
0660 #define   C_00070C_RB_RPTR_SWAP                        0xFFFFFFFC
0661 #define   S_00070C_RB_RPTR_ADDR(x)                     (((x) & 0x3FFFFFFF) << 2)
0662 #define   G_00070C_RB_RPTR_ADDR(x)                     (((x) >> 2) & 0x3FFFFFFF)
0663 #define   C_00070C_RB_RPTR_ADDR                        0x00000003
0664 #define R_000740_CP_CSQ_CNTL                         0x000740
0665 #define   S_000740_CSQ_CNT_PRIMARY(x)                  (((x) & 0xFF) << 0)
0666 #define   G_000740_CSQ_CNT_PRIMARY(x)                  (((x) >> 0) & 0xFF)
0667 #define   C_000740_CSQ_CNT_PRIMARY                     0xFFFFFF00
0668 #define   S_000740_CSQ_CNT_INDIRECT(x)                 (((x) & 0xFF) << 8)
0669 #define   G_000740_CSQ_CNT_INDIRECT(x)                 (((x) >> 8) & 0xFF)
0670 #define   C_000740_CSQ_CNT_INDIRECT                    0xFFFF00FF
0671 #define   S_000740_CSQ_MODE(x)                         (((x) & 0xF) << 28)
0672 #define   G_000740_CSQ_MODE(x)                         (((x) >> 28) & 0xF)
0673 #define   C_000740_CSQ_MODE                            0x0FFFFFFF
0674 #define R_000770_SCRATCH_UMSK                        0x000770
0675 #define   S_000770_SCRATCH_UMSK(x)                     (((x) & 0x3F) << 0)
0676 #define   G_000770_SCRATCH_UMSK(x)                     (((x) >> 0) & 0x3F)
0677 #define   C_000770_SCRATCH_UMSK                        0xFFFFFFC0
0678 #define   S_000770_SCRATCH_SWAP(x)                     (((x) & 0x3) << 16)
0679 #define   G_000770_SCRATCH_SWAP(x)                     (((x) >> 16) & 0x3)
0680 #define   C_000770_SCRATCH_SWAP                        0xFFFCFFFF
0681 #define R_000774_SCRATCH_ADDR                        0x000774
0682 #define   S_000774_SCRATCH_ADDR(x)                     (((x) & 0x7FFFFFF) << 5)
0683 #define   G_000774_SCRATCH_ADDR(x)                     (((x) >> 5) & 0x7FFFFFF)
0684 #define   C_000774_SCRATCH_ADDR                        0x0000001F
0685 #define R_0007C0_CP_STAT                             0x0007C0
0686 #define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
0687 #define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
0688 #define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
0689 #define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
0690 #define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
0691 #define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
0692 #define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
0693 #define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
0694 #define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
0695 #define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
0696 #define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
0697 #define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
0698 #define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
0699 #define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
0700 #define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
0701 #define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
0702 #define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
0703 #define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
0704 #define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
0705 #define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
0706 #define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
0707 #define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
0708 #define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
0709 #define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
0710 #define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
0711 #define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
0712 #define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
0713 #define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
0714 #define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
0715 #define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
0716 #define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
0717 #define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
0718 #define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
0719 #define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
0720 #define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
0721 #define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
0722 #define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
0723 #define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
0724 #define   C_0007C0_CP_BUSY                             0x7FFFFFFF
0725 #define R_000E40_RBBM_STATUS                         0x000E40
0726 #define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
0727 #define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
0728 #define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
0729 #define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
0730 #define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
0731 #define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
0732 #define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
0733 #define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
0734 #define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
0735 #define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
0736 #define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
0737 #define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
0738 #define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
0739 #define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
0740 #define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
0741 #define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
0742 #define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
0743 #define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
0744 #define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
0745 #define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
0746 #define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
0747 #define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
0748 #define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
0749 #define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
0750 #define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
0751 #define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
0752 #define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
0753 #define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
0754 #define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
0755 #define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
0756 #define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
0757 #define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
0758 #define   C_000E40_E2_BUSY                             0xFFFDFFFF
0759 #define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
0760 #define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
0761 #define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
0762 #define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
0763 #define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
0764 #define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
0765 #define   S_000E40_SE_BUSY(x)                          (((x) & 0x1) << 20)
0766 #define   G_000E40_SE_BUSY(x)                          (((x) >> 20) & 0x1)
0767 #define   C_000E40_SE_BUSY                             0xFFEFFFFF
0768 #define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
0769 #define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
0770 #define   C_000E40_RE_BUSY                             0xFFDFFFFF
0771 #define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
0772 #define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
0773 #define   C_000E40_TAM_BUSY                            0xFFBFFFFF
0774 #define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
0775 #define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
0776 #define   C_000E40_TDM_BUSY                            0xFF7FFFFF
0777 #define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
0778 #define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
0779 #define   C_000E40_PB_BUSY                             0xFEFFFFFF
0780 #define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
0781 #define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
0782 #define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
0783 
0784 
0785 #define R_00000D_SCLK_CNTL                           0x00000D
0786 #define   S_00000D_SCLK_SRC_SEL(x)                     (((x) & 0x7) << 0)
0787 #define   G_00000D_SCLK_SRC_SEL(x)                     (((x) >> 0) & 0x7)
0788 #define   C_00000D_SCLK_SRC_SEL                        0xFFFFFFF8
0789 #define   S_00000D_TCLK_SRC_SEL(x)                     (((x) & 0x7) << 8)
0790 #define   G_00000D_TCLK_SRC_SEL(x)                     (((x) >> 8) & 0x7)
0791 #define   C_00000D_TCLK_SRC_SEL                        0xFFFFF8FF
0792 #define   S_00000D_FORCE_CP(x)                         (((x) & 0x1) << 16)
0793 #define   G_00000D_FORCE_CP(x)                         (((x) >> 16) & 0x1)
0794 #define   C_00000D_FORCE_CP                            0xFFFEFFFF
0795 #define   S_00000D_FORCE_HDP(x)                        (((x) & 0x1) << 17)
0796 #define   G_00000D_FORCE_HDP(x)                        (((x) >> 17) & 0x1)
0797 #define   C_00000D_FORCE_HDP                           0xFFFDFFFF
0798 #define   S_00000D_FORCE_DISP(x)                       (((x) & 0x1) << 18)
0799 #define   G_00000D_FORCE_DISP(x)                       (((x) >> 18) & 0x1)
0800 #define   C_00000D_FORCE_DISP                          0xFFFBFFFF
0801 #define   S_00000D_FORCE_TOP(x)                        (((x) & 0x1) << 19)
0802 #define   G_00000D_FORCE_TOP(x)                        (((x) >> 19) & 0x1)
0803 #define   C_00000D_FORCE_TOP                           0xFFF7FFFF
0804 #define   S_00000D_FORCE_E2(x)                         (((x) & 0x1) << 20)
0805 #define   G_00000D_FORCE_E2(x)                         (((x) >> 20) & 0x1)
0806 #define   C_00000D_FORCE_E2                            0xFFEFFFFF
0807 #define   S_00000D_FORCE_SE(x)                         (((x) & 0x1) << 21)
0808 #define   G_00000D_FORCE_SE(x)                         (((x) >> 21) & 0x1)
0809 #define   C_00000D_FORCE_SE                            0xFFDFFFFF
0810 #define   S_00000D_FORCE_IDCT(x)                       (((x) & 0x1) << 22)
0811 #define   G_00000D_FORCE_IDCT(x)                       (((x) >> 22) & 0x1)
0812 #define   C_00000D_FORCE_IDCT                          0xFFBFFFFF
0813 #define   S_00000D_FORCE_VIP(x)                        (((x) & 0x1) << 23)
0814 #define   G_00000D_FORCE_VIP(x)                        (((x) >> 23) & 0x1)
0815 #define   C_00000D_FORCE_VIP                           0xFF7FFFFF
0816 #define   S_00000D_FORCE_RE(x)                         (((x) & 0x1) << 24)
0817 #define   G_00000D_FORCE_RE(x)                         (((x) >> 24) & 0x1)
0818 #define   C_00000D_FORCE_RE                            0xFEFFFFFF
0819 #define   S_00000D_FORCE_PB(x)                         (((x) & 0x1) << 25)
0820 #define   G_00000D_FORCE_PB(x)                         (((x) >> 25) & 0x1)
0821 #define   C_00000D_FORCE_PB                            0xFDFFFFFF
0822 #define   S_00000D_FORCE_TAM(x)                        (((x) & 0x1) << 26)
0823 #define   G_00000D_FORCE_TAM(x)                        (((x) >> 26) & 0x1)
0824 #define   C_00000D_FORCE_TAM                           0xFBFFFFFF
0825 #define   S_00000D_FORCE_TDM(x)                        (((x) & 0x1) << 27)
0826 #define   G_00000D_FORCE_TDM(x)                        (((x) >> 27) & 0x1)
0827 #define   C_00000D_FORCE_TDM                           0xF7FFFFFF
0828 #define   S_00000D_FORCE_RB(x)                         (((x) & 0x1) << 28)
0829 #define   G_00000D_FORCE_RB(x)                         (((x) >> 28) & 0x1)
0830 #define   C_00000D_FORCE_RB                            0xEFFFFFFF
0831 
0832 /* PLL regs */
0833 #define SCLK_CNTL                                      0xd
0834 #define   FORCE_HDP                                    (1 << 17)
0835 #define CLK_PWRMGT_CNTL                                0x14
0836 #define   GLOBAL_PMAN_EN                               (1 << 10)
0837 #define   DISP_PM                                      (1 << 20)
0838 #define PLL_PWRMGT_CNTL                                0x15
0839 #define   MPLL_TURNOFF                                 (1 << 0)
0840 #define   SPLL_TURNOFF                                 (1 << 1)
0841 #define   PPLL_TURNOFF                                 (1 << 2)
0842 #define   P2PLL_TURNOFF                                (1 << 3)
0843 #define   TVPLL_TURNOFF                                (1 << 4)
0844 #define   MOBILE_SU                                    (1 << 16)
0845 #define   SU_SCLK_USE_BCLK                             (1 << 17)
0846 #define SCLK_CNTL2                                     0x1e
0847 #define   REDUCED_SPEED_SCLK_MODE                      (1 << 16)
0848 #define   REDUCED_SPEED_SCLK_SEL(x)                    ((x) << 17)
0849 #define MCLK_MISC                                      0x1f
0850 #define   EN_MCLK_TRISTATE_IN_SUSPEND                  (1 << 18)
0851 #define SCLK_MORE_CNTL                                 0x35
0852 #define   REDUCED_SPEED_SCLK_EN                        (1 << 16)
0853 #define   IO_CG_VOLTAGE_DROP                           (1 << 17)
0854 #define   VOLTAGE_DELAY_SEL(x)                         ((x) << 20)
0855 #define   VOLTAGE_DROP_SYNC                            (1 << 19)
0856 
0857 /* mmreg */
0858 #define DISP_PWR_MAN                                   0xd08
0859 #define   DISP_D3_GRPH_RST                             (1 << 18)
0860 #define   DISP_D3_SUBPIC_RST                           (1 << 19)
0861 #define   DISP_D3_OV0_RST                              (1 << 20)
0862 #define   DISP_D1D2_GRPH_RST                           (1 << 21)
0863 #define   DISP_D1D2_SUBPIC_RST                         (1 << 22)
0864 #define   DISP_D1D2_OV0_RST                            (1 << 23)
0865 #define   DISP_DVO_ENABLE_RST                          (1 << 24)
0866 #define   TV_ENABLE_RST                                (1 << 25)
0867 #define   AUTO_PWRUP_EN                                (1 << 26)
0868 
0869 #endif
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