drm/radeon/r100_track.h

0001 /* SPDX-License-Identifier: MIT */
0002
0003 #include "radeon.h"
0004
0005 #define R100_TRACK_MAX_TEXTURE 3
0006 #define R200_TRACK_MAX_TEXTURE 6
0007 #define R300_TRACK_MAX_TEXTURE 16
0008
0009 #define R100_MAX_CB 1
0010 #define R300_MAX_CB 4
0011
0012 /*
0013  * CS functions
0014  */
0015 struct r100_cs_track_cb {
0016     struct radeon_bo    *robj;
0017     unsigned        pitch;
0018     unsigned        cpp;
0019     unsigned        offset;
0020 };
0021
0022 struct r100_cs_track_array {
0023     struct radeon_bo    *robj;
0024     unsigned        esize;
0025 };
0026
0027 struct r100_cs_cube_info {
0028     struct radeon_bo    *robj;
0029     unsigned        offset;
0030     unsigned        width;
0031     unsigned        height;
0032 };
0033
0034 #define R100_TRACK_COMP_NONE   0
0035 #define R100_TRACK_COMP_DXT1   1
0036 #define R100_TRACK_COMP_DXT35  2
0037
0038 struct r100_cs_track_texture {
0039     struct radeon_bo    *robj;
0040     struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
0041     unsigned        pitch;
0042     unsigned        width;
0043     unsigned        height;
0044     unsigned        num_levels;
0045     unsigned        cpp;
0046     unsigned        tex_coord_type;
0047     unsigned        txdepth;
0048     unsigned        width_11;
0049     unsigned        height_11;
0050     bool            use_pitch;
0051     bool            enabled;
0052     bool                    lookup_disable;
0053     bool            roundup_w;
0054     bool            roundup_h;
0055     unsigned                compress_format;
0056 };
0057
0058 struct r100_cs_track {
0059     unsigned            num_cb;
0060     unsigned                        num_texture;
0061     unsigned            maxy;
0062     unsigned            vtx_size;
0063     unsigned            vap_vf_cntl;
0064     unsigned            vap_alt_nverts;
0065     unsigned            immd_dwords;
0066     unsigned            num_arrays;
0067     unsigned            max_indx;
0068     unsigned            color_channel_mask;
0069     struct r100_cs_track_array  arrays[16];
0070     struct r100_cs_track_cb     cb[R300_MAX_CB];
0071     struct r100_cs_track_cb     zb;
0072     struct r100_cs_track_cb     aa;
0073     struct r100_cs_track_texture    textures[R300_TRACK_MAX_TEXTURE];
0074     bool                z_enabled;
0075     bool                            separate_cube;
0076     bool                zb_cb_clear;
0077     bool                blend_read_enable;
0078     bool                cb_dirty;
0079     bool                zb_dirty;
0080     bool                tex_dirty;
0081     bool                aa_dirty;
0082     bool                aaresolve;
0083 };
0084
0085 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
0086 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
0087
0088 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
0089
0090 int r200_packet0_check(struct radeon_cs_parser *p,
0091                struct radeon_cs_packet *pkt,
0092                unsigned idx, unsigned reg);
0093
0094 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
0095                 struct radeon_cs_packet *pkt,
0096                 unsigned idx,
0097                 unsigned reg);
0098 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
0099                  struct radeon_cs_packet *pkt,
0100                  int idx);