drm/radeon/nislands_smc.h

0001 /*
0002  * Copyright 2012 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __NISLANDS_SMC_H__
0024 #define __NISLANDS_SMC_H__
0025
0026 #pragma pack(push, 1)
0027
0028 #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
0029
0030 struct PP_NIslands_Dpm2PerfLevel
0031 {
0032     uint8_t     MaxPS;
0033     uint8_t     TgtAct;
0034     uint8_t     MaxPS_StepInc;
0035     uint8_t     MaxPS_StepDec;
0036     uint8_t     PSST;
0037     uint8_t     NearTDPDec;
0038     uint8_t     AboveSafeInc;
0039     uint8_t     BelowSafeInc;
0040     uint8_t     PSDeltaLimit;
0041     uint8_t     PSDeltaWin;
0042     uint8_t     Reserved[6];
0043 };
0044
0045 typedef struct PP_NIslands_Dpm2PerfLevel PP_NIslands_Dpm2PerfLevel;
0046
0047 struct PP_NIslands_DPM2Parameters
0048 {
0049     uint32_t    TDPLimit;
0050     uint32_t    NearTDPLimit;
0051     uint32_t    SafePowerLimit;
0052     uint32_t    PowerBoostLimit;
0053 };
0054 typedef struct PP_NIslands_DPM2Parameters PP_NIslands_DPM2Parameters;
0055
0056 struct NISLANDS_SMC_SCLK_VALUE
0057 {
0058     uint32_t        vCG_SPLL_FUNC_CNTL;
0059     uint32_t        vCG_SPLL_FUNC_CNTL_2;
0060     uint32_t        vCG_SPLL_FUNC_CNTL_3;
0061     uint32_t        vCG_SPLL_FUNC_CNTL_4;
0062     uint32_t        vCG_SPLL_SPREAD_SPECTRUM;
0063     uint32_t        vCG_SPLL_SPREAD_SPECTRUM_2;
0064     uint32_t        sclk_value;
0065 };
0066
0067 typedef struct NISLANDS_SMC_SCLK_VALUE NISLANDS_SMC_SCLK_VALUE;
0068
0069 struct NISLANDS_SMC_MCLK_VALUE
0070 {
0071     uint32_t        vMPLL_FUNC_CNTL;
0072     uint32_t        vMPLL_FUNC_CNTL_1;
0073     uint32_t        vMPLL_FUNC_CNTL_2;
0074     uint32_t        vMPLL_AD_FUNC_CNTL;
0075     uint32_t        vMPLL_AD_FUNC_CNTL_2;
0076     uint32_t        vMPLL_DQ_FUNC_CNTL;
0077     uint32_t        vMPLL_DQ_FUNC_CNTL_2;
0078     uint32_t        vMCLK_PWRMGT_CNTL;
0079     uint32_t        vDLL_CNTL;
0080     uint32_t        vMPLL_SS;
0081     uint32_t        vMPLL_SS2;
0082     uint32_t        mclk_value;
0083 };
0084
0085 typedef struct NISLANDS_SMC_MCLK_VALUE NISLANDS_SMC_MCLK_VALUE;
0086
0087 struct NISLANDS_SMC_VOLTAGE_VALUE
0088 {
0089     uint16_t             value;
0090     uint8_t              index;
0091     uint8_t              padding;
0092 };
0093
0094 typedef struct NISLANDS_SMC_VOLTAGE_VALUE NISLANDS_SMC_VOLTAGE_VALUE;
0095
0096 struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL
0097 {
0098     uint8_t                     arbValue;
0099     uint8_t                     ACIndex;
0100     uint8_t                     displayWatermark;
0101     uint8_t                     gen2PCIE;
0102     uint8_t                     reserved1;
0103     uint8_t                     reserved2;
0104     uint8_t                     strobeMode;
0105     uint8_t                     mcFlags;
0106     uint32_t                    aT;
0107     uint32_t                    bSP;
0108     NISLANDS_SMC_SCLK_VALUE     sclk;
0109     NISLANDS_SMC_MCLK_VALUE     mclk;
0110     NISLANDS_SMC_VOLTAGE_VALUE  vddc;
0111     NISLANDS_SMC_VOLTAGE_VALUE  mvdd;
0112     NISLANDS_SMC_VOLTAGE_VALUE  vddci;
0113     NISLANDS_SMC_VOLTAGE_VALUE  std_vddc;
0114     uint32_t                    powergate_en;
0115     uint8_t                     hUp;
0116     uint8_t                     hDown;
0117     uint8_t                     stateFlags;
0118     uint8_t                     arbRefreshState;
0119     uint32_t                    SQPowerThrottle;
0120     uint32_t                    SQPowerThrottle_2;
0121     uint32_t                    reserved[2];
0122     PP_NIslands_Dpm2PerfLevel   dpm2;
0123 };
0124
0125 #define NISLANDS_SMC_STROBE_RATIO    0x0F
0126 #define NISLANDS_SMC_STROBE_ENABLE   0x10
0127
0128 #define NISLANDS_SMC_MC_EDC_RD_FLAG  0x01
0129 #define NISLANDS_SMC_MC_EDC_WR_FLAG  0x02
0130 #define NISLANDS_SMC_MC_RTT_ENABLE   0x04
0131 #define NISLANDS_SMC_MC_STUTTER_EN   0x08
0132
0133 typedef struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL NISLANDS_SMC_HW_PERFORMANCE_LEVEL;
0134
0135 struct NISLANDS_SMC_SWSTATE
0136 {
0137     uint8_t                             flags;
0138     uint8_t                             levelCount;
0139     uint8_t                             padding2;
0140     uint8_t                             padding3;
0141     NISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[];
0142 };
0143
0144 typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE;
0145
0146 struct NISLANDS_SMC_SWSTATE_SINGLE {
0147     uint8_t                             flags;
0148     uint8_t                             levelCount;
0149     uint8_t                             padding2;
0150     uint8_t                             padding3;
0151     NISLANDS_SMC_HW_PERFORMANCE_LEVEL   level;
0152 };
0153
0154 #define NISLANDS_SMC_VOLTAGEMASK_VDDC  0
0155 #define NISLANDS_SMC_VOLTAGEMASK_MVDD  1
0156 #define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2
0157 #define NISLANDS_SMC_VOLTAGEMASK_MAX   4
0158
0159 struct NISLANDS_SMC_VOLTAGEMASKTABLE
0160 {
0161     uint8_t  highMask[NISLANDS_SMC_VOLTAGEMASK_MAX];
0162     uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX];
0163 };
0164
0165 typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE;
0166
0167 #define NISLANDS_MAX_NO_VREG_STEPS 32
0168
0169 struct NISLANDS_SMC_STATETABLE
0170 {
0171     uint8_t                             thermalProtectType;
0172     uint8_t                             systemFlags;
0173     uint8_t                             maxVDDCIndexInPPTable;
0174     uint8_t                             extraFlags;
0175     uint8_t                             highSMIO[NISLANDS_MAX_NO_VREG_STEPS];
0176     uint32_t                            lowSMIO[NISLANDS_MAX_NO_VREG_STEPS];
0177     NISLANDS_SMC_VOLTAGEMASKTABLE       voltageMaskTable;
0178     PP_NIslands_DPM2Parameters          dpm2Params;
0179     struct NISLANDS_SMC_SWSTATE_SINGLE  initialState;
0180     struct NISLANDS_SMC_SWSTATE_SINGLE  ACPIState;
0181     struct NISLANDS_SMC_SWSTATE_SINGLE  ULVState;
0182     NISLANDS_SMC_SWSTATE                driverState;
0183     NISLANDS_SMC_HW_PERFORMANCE_LEVEL   dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
0184 };
0185
0186 typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE;
0187
0188 #define NI_SMC_SOFT_REGISTERS_START        0x108
0189
0190 #define NI_SMC_SOFT_REGISTER_mclk_chg_timeout        0x0
0191 #define NI_SMC_SOFT_REGISTER_delay_bbias             0xC
0192 #define NI_SMC_SOFT_REGISTER_delay_vreg              0x10
0193 #define NI_SMC_SOFT_REGISTER_delay_acpi              0x2C
0194 #define NI_SMC_SOFT_REGISTER_seq_index               0x64
0195 #define NI_SMC_SOFT_REGISTER_mvdd_chg_time           0x68
0196 #define NI_SMC_SOFT_REGISTER_mclk_switch_lim         0x78
0197 #define NI_SMC_SOFT_REGISTER_watermark_threshold     0x80
0198 #define NI_SMC_SOFT_REGISTER_mc_block_delay          0x84
0199 #define NI_SMC_SOFT_REGISTER_uvd_enabled             0x98
0200
0201 #define SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES 16
0202 #define SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
0203 #define SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
0204 #define SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES 4
0205
0206 struct SMC_NISLANDS_MC_TPP_CAC_TABLE
0207 {
0208     uint32_t    tpp[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES];
0209     uint32_t    cacValue[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES];
0210 };
0211
0212 typedef struct SMC_NISLANDS_MC_TPP_CAC_TABLE SMC_NISLANDS_MC_TPP_CAC_TABLE;
0213
0214
0215 struct PP_NIslands_CACTABLES
0216 {
0217     uint32_t                cac_bif_lut[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES];
0218     uint32_t                cac_lkge_lut[SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES];
0219
0220     uint32_t                pwr_const;
0221
0222     uint32_t                dc_cacValue;
0223     uint32_t                bif_cacValue;
0224     uint32_t                lkge_pwr;
0225
0226     uint8_t                 cac_width;
0227     uint8_t                 window_size_p2;
0228
0229     uint8_t                 num_drop_lsb;
0230     uint8_t                 padding_0;
0231
0232     uint32_t                last_power;
0233
0234     uint8_t                 AllowOvrflw;
0235     uint8_t                 MCWrWeight;
0236     uint8_t                 MCRdWeight;
0237     uint8_t                 padding_1[9];
0238
0239     uint8_t                 enableWinAvg;
0240     uint8_t                 numWin_TDP;
0241     uint8_t                 l2numWin_TDP;
0242     uint8_t                 WinIndex;
0243
0244     uint32_t                dynPwr_TDP[4];
0245     uint32_t                lkgePwr_TDP[4];
0246     uint32_t                power_TDP[4];
0247     uint32_t                avg_dynPwr_TDP;
0248     uint32_t                avg_lkgePwr_TDP;
0249     uint32_t                avg_power_TDP;
0250     uint32_t                lts_power_TDP;
0251     uint8_t                 lts_truncate_n;
0252     uint8_t                 padding_2[7];
0253 };
0254
0255 typedef struct PP_NIslands_CACTABLES PP_NIslands_CACTABLES;
0256
0257 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 32
0258 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
0259
0260 struct SMC_NIslands_MCRegisterAddress
0261 {
0262     uint16_t s0;
0263     uint16_t s1;
0264 };
0265
0266 typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress;
0267
0268
0269 struct SMC_NIslands_MCRegisterSet
0270 {
0271     uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
0272 };
0273
0274 typedef struct SMC_NIslands_MCRegisterSet SMC_NIslands_MCRegisterSet;
0275
0276 struct SMC_NIslands_MCRegisters
0277 {
0278     uint8_t                             last;
0279     uint8_t                             reserved[3];
0280     SMC_NIslands_MCRegisterAddress      address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
0281     SMC_NIslands_MCRegisterSet          data[SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT];
0282 };
0283
0284 typedef struct SMC_NIslands_MCRegisters SMC_NIslands_MCRegisters;
0285
0286 struct SMC_NIslands_MCArbDramTimingRegisterSet
0287 {
0288     uint32_t mc_arb_dram_timing;
0289     uint32_t mc_arb_dram_timing2;
0290     uint8_t  mc_arb_rfsh_rate;
0291     uint8_t  padding[3];
0292 };
0293
0294 typedef struct SMC_NIslands_MCArbDramTimingRegisterSet SMC_NIslands_MCArbDramTimingRegisterSet;
0295
0296 struct SMC_NIslands_MCArbDramTimingRegisters
0297 {
0298     uint8_t                                     arb_current;
0299     uint8_t                                     reserved[3];
0300     SMC_NIslands_MCArbDramTimingRegisterSet     data[20];
0301 };
0302
0303 typedef struct SMC_NIslands_MCArbDramTimingRegisters SMC_NIslands_MCArbDramTimingRegisters;
0304
0305 struct SMC_NISLANDS_SPLL_DIV_TABLE
0306 {
0307     uint32_t    freq[256];
0308     uint32_t    ss[256];
0309 };
0310
0311 #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK  0x01ffffff
0312 #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0
0313 #define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK   0xfe000000
0314 #define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT  25
0315 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK   0x000fffff
0316 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT  0
0317 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK   0xfff00000
0318 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT  20
0319
0320 typedef struct SMC_NISLANDS_SPLL_DIV_TABLE SMC_NISLANDS_SPLL_DIV_TABLE;
0321
0322 #define NISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x100
0323
0324 #define NISLANDS_SMC_FIRMWARE_HEADER_version                   0x0
0325 #define NISLANDS_SMC_FIRMWARE_HEADER_flags                     0x4
0326 #define NISLANDS_SMC_FIRMWARE_HEADER_softRegisters             0x8
0327 #define NISLANDS_SMC_FIRMWARE_HEADER_stateTable                0xC
0328 #define NISLANDS_SMC_FIRMWARE_HEADER_fanTable                  0x10
0329 #define NISLANDS_SMC_FIRMWARE_HEADER_cacTable                  0x14
0330 #define NISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable           0x20
0331 #define NISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x2C
0332 #define NISLANDS_SMC_FIRMWARE_HEADER_spllTable                 0x30
0333
0334 #pragma pack(pop)
0335
0336 #endif
0337