drm/radeon/ni_dpm.h

0001 /*
0002  * Copyright 2012 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __NI_DPM_H__
0024 #define __NI_DPM_H__
0025
0026 #include "cypress_dpm.h"
0027 #include "btc_dpm.h"
0028 #include "nislands_smc.h"
0029
0030 struct ni_clock_registers {
0031     u32 cg_spll_func_cntl;
0032     u32 cg_spll_func_cntl_2;
0033     u32 cg_spll_func_cntl_3;
0034     u32 cg_spll_func_cntl_4;
0035     u32 cg_spll_spread_spectrum;
0036     u32 cg_spll_spread_spectrum_2;
0037     u32 mclk_pwrmgt_cntl;
0038     u32 dll_cntl;
0039     u32 mpll_ad_func_cntl;
0040     u32 mpll_ad_func_cntl_2;
0041     u32 mpll_dq_func_cntl;
0042     u32 mpll_dq_func_cntl_2;
0043     u32 mpll_ss1;
0044     u32 mpll_ss2;
0045 };
0046
0047 struct ni_mc_reg_entry {
0048     u32 mclk_max;
0049     u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
0050 };
0051
0052 struct ni_mc_reg_table {
0053     u8 last;
0054     u8 num_entries;
0055     u16 valid_flag;
0056     struct ni_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
0057     SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
0058 };
0059
0060 #define NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 2
0061
0062 enum ni_dc_cac_level
0063 {
0064     NISLANDS_DCCAC_LEVEL_0 = 0,
0065     NISLANDS_DCCAC_LEVEL_1,
0066     NISLANDS_DCCAC_LEVEL_2,
0067     NISLANDS_DCCAC_LEVEL_3,
0068     NISLANDS_DCCAC_LEVEL_4,
0069     NISLANDS_DCCAC_LEVEL_5,
0070     NISLANDS_DCCAC_LEVEL_6,
0071     NISLANDS_DCCAC_LEVEL_7,
0072     NISLANDS_DCCAC_MAX_LEVELS
0073 };
0074
0075 struct ni_leakage_coeffients
0076 {
0077     u32 at;
0078     u32 bt;
0079     u32 av;
0080     u32 bv;
0081     s32 t_slope;
0082     s32 t_intercept;
0083     u32 t_ref;
0084 };
0085
0086 struct ni_cac_data
0087 {
0088     struct ni_leakage_coeffients leakage_coefficients;
0089     u32 i_leakage;
0090     s32 leakage_minimum_temperature;
0091     u32 pwr_const;
0092     u32 dc_cac_value;
0093     u32 bif_cac_value;
0094     u32 lkge_pwr;
0095     u8 mc_wr_weight;
0096     u8 mc_rd_weight;
0097     u8 allow_ovrflw;
0098     u8 num_win_tdp;
0099     u8 l2num_win_tdp;
0100     u8 lts_truncate_n;
0101 };
0102
0103 struct ni_cac_weights
0104 {
0105     u32 weight_tcp_sig0;
0106     u32 weight_tcp_sig1;
0107     u32 weight_ta_sig;
0108     u32 weight_tcc_en0;
0109     u32 weight_tcc_en1;
0110     u32 weight_tcc_en2;
0111     u32 weight_cb_en0;
0112     u32 weight_cb_en1;
0113     u32 weight_cb_en2;
0114     u32 weight_cb_en3;
0115     u32 weight_db_sig0;
0116     u32 weight_db_sig1;
0117     u32 weight_db_sig2;
0118     u32 weight_db_sig3;
0119     u32 weight_sxm_sig0;
0120     u32 weight_sxm_sig1;
0121     u32 weight_sxm_sig2;
0122     u32 weight_sxs_sig0;
0123     u32 weight_sxs_sig1;
0124     u32 weight_xbr_0;
0125     u32 weight_xbr_1;
0126     u32 weight_xbr_2;
0127     u32 weight_spi_sig0;
0128     u32 weight_spi_sig1;
0129     u32 weight_spi_sig2;
0130     u32 weight_spi_sig3;
0131     u32 weight_spi_sig4;
0132     u32 weight_spi_sig5;
0133     u32 weight_lds_sig0;
0134     u32 weight_lds_sig1;
0135     u32 weight_sc;
0136     u32 weight_bif;
0137     u32 weight_cp;
0138     u32 weight_pa_sig0;
0139     u32 weight_pa_sig1;
0140     u32 weight_vgt_sig0;
0141     u32 weight_vgt_sig1;
0142     u32 weight_vgt_sig2;
0143     u32 weight_dc_sig0;
0144     u32 weight_dc_sig1;
0145     u32 weight_dc_sig2;
0146     u32 weight_dc_sig3;
0147     u32 weight_uvd_sig0;
0148     u32 weight_uvd_sig1;
0149     u32 weight_spare0;
0150     u32 weight_spare1;
0151     u32 weight_sq_vsp;
0152     u32 weight_sq_vsp0;
0153     u32 weight_sq_gpr;
0154     u32 ovr_mode_spare_0;
0155     u32 ovr_val_spare_0;
0156     u32 ovr_mode_spare_1;
0157     u32 ovr_val_spare_1;
0158     u32 vsp;
0159     u32 vsp0;
0160     u32 gpr;
0161     u8 mc_read_weight;
0162     u8 mc_write_weight;
0163     u32 tid_cnt;
0164     u32 tid_unit;
0165     u32 l2_lta_window_size;
0166     u32 lts_truncate;
0167     u32 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];
0168     u32 pcie_cac[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES];
0169     bool enable_power_containment_by_default;
0170 };
0171
0172 struct ni_ps {
0173     u16 performance_level_count;
0174     bool dc_compatible;
0175     struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
0176 };
0177
0178 struct ni_power_info {
0179     /* must be first! */
0180     struct evergreen_power_info eg;
0181     struct ni_clock_registers clock_registers;
0182     struct ni_mc_reg_table mc_reg_table;
0183     u32 mclk_rtt_mode_threshold;
0184     /* flags */
0185     bool use_power_boost_limit;
0186     bool support_cac_long_term_average;
0187     bool cac_enabled;
0188     bool cac_configuration_required;
0189     bool driver_calculate_cac_leakage;
0190     bool pc_enabled;
0191     bool enable_power_containment;
0192     bool enable_cac;
0193     bool enable_sq_ramping;
0194     /* smc offsets */
0195     u16 arb_table_start;
0196     u16 fan_table_start;
0197     u16 cac_table_start;
0198     u16 spll_table_start;
0199     /* CAC stuff */
0200     struct ni_cac_data cac_data;
0201     u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS];
0202     const struct ni_cac_weights *cac_weights;
0203     u8 lta_window_size;
0204     u8 lts_truncate;
0205     struct ni_ps current_ps;
0206     struct ni_ps requested_ps;
0207     /* scratch structs */
0208     SMC_NIslands_MCRegisters smc_mc_reg_table;
0209     NISLANDS_SMC_STATETABLE smc_statetable;
0210 };
0211
0212 #define NISLANDS_INITIAL_STATE_ARB_INDEX    0
0213 #define NISLANDS_ACPI_STATE_ARB_INDEX       1
0214 #define NISLANDS_ULV_STATE_ARB_INDEX        2
0215 #define NISLANDS_DRIVER_STATE_ARB_INDEX     3
0216
0217 #define NISLANDS_DPM2_MAX_PULSE_SKIP        256
0218
0219 #define NISLANDS_DPM2_NEAR_TDP_DEC          10
0220 #define NISLANDS_DPM2_ABOVE_SAFE_INC        5
0221 #define NISLANDS_DPM2_BELOW_SAFE_INC        20
0222
0223 #define NISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT            80
0224
0225 #define NISLANDS_DPM2_MAXPS_PERCENT_H                   90
0226 #define NISLANDS_DPM2_MAXPS_PERCENT_M                   0
0227
0228 #define NISLANDS_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
0229 #define NISLANDS_DPM2_SQ_RAMP_MIN_POWER                 0x12
0230 #define NISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
0231 #define NISLANDS_DPM2_SQ_RAMP_STI_SIZE                  0x1E
0232 #define NISLANDS_DPM2_SQ_RAMP_LTI_RATIO                 0xF
0233
0234 int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
0235                 u32 arb_freq_src, u32 arb_freq_dest);
0236 void ni_update_current_ps(struct radeon_device *rdev,
0237               struct radeon_ps *rps);
0238 void ni_update_requested_ps(struct radeon_device *rdev,
0239                 struct radeon_ps *rps);
0240
0241 void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
0242                        struct radeon_ps *new_ps,
0243                        struct radeon_ps *old_ps);
0244 void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
0245                       struct radeon_ps *new_ps,
0246                       struct radeon_ps *old_ps);
0247
0248 bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
0249
0250 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
0251 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
0252
0253 #endif