drm/radeon/kv_dpm.h

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __KV_DPM_H__
0024 #define __KV_DPM_H__
0025
0026 #define SMU__NUM_SCLK_DPM_STATE  8
0027 #define SMU__NUM_MCLK_DPM_LEVELS 4
0028 #define SMU__NUM_LCLK_DPM_LEVELS 8
0029 #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */
0030 #include "smu7_fusion.h"
0031 #include "trinity_dpm.h"
0032 #include "ppsmc.h"
0033
0034 #define KV_NUM_NBPSTATES   4
0035
0036 enum kv_pt_config_reg_type {
0037     KV_CONFIGREG_MMR = 0,
0038     KV_CONFIGREG_SMC_IND,
0039     KV_CONFIGREG_DIDT_IND,
0040     KV_CONFIGREG_CACHE,
0041     KV_CONFIGREG_MAX
0042 };
0043
0044 struct kv_pt_config_reg {
0045     u32 offset;
0046     u32 mask;
0047     u32 shift;
0048     u32 value;
0049     enum kv_pt_config_reg_type type;
0050 };
0051
0052 struct kv_lcac_config_values {
0053     u32 block_id;
0054     u32 signal_id;
0055     u32 t;
0056 };
0057
0058 struct kv_lcac_config_reg {
0059     u32 cntl;
0060     u32 block_mask;
0061     u32 block_shift;
0062     u32 signal_mask;
0063     u32 signal_shift;
0064     u32 t_mask;
0065     u32 t_shift;
0066     u32 enable_mask;
0067     u32 enable_shift;
0068 };
0069
0070 struct kv_pl {
0071     u32 sclk;
0072     u8 vddc_index;
0073     u8 ds_divider_index;
0074     u8 ss_divider_index;
0075     u8 allow_gnb_slow;
0076     u8 force_nbp_state;
0077     u8 display_wm;
0078     u8 vce_wm;
0079 };
0080
0081 struct kv_ps {
0082     struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
0083     u32 num_levels;
0084     bool need_dfs_bypass;
0085     u8 dpm0_pg_nb_ps_lo;
0086     u8 dpm0_pg_nb_ps_hi;
0087     u8 dpmx_nb_ps_lo;
0088     u8 dpmx_nb_ps_hi;
0089 };
0090
0091 struct kv_sys_info {
0092     u32 bootup_uma_clk;
0093     u32 bootup_sclk;
0094     u32 dentist_vco_freq;
0095     u32 nb_dpm_enable;
0096     u32 nbp_memory_clock[KV_NUM_NBPSTATES];
0097     u32 nbp_n_clock[KV_NUM_NBPSTATES];
0098     u16 bootup_nb_voltage_index;
0099     u8 htc_tmp_lmt;
0100     u8 htc_hyst_lmt;
0101     struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
0102     struct sumo_vid_mapping_table vid_mapping_table;
0103     u32 uma_channel_number;
0104 };
0105
0106 struct kv_power_info {
0107     u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];
0108     u32 voltage_drop_t;
0109     struct kv_sys_info sys_info;
0110     struct kv_pl boot_pl;
0111     bool enable_nb_ps_policy;
0112     bool disable_nb_ps3_in_battery;
0113     bool video_start;
0114     bool battery_state;
0115     u32 lowest_valid;
0116     u32 highest_valid;
0117     u16 high_voltage_t;
0118     bool cac_enabled;
0119     bool bapm_enable;
0120     /* smc offsets */
0121     u32 sram_end;
0122     u32 dpm_table_start;
0123     u32 soft_regs_start;
0124     /* dpm SMU tables */
0125     u8 graphics_dpm_level_count;
0126     u8 uvd_level_count;
0127     u8 vce_level_count;
0128     u8 acp_level_count;
0129     u8 samu_level_count;
0130     u16 fps_high_t;
0131     SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
0132     SMU7_Fusion_ACPILevel acpi_level;
0133     SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD];
0134     SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE];
0135     SMU7_Fusion_ExtClkLevel acp_level[SMU7_MAX_LEVELS_ACP];
0136     SMU7_Fusion_ExtClkLevel samu_level[SMU7_MAX_LEVELS_SAMU];
0137     u8 uvd_boot_level;
0138     u8 vce_boot_level;
0139     u8 acp_boot_level;
0140     u8 samu_boot_level;
0141     u8 uvd_interval;
0142     u8 vce_interval;
0143     u8 acp_interval;
0144     u8 samu_interval;
0145     u8 graphics_boot_level;
0146     u8 graphics_interval;
0147     u8 graphics_therm_throttle_enable;
0148     u8 graphics_voltage_change_enable;
0149     u8 graphics_clk_slow_enable;
0150     u8 graphics_clk_slow_divider;
0151     u8 fps_low_t;
0152     u32 low_sclk_interrupt_t;
0153     bool uvd_power_gated;
0154     bool vce_power_gated;
0155     bool acp_power_gated;
0156     bool samu_power_gated;
0157     bool nb_dpm_enabled;
0158     /* flags */
0159     bool enable_didt;
0160     bool enable_dpm;
0161     bool enable_auto_thermal_throttling;
0162     bool enable_nb_dpm;
0163     /* caps */
0164     bool caps_cac;
0165     bool caps_power_containment;
0166     bool caps_sq_ramping;
0167     bool caps_db_ramping;
0168     bool caps_td_ramping;
0169     bool caps_tcp_ramping;
0170     bool caps_sclk_throttle_low_notification;
0171     bool caps_fps;
0172     bool caps_uvd_dpm;
0173     bool caps_uvd_pg;
0174     bool caps_vce_pg;
0175     bool caps_samu_pg;
0176     bool caps_acp_pg;
0177     bool caps_stable_p_state;
0178     bool caps_enable_dfs_bypass;
0179     bool caps_sclk_ds;
0180     struct radeon_ps current_rps;
0181     struct kv_ps current_ps;
0182     struct radeon_ps requested_rps;
0183     struct kv_ps requested_ps;
0184 };
0185
0186
0187 /* kv_smc.c */
0188 int kv_notify_message_to_smu(struct radeon_device *rdev, u32 id);
0189 int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask);
0190 int kv_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
0191                       PPSMC_Msg msg, u32 parameter);
0192 int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
0193                u32 *value, u32 limit);
0194 int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable);
0195 int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable);
0196 int kv_copy_bytes_to_smc(struct radeon_device *rdev,
0197              u32 smc_start_address,
0198              const u8 *src, u32 byte_count, u32 limit);
0199
0200 #endif