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0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Christian König.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Christian König
0025  *          Rafał Miłecki
0026  */
0027 #include <linux/hdmi.h>
0028 
0029 #include <drm/radeon_drm.h>
0030 #include "evergreen_hdmi.h"
0031 #include "radeon.h"
0032 #include "radeon_asic.h"
0033 #include "radeon_audio.h"
0034 #include "evergreend.h"
0035 #include "atom.h"
0036 
0037 /* enable the audio stream */
0038 void dce4_audio_enable(struct radeon_device *rdev,
0039                   struct r600_audio_pin *pin,
0040                   u8 enable_mask)
0041 {
0042     u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
0043 
0044     if (!pin)
0045         return;
0046 
0047     if (enable_mask) {
0048         tmp |= AUDIO_ENABLED;
0049         if (enable_mask & 1)
0050             tmp |= PIN0_AUDIO_ENABLED;
0051         if (enable_mask & 2)
0052             tmp |= PIN1_AUDIO_ENABLED;
0053         if (enable_mask & 4)
0054             tmp |= PIN2_AUDIO_ENABLED;
0055         if (enable_mask & 8)
0056             tmp |= PIN3_AUDIO_ENABLED;
0057     } else {
0058         tmp &= ~(AUDIO_ENABLED |
0059              PIN0_AUDIO_ENABLED |
0060              PIN1_AUDIO_ENABLED |
0061              PIN2_AUDIO_ENABLED |
0062              PIN3_AUDIO_ENABLED);
0063     }
0064 
0065     WREG32(AZ_HOT_PLUG_CONTROL, tmp);
0066 }
0067 
0068 void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
0069     const struct radeon_hdmi_acr *acr)
0070 {
0071     struct drm_device *dev = encoder->dev;
0072     struct radeon_device *rdev = dev->dev_private;
0073     int bpc = 8;
0074 
0075     if (encoder->crtc) {
0076         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
0077         bpc = radeon_crtc->bpc;
0078     }
0079 
0080     if (bpc > 8)
0081         WREG32(HDMI_ACR_PACKET_CONTROL + offset,
0082             HDMI_ACR_AUTO_SEND);    /* allow hw to sent ACR packets when required */
0083     else
0084         WREG32(HDMI_ACR_PACKET_CONTROL + offset,
0085             HDMI_ACR_SOURCE |       /* select SW CTS value */
0086             HDMI_ACR_AUTO_SEND);    /* allow hw to sent ACR packets when required */
0087 
0088     WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
0089     WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);
0090 
0091     WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));
0092     WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);
0093 
0094     WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));
0095     WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);
0096 }
0097 
0098 void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
0099         struct drm_connector *connector, struct drm_display_mode *mode)
0100 {
0101     struct radeon_device *rdev = encoder->dev->dev_private;
0102     u32 tmp = 0;
0103 
0104     if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
0105         if (connector->latency_present[1])
0106             tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
0107                 AUDIO_LIPSYNC(connector->audio_latency[1]);
0108         else
0109             tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
0110     } else {
0111         if (connector->latency_present[0])
0112             tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
0113                 AUDIO_LIPSYNC(connector->audio_latency[0]);
0114         else
0115             tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
0116     }
0117     WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
0118 }
0119 
0120 void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
0121     u8 *sadb, int sad_count)
0122 {
0123     struct radeon_device *rdev = encoder->dev->dev_private;
0124     u32 tmp;
0125 
0126     /* program the speaker allocation */
0127     tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
0128     tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
0129     /* set HDMI mode */
0130     tmp |= HDMI_CONNECTION;
0131     if (sad_count)
0132         tmp |= SPEAKER_ALLOCATION(sadb[0]);
0133     else
0134         tmp |= SPEAKER_ALLOCATION(5); /* stereo */
0135     WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
0136 }
0137 
0138 void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
0139     u8 *sadb, int sad_count)
0140 {
0141     struct radeon_device *rdev = encoder->dev->dev_private;
0142     u32 tmp;
0143 
0144     /* program the speaker allocation */
0145     tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
0146     tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
0147     /* set DP mode */
0148     tmp |= DP_CONNECTION;
0149     if (sad_count)
0150         tmp |= SPEAKER_ALLOCATION(sadb[0]);
0151     else
0152         tmp |= SPEAKER_ALLOCATION(5); /* stereo */
0153     WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
0154 }
0155 
0156 void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
0157     struct cea_sad *sads, int sad_count)
0158 {
0159     int i;
0160     struct radeon_device *rdev = encoder->dev->dev_private;
0161     static const u16 eld_reg_to_type[][2] = {
0162         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
0163         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
0164         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
0165         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
0166         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
0167         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
0168         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
0169         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
0170         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
0171         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
0172         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
0173         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
0174     };
0175 
0176     for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
0177         u32 value = 0;
0178         u8 stereo_freqs = 0;
0179         int max_channels = -1;
0180         int j;
0181 
0182         for (j = 0; j < sad_count; j++) {
0183             struct cea_sad *sad = &sads[j];
0184 
0185             if (sad->format == eld_reg_to_type[i][1]) {
0186                 if (sad->channels > max_channels) {
0187                     value = MAX_CHANNELS(sad->channels) |
0188                         DESCRIPTOR_BYTE_2(sad->byte2) |
0189                         SUPPORTED_FREQUENCIES(sad->freq);
0190                     max_channels = sad->channels;
0191                 }
0192 
0193                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
0194                     stereo_freqs |= sad->freq;
0195                 else
0196                     break;
0197             }
0198         }
0199 
0200         value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
0201 
0202         WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
0203     }
0204 }
0205 
0206 /*
0207  * build a AVI Info Frame
0208  */
0209 void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,
0210                   unsigned char *buffer, size_t size)
0211 {
0212     uint8_t *frame = buffer + 3;
0213 
0214     WREG32(AFMT_AVI_INFO0 + offset,
0215         frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
0216     WREG32(AFMT_AVI_INFO1 + offset,
0217         frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
0218     WREG32(AFMT_AVI_INFO2 + offset,
0219         frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
0220     WREG32(AFMT_AVI_INFO3 + offset,
0221         frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));
0222 
0223     WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
0224          HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
0225          ~HDMI_AVI_INFO_LINE_MASK);
0226 }
0227 
0228 void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
0229     struct radeon_crtc *crtc, unsigned int clock)
0230 {
0231     unsigned int max_ratio = clock / 24000;
0232     u32 dto_phase;
0233     u32 wallclock_ratio;
0234     u32 value;
0235 
0236     if (max_ratio >= 8) {
0237         dto_phase = 192 * 1000;
0238         wallclock_ratio = 3;
0239     } else if (max_ratio >= 4) {
0240         dto_phase = 96 * 1000;
0241         wallclock_ratio = 2;
0242     } else if (max_ratio >= 2) {
0243         dto_phase = 48 * 1000;
0244         wallclock_ratio = 1;
0245     } else {
0246         dto_phase = 24 * 1000;
0247         wallclock_ratio = 0;
0248     }
0249 
0250     value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
0251     value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
0252     value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO;
0253     WREG32(DCCG_AUDIO_DTO0_CNTL, value);
0254 
0255     /* Two dtos; generally use dto0 for HDMI */
0256     value = 0;
0257 
0258     if (crtc)
0259         value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
0260 
0261     WREG32(DCCG_AUDIO_DTO_SOURCE, value);
0262 
0263     /* Express [24MHz / target pixel clock] as an exact rational
0264      * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
0265      * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
0266      */
0267     WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
0268     WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
0269 }
0270 
0271 void dce4_dp_audio_set_dto(struct radeon_device *rdev,
0272                struct radeon_crtc *crtc, unsigned int clock)
0273 {
0274     u32 value;
0275 
0276     value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
0277     value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO;
0278     WREG32(DCCG_AUDIO_DTO1_CNTL, value);
0279 
0280     /* Two dtos; generally use dto1 for DP */
0281     value = 0;
0282     value |= DCCG_AUDIO_DTO_SEL;
0283 
0284     if (crtc)
0285         value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
0286 
0287     WREG32(DCCG_AUDIO_DTO_SOURCE, value);
0288 
0289     /* Express [24MHz / target pixel clock] as an exact rational
0290      * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
0291      * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
0292      */
0293     if (ASIC_IS_DCE41(rdev)) {
0294         unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) &
0295             DENTIST_DPREFCLK_WDIVIDER_MASK) >>
0296             DENTIST_DPREFCLK_WDIVIDER_SHIFT;
0297         div = radeon_audio_decode_dfs_div(div);
0298 
0299         if (div)
0300             clock = 100 * clock / div;
0301     }
0302 
0303     WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
0304     WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
0305 }
0306 
0307 void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
0308 {
0309     struct drm_device *dev = encoder->dev;
0310     struct radeon_device *rdev = dev->dev_private;
0311 
0312     WREG32(HDMI_VBI_PACKET_CONTROL + offset,
0313         HDMI_NULL_SEND |    /* send null packets when required */
0314         HDMI_GC_SEND |      /* send general control packets */
0315         HDMI_GC_CONT);      /* send general control packets every frame */
0316 }
0317 
0318 void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc)
0319 {
0320     struct drm_device *dev = encoder->dev;
0321     struct radeon_device *rdev = dev->dev_private;
0322     struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
0323     uint32_t val;
0324 
0325     val = RREG32(HDMI_CONTROL + offset);
0326     val &= ~HDMI_DEEP_COLOR_ENABLE;
0327     val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;
0328 
0329     switch (bpc) {
0330         case 0:
0331         case 6:
0332         case 8:
0333         case 16:
0334         default:
0335             DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
0336                      connector->name, bpc);
0337             break;
0338         case 10:
0339             val |= HDMI_DEEP_COLOR_ENABLE;
0340             val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
0341             DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
0342                      connector->name);
0343             break;
0344         case 12:
0345             val |= HDMI_DEEP_COLOR_ENABLE;
0346             val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
0347             DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
0348                      connector->name);
0349             break;
0350     }
0351 
0352     WREG32(HDMI_CONTROL + offset, val);
0353 }
0354 
0355 void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset)
0356 {
0357     struct drm_device *dev = encoder->dev;
0358     struct radeon_device *rdev = dev->dev_private;
0359 
0360     WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
0361         AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
0362 
0363     WREG32(AFMT_60958_0 + offset,
0364         AFMT_60958_CS_CHANNEL_NUMBER_L(1));
0365 
0366     WREG32(AFMT_60958_1 + offset,
0367         AFMT_60958_CS_CHANNEL_NUMBER_R(2));
0368 
0369     WREG32(AFMT_60958_2 + offset,
0370         AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
0371         AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
0372         AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
0373         AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
0374         AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
0375         AFMT_60958_CS_CHANNEL_NUMBER_7(8));
0376 
0377     WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
0378         AFMT_AUDIO_CHANNEL_ENABLE(0xff));
0379 
0380     WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
0381            HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
0382            HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
0383 
0384     /* allow 60958 channel status and send audio packets fields to be updated */
0385     WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
0386           AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE);
0387 }
0388 
0389 
0390 void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
0391 {
0392     struct drm_device *dev = encoder->dev;
0393     struct radeon_device *rdev = dev->dev_private;
0394 
0395     if (mute)
0396         WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE);
0397     else
0398         WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE);
0399 }
0400 
0401 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
0402 {
0403     struct drm_device *dev = encoder->dev;
0404     struct radeon_device *rdev = dev->dev_private;
0405     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0406     struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
0407 
0408     if (!dig || !dig->afmt)
0409         return;
0410 
0411     if (enable) {
0412         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
0413 
0414         if (connector && drm_detect_monitor_audio(radeon_connector_edid(connector))) {
0415             WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
0416                    HDMI_AVI_INFO_SEND | /* enable AVI info frames */
0417                    HDMI_AVI_INFO_CONT | /* required for audio info values to be updated */
0418                    HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
0419                    HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
0420             WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
0421                   AFMT_AUDIO_SAMPLE_SEND);
0422         } else {
0423             WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
0424                    HDMI_AVI_INFO_SEND | /* enable AVI info frames */
0425                    HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
0426             WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
0427                    ~AFMT_AUDIO_SAMPLE_SEND);
0428         }
0429     } else {
0430         WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
0431                ~AFMT_AUDIO_SAMPLE_SEND);
0432         WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);
0433     }
0434 
0435     dig->afmt->enabled = enable;
0436 
0437     DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
0438           enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
0439 }
0440 
0441 void evergreen_dp_enable(struct drm_encoder *encoder, bool enable)
0442 {
0443     struct drm_device *dev = encoder->dev;
0444     struct radeon_device *rdev = dev->dev_private;
0445     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0446     struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
0447     struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
0448 
0449     if (!dig || !dig->afmt)
0450         return;
0451 
0452     if (enable && connector &&
0453         drm_detect_monitor_audio(radeon_connector_edid(connector))) {
0454         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
0455         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
0456         struct radeon_connector_atom_dig *dig_connector;
0457         uint32_t val;
0458 
0459         WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
0460               AFMT_AUDIO_SAMPLE_SEND);
0461 
0462         WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,
0463                EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));
0464 
0465         if (!ASIC_IS_DCE6(rdev) && radeon_connector->con_priv) {
0466             dig_connector = radeon_connector->con_priv;
0467             val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);
0468             val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf);
0469 
0470             if (dig_connector->dp_clock == 162000)
0471                 val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3);
0472             else
0473                 val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5);
0474 
0475             WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val);
0476         }
0477 
0478         WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,
0479             EVERGREEN_DP_SEC_ASP_ENABLE |       /* Audio packet transmission */
0480             EVERGREEN_DP_SEC_ATP_ENABLE |       /* Audio timestamp packet transmission */
0481             EVERGREEN_DP_SEC_AIP_ENABLE |       /* Audio infoframe packet transmission */
0482             EVERGREEN_DP_SEC_STREAM_ENABLE);    /* Master enable for secondary stream engine */
0483     } else {
0484         WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);
0485         WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
0486                ~AFMT_AUDIO_SAMPLE_SEND);
0487     }
0488 
0489     dig->afmt->enabled = enable;
0490 }
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