drm/radeon/dce6_afmt.c

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include <linux/hdmi.h>
0024
0025 #include "dce6_afmt.h"
0026 #include "radeon.h"
0027 #include "radeon_audio.h"
0028 #include "sid.h"
0029
0030 #define DCE8_DCCG_AUDIO_DTO1_PHASE  0x05b8
0031 #define DCE8_DCCG_AUDIO_DTO1_MODULE 0x05bc
0032
0033 u32 dce6_endpoint_rreg(struct radeon_device *rdev,
0034                   u32 block_offset, u32 reg)
0035 {
0036     unsigned long flags;
0037     u32 r;
0038
0039     spin_lock_irqsave(&rdev->end_idx_lock, flags);
0040     WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
0041     r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
0042     spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
0043
0044     return r;
0045 }
0046
0047 void dce6_endpoint_wreg(struct radeon_device *rdev,
0048                    u32 block_offset, u32 reg, u32 v)
0049 {
0050     unsigned long flags;
0051
0052     spin_lock_irqsave(&rdev->end_idx_lock, flags);
0053     if (ASIC_IS_DCE8(rdev))
0054         WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
0055     else
0056         WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
0057                AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
0058     WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
0059     spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
0060 }
0061
0062 static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
0063 {
0064     int i;
0065     u32 offset, tmp;
0066
0067     for (i = 0; i < rdev->audio.num_pins; i++) {
0068         offset = rdev->audio.pin[i].offset;
0069         tmp = RREG32_ENDPOINT(offset,
0070                       AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
0071         if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
0072             rdev->audio.pin[i].connected = false;
0073         else
0074             rdev->audio.pin[i].connected = true;
0075     }
0076 }
0077
0078 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev)
0079 {
0080     struct drm_encoder *encoder;
0081     struct radeon_encoder *radeon_encoder;
0082     struct radeon_encoder_atom_dig *dig;
0083     struct r600_audio_pin *pin = NULL;
0084     int i, pin_count;
0085
0086     dce6_afmt_get_connected_pins(rdev);
0087
0088     for (i = 0; i < rdev->audio.num_pins; i++) {
0089         if (rdev->audio.pin[i].connected) {
0090             pin = &rdev->audio.pin[i];
0091             pin_count = 0;
0092
0093             list_for_each_entry(encoder, &rdev->ddev->mode_config.encoder_list, head) {
0094                 if (radeon_encoder_is_digital(encoder)) {
0095                     radeon_encoder = to_radeon_encoder(encoder);
0096                     dig = radeon_encoder->enc_priv;
0097                     if (dig->pin == pin)
0098                         pin_count++;
0099                 }
0100             }
0101
0102             if (pin_count == 0)
0103                 return pin;
0104         }
0105     }
0106     if (!pin)
0107         DRM_ERROR("No connected audio pins found!\n");
0108     return pin;
0109 }
0110
0111 void dce6_afmt_select_pin(struct drm_encoder *encoder)
0112 {
0113     struct radeon_device *rdev = encoder->dev->dev_private;
0114     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0115     struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
0116
0117     if (!dig || !dig->afmt || !dig->pin)
0118         return;
0119
0120     WREG32(AFMT_AUDIO_SRC_CONTROL +  dig->afmt->offset,
0121            AFMT_AUDIO_SRC_SELECT(dig->pin->id));
0122 }
0123
0124 void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
0125                     struct drm_connector *connector,
0126                     struct drm_display_mode *mode)
0127 {
0128     struct radeon_device *rdev = encoder->dev->dev_private;
0129     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0130     struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
0131     u32 tmp = 0;
0132
0133     if (!dig || !dig->afmt || !dig->pin)
0134         return;
0135
0136     if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
0137         if (connector->latency_present[1])
0138             tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
0139                 AUDIO_LIPSYNC(connector->audio_latency[1]);
0140         else
0141             tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
0142     } else {
0143         if (connector->latency_present[0])
0144             tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
0145                 AUDIO_LIPSYNC(connector->audio_latency[0]);
0146         else
0147             tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
0148     }
0149     WREG32_ENDPOINT(dig->pin->offset,
0150             AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
0151 }
0152
0153 void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
0154                          u8 *sadb, int sad_count)
0155 {
0156     struct radeon_device *rdev = encoder->dev->dev_private;
0157     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0158     struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
0159     u32 tmp;
0160
0161     if (!dig || !dig->afmt || !dig->pin)
0162         return;
0163
0164     /* program the speaker allocation */
0165     tmp = RREG32_ENDPOINT(dig->pin->offset,
0166                   AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
0167     tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
0168     /* set HDMI mode */
0169     tmp |= HDMI_CONNECTION;
0170     if (sad_count)
0171         tmp |= SPEAKER_ALLOCATION(sadb[0]);
0172     else
0173         tmp |= SPEAKER_ALLOCATION(5); /* stereo */
0174     WREG32_ENDPOINT(dig->pin->offset,
0175             AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
0176 }
0177
0178 void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
0179                        u8 *sadb, int sad_count)
0180 {
0181     struct radeon_device *rdev = encoder->dev->dev_private;
0182     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0183     struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
0184     u32 tmp;
0185
0186     if (!dig || !dig->afmt || !dig->pin)
0187         return;
0188
0189     /* program the speaker allocation */
0190     tmp = RREG32_ENDPOINT(dig->pin->offset,
0191                   AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
0192     tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
0193     /* set DP mode */
0194     tmp |= DP_CONNECTION;
0195     if (sad_count)
0196         tmp |= SPEAKER_ALLOCATION(sadb[0]);
0197     else
0198         tmp |= SPEAKER_ALLOCATION(5); /* stereo */
0199     WREG32_ENDPOINT(dig->pin->offset,
0200             AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
0201 }
0202
0203 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
0204                   struct cea_sad *sads, int sad_count)
0205 {
0206     int i;
0207     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0208     struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
0209     struct radeon_device *rdev = encoder->dev->dev_private;
0210     static const u16 eld_reg_to_type[][2] = {
0211         { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
0212         { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
0213         { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
0214         { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
0215         { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
0216         { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
0217         { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
0218         { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
0219         { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
0220         { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
0221         { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
0222         { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
0223     };
0224
0225     if (!dig || !dig->afmt || !dig->pin)
0226         return;
0227
0228     for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
0229         u32 value = 0;
0230         u8 stereo_freqs = 0;
0231         int max_channels = -1;
0232         int j;
0233
0234         for (j = 0; j < sad_count; j++) {
0235             struct cea_sad *sad = &sads[j];
0236
0237             if (sad->format == eld_reg_to_type[i][1]) {
0238                 if (sad->channels > max_channels) {
0239                     value = MAX_CHANNELS(sad->channels) |
0240                         DESCRIPTOR_BYTE_2(sad->byte2) |
0241                         SUPPORTED_FREQUENCIES(sad->freq);
0242                     max_channels = sad->channels;
0243                 }
0244
0245                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
0246                     stereo_freqs |= sad->freq;
0247                 else
0248                     break;
0249             }
0250         }
0251
0252         value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
0253
0254         WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value);
0255     }
0256 }
0257
0258 void dce6_audio_enable(struct radeon_device *rdev,
0259                struct r600_audio_pin *pin,
0260                u8 enable_mask)
0261 {
0262     if (!pin)
0263         return;
0264
0265     WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
0266             enable_mask ? AUDIO_ENABLED : 0);
0267 }
0268
0269 void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
0270                  struct radeon_crtc *crtc, unsigned int clock)
0271 {
0272     /* Two dtos; generally use dto0 for HDMI */
0273     u32 value = 0;
0274
0275     if (crtc)
0276         value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
0277
0278     WREG32(DCCG_AUDIO_DTO_SOURCE, value);
0279
0280     /* Express [24MHz / target pixel clock] as an exact rational
0281      * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
0282      * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
0283      */
0284     WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);
0285     WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
0286 }
0287
0288 void dce6_dp_audio_set_dto(struct radeon_device *rdev,
0289                struct radeon_crtc *crtc, unsigned int clock)
0290 {
0291     /* Two dtos; generally use dto1 for DP */
0292     u32 value = 0;
0293     value |= DCCG_AUDIO_DTO_SEL;
0294
0295     if (crtc)
0296         value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
0297
0298     WREG32(DCCG_AUDIO_DTO_SOURCE, value);
0299
0300     /* Express [24MHz / target pixel clock] as an exact rational
0301      * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
0302      * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
0303      */
0304     if (ASIC_IS_DCE8(rdev)) {
0305         unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) &
0306             DENTIST_DPREFCLK_WDIVIDER_MASK) >>
0307             DENTIST_DPREFCLK_WDIVIDER_SHIFT;
0308         div = radeon_audio_decode_dfs_div(div);
0309
0310         if (div)
0311             clock = clock * 100 / div;
0312
0313         WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
0314         WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
0315     } else {
0316         WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
0317         WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
0318     }
0319 }