drm/radeon/dce3_1_afmt.c

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  * Copyright 2014 Rafał Miłecki
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  */
0023 #include <linux/hdmi.h>
0024
0025 #include "radeon.h"
0026 #include "radeon_asic.h"
0027 #include "radeon_audio.h"
0028 #include "r600d.h"
0029
0030 void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
0031     u8 *sadb, int sad_count)
0032 {
0033     struct radeon_device *rdev = encoder->dev->dev_private;
0034     u32 tmp;
0035
0036     /* program the speaker allocation */
0037     tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
0038     tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
0039     /* set HDMI mode */
0040     tmp |= HDMI_CONNECTION;
0041     if (sad_count)
0042         tmp |= SPEAKER_ALLOCATION(sadb[0]);
0043     else
0044         tmp |= SPEAKER_ALLOCATION(5); /* stereo */
0045     WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
0046 }
0047
0048 void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
0049     u8 *sadb, int sad_count)
0050 {
0051     struct radeon_device *rdev = encoder->dev->dev_private;
0052     u32 tmp;
0053
0054     /* program the speaker allocation */
0055     tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
0056     tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
0057     /* set DP mode */
0058     tmp |= DP_CONNECTION;
0059     if (sad_count)
0060         tmp |= SPEAKER_ALLOCATION(sadb[0]);
0061     else
0062         tmp |= SPEAKER_ALLOCATION(5); /* stereo */
0063     WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
0064 }
0065
0066 void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder,
0067     struct cea_sad *sads, int sad_count)
0068 {
0069     int i;
0070     struct radeon_device *rdev = encoder->dev->dev_private;
0071     static const u16 eld_reg_to_type[][2] = {
0072         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
0073         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
0074         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
0075         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
0076         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
0077         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
0078         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
0079         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
0080         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
0081         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
0082         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
0083         { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
0084     };
0085
0086     for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
0087         u32 value = 0;
0088         u8 stereo_freqs = 0;
0089         int max_channels = -1;
0090         int j;
0091
0092         for (j = 0; j < sad_count; j++) {
0093             struct cea_sad *sad = &sads[j];
0094
0095             if (sad->format == eld_reg_to_type[i][1]) {
0096                 if (sad->channels > max_channels) {
0097                     value = MAX_CHANNELS(sad->channels) |
0098                         DESCRIPTOR_BYTE_2(sad->byte2) |
0099                         SUPPORTED_FREQUENCIES(sad->freq);
0100                     max_channels = sad->channels;
0101                 }
0102
0103                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
0104                     stereo_freqs |= sad->freq;
0105                 else
0106                     break;
0107             }
0108         }
0109
0110         value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
0111
0112         WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
0113     }
0114 }
0115
0116 void dce3_2_audio_set_dto(struct radeon_device *rdev,
0117     struct radeon_crtc *crtc, unsigned int clock)
0118 {
0119     struct radeon_encoder *radeon_encoder;
0120     struct radeon_encoder_atom_dig *dig;
0121     unsigned int max_ratio = clock / 24000;
0122     u32 dto_phase;
0123     u32 wallclock_ratio;
0124     u32 dto_cntl;
0125
0126     if (!crtc)
0127         return;
0128
0129     radeon_encoder = to_radeon_encoder(crtc->encoder);
0130     dig = radeon_encoder->enc_priv;
0131
0132     if (!dig)
0133         return;
0134
0135     if (max_ratio >= 8) {
0136         dto_phase = 192 * 1000;
0137         wallclock_ratio = 3;
0138     } else if (max_ratio >= 4) {
0139         dto_phase = 96 * 1000;
0140         wallclock_ratio = 2;
0141     } else if (max_ratio >= 2) {
0142         dto_phase = 48 * 1000;
0143         wallclock_ratio = 1;
0144     } else {
0145         dto_phase = 24 * 1000;
0146         wallclock_ratio = 0;
0147     }
0148
0149     /* Express [24MHz / target pixel clock] as an exact rational
0150      * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
0151      * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
0152      */
0153     if (dig->dig_encoder == 0) {
0154         dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
0155         dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
0156         WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
0157         WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
0158         WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
0159         WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
0160     } else {
0161         dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
0162         dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
0163         WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
0164         WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
0165         WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
0166         WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
0167     }
0168 }
0169
0170 void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset,
0171     const struct radeon_hdmi_acr *acr)
0172 {
0173     struct drm_device *dev = encoder->dev;
0174     struct radeon_device *rdev = dev->dev_private;
0175
0176     WREG32(DCE3_HDMI0_ACR_PACKET_CONTROL + offset,
0177         HDMI0_ACR_SOURCE |      /* select SW CTS value */
0178         HDMI0_ACR_AUTO_SEND);   /* allow hw to sent ACR packets when required */
0179
0180     WREG32_P(HDMI0_ACR_32_0 + offset,
0181         HDMI0_ACR_CTS_32(acr->cts_32khz),
0182         ~HDMI0_ACR_CTS_32_MASK);
0183     WREG32_P(HDMI0_ACR_32_1 + offset,
0184         HDMI0_ACR_N_32(acr->n_32khz),
0185         ~HDMI0_ACR_N_32_MASK);
0186
0187     WREG32_P(HDMI0_ACR_44_0 + offset,
0188         HDMI0_ACR_CTS_44(acr->cts_44_1khz),
0189         ~HDMI0_ACR_CTS_44_MASK);
0190     WREG32_P(HDMI0_ACR_44_1 + offset,
0191         HDMI0_ACR_N_44(acr->n_44_1khz),
0192         ~HDMI0_ACR_N_44_MASK);
0193
0194     WREG32_P(HDMI0_ACR_48_0 + offset,
0195         HDMI0_ACR_CTS_48(acr->cts_48khz),
0196         ~HDMI0_ACR_CTS_48_MASK);
0197     WREG32_P(HDMI0_ACR_48_1 + offset,
0198         HDMI0_ACR_N_48(acr->n_48khz),
0199         ~HDMI0_ACR_N_48_MASK);
0200 }
0201
0202 void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset)
0203 {
0204     struct drm_device *dev = encoder->dev;
0205     struct radeon_device *rdev = dev->dev_private;
0206
0207     WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
0208         HDMI0_AUDIO_DELAY_EN(1) |           /* default audio delay */
0209         HDMI0_AUDIO_PACKETS_PER_LINE(3));   /* should be suffient for all audio modes and small enough for all hblanks */
0210
0211     WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
0212         AFMT_AUDIO_SAMPLE_SEND |            /* send audio packets */
0213         AFMT_60958_CS_UPDATE);              /* allow 60958 channel status fields to be updated */
0214
0215     WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
0216         HDMI0_AUDIO_INFO_SEND |             /* enable audio info frames (frames won't be set until audio is enabled) */
0217         HDMI0_AUDIO_INFO_CONT);             /* send audio info frames every frame/field */
0218
0219     WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
0220         HDMI0_AUDIO_INFO_LINE(2));          /* anything other than 0 */
0221 }
0222
0223 void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
0224 {
0225     struct drm_device *dev = encoder->dev;
0226     struct radeon_device *rdev = dev->dev_private;
0227
0228     if (mute)
0229         WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);
0230     else
0231         WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);
0232 }