drm/radeon/cypress_dpm.h

0001 /*
0002  * Copyright 2011 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __CYPRESS_DPM_H__
0024 #define __CYPRESS_DPM_H__
0025
0026 #include "rv770_dpm.h"
0027 #include "evergreen_smc.h"
0028
0029 struct evergreen_mc_reg_entry {
0030     u32 mclk_max;
0031     u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];
0032 };
0033
0034 struct evergreen_mc_reg_table {
0035     u8 last;
0036     u8 num_entries;
0037     u16 valid_flag;
0038     struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
0039     SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];
0040 };
0041
0042 struct evergreen_ulv_param {
0043     bool supported;
0044     struct rv7xx_pl *pl;
0045 };
0046
0047 struct evergreen_arb_registers {
0048     u32 mc_arb_dram_timing;
0049     u32 mc_arb_dram_timing2;
0050     u32 mc_arb_rfsh_rate;
0051     u32 mc_arb_burst_time;
0052 };
0053
0054 struct at {
0055     u32 rlp;
0056     u32 rmp;
0057     u32 lhp;
0058     u32 lmp;
0059 };
0060
0061 struct evergreen_power_info {
0062     /* must be first! */
0063     struct rv7xx_power_info rv7xx;
0064     /* flags */
0065     bool vddci_control;
0066     bool dynamic_ac_timing;
0067     bool abm;
0068     bool mcls;
0069     bool light_sleep;
0070     bool memory_transition;
0071     bool pcie_performance_request;
0072     bool pcie_performance_request_registered;
0073     bool sclk_deep_sleep;
0074     bool dll_default_on;
0075     bool ls_clock_gating;
0076     bool smu_uvd_hs;
0077     bool uvd_enabled;
0078     /* stored values */
0079     u16 acpi_vddci;
0080     u8 mvdd_high_index;
0081     u8 mvdd_low_index;
0082     u32 mclk_edc_wr_enable_threshold;
0083     struct evergreen_mc_reg_table mc_reg_table;
0084     struct atom_voltage_table vddc_voltage_table;
0085     struct atom_voltage_table vddci_voltage_table;
0086     struct evergreen_arb_registers bootup_arb_registers;
0087     struct evergreen_ulv_param ulv;
0088     struct at ats[2];
0089     /* smc offsets */
0090     u16 mc_reg_table_start;
0091     struct radeon_ps current_rps;
0092     struct rv7xx_ps current_ps;
0093     struct radeon_ps requested_rps;
0094     struct rv7xx_ps requested_ps;
0095 };
0096
0097 #define CYPRESS_HASI_DFLT                               400000
0098 #define CYPRESS_MGCGTTLOCAL0_DFLT                       0x00000000
0099 #define CYPRESS_MGCGTTLOCAL1_DFLT                       0x00000000
0100 #define CYPRESS_MGCGTTLOCAL2_DFLT                       0x00000000
0101 #define CYPRESS_MGCGTTLOCAL3_DFLT                       0x00000000
0102 #define CYPRESS_MGCGCGTSSMCTRL_DFLT                     0x81944bc0
0103 #define REDWOOD_MGCGCGTSSMCTRL_DFLT                     0x6e944040
0104 #define CEDAR_MGCGCGTSSMCTRL_DFLT                       0x46944040
0105 #define CYPRESS_VRC_DFLT                                0xC00033
0106
0107 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
0108 #define PCIE_PERF_REQ_FORCE_LOWPOWER    1
0109 #define PCIE_PERF_REQ_PECI_GEN1         2
0110 #define PCIE_PERF_REQ_PECI_GEN2         3
0111 #define PCIE_PERF_REQ_PECI_GEN3         4
0112
0113 int cypress_convert_power_level_to_smc(struct radeon_device *rdev,
0114                        struct rv7xx_pl *pl,
0115                        RV770_SMC_HW_PERFORMANCE_LEVEL *level,
0116                        u8 watermark_level);
0117 int cypress_populate_smc_acpi_state(struct radeon_device *rdev,
0118                     RV770_SMC_STATETABLE *table);
0119 int cypress_populate_smc_voltage_tables(struct radeon_device *rdev,
0120                     RV770_SMC_STATETABLE *table);
0121 int cypress_populate_smc_initial_state(struct radeon_device *rdev,
0122                        struct radeon_ps *radeon_initial_state,
0123                        RV770_SMC_STATETABLE *table);
0124 u32 cypress_calculate_burst_time(struct radeon_device *rdev,
0125                  u32 engine_clock, u32 memory_clock);
0126 void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev,
0127                               struct radeon_ps *radeon_new_state,
0128                               struct radeon_ps *radeon_current_state);
0129 int cypress_upload_sw_state(struct radeon_device *rdev,
0130                 struct radeon_ps *radeon_new_state);
0131 int cypress_upload_mc_reg_table(struct radeon_device *rdev,
0132                 struct radeon_ps *radeon_new_state);
0133 void cypress_program_memory_timing_parameters(struct radeon_device *rdev,
0134                           struct radeon_ps *radeon_new_state);
0135 void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
0136                              struct radeon_ps *radeon_new_state,
0137                              struct radeon_ps *radeon_current_state);
0138 int cypress_construct_voltage_tables(struct radeon_device *rdev);
0139 int cypress_get_mvdd_configuration(struct radeon_device *rdev);
0140 void cypress_enable_spread_spectrum(struct radeon_device *rdev,
0141                     bool enable);
0142 void cypress_enable_display_gap(struct radeon_device *rdev);
0143 int cypress_get_table_locations(struct radeon_device *rdev);
0144 int cypress_populate_mc_reg_table(struct radeon_device *rdev,
0145                   struct radeon_ps *radeon_boot_state);
0146 void cypress_program_response_times(struct radeon_device *rdev);
0147 int cypress_notify_smc_display_change(struct radeon_device *rdev,
0148                       bool has_display);
0149 void cypress_enable_sclk_control(struct radeon_device *rdev,
0150                  bool enable);
0151 void cypress_enable_mclk_control(struct radeon_device *rdev,
0152                  bool enable);
0153 void cypress_start_dpm(struct radeon_device *rdev);
0154 void cypress_advertise_gen2_capability(struct radeon_device *rdev);
0155 u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf);
0156 u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev,
0157                     u32 memory_clock, bool strobe_mode);
0158 u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk);
0159
0160 #endif