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0001 /*
0002  * Copyright 2011 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Alex Deucher
0023  */
0024 
0025 #include <linux/pci.h>
0026 
0027 #include "atom.h"
0028 #include "cypress_dpm.h"
0029 #include "evergreen.h"
0030 #include "evergreend.h"
0031 #include "r600_dpm.h"
0032 #include "rv770.h"
0033 #include "radeon.h"
0034 #include "radeon_asic.h"
0035 
0036 #define SMC_RAM_END 0x8000
0037 
0038 #define MC_CG_ARB_FREQ_F0           0x0a
0039 #define MC_CG_ARB_FREQ_F1           0x0b
0040 #define MC_CG_ARB_FREQ_F2           0x0c
0041 #define MC_CG_ARB_FREQ_F3           0x0d
0042 
0043 #define MC_CG_SEQ_DRAMCONF_S0       0x05
0044 #define MC_CG_SEQ_DRAMCONF_S1       0x06
0045 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
0046 #define MC_CG_SEQ_YCLK_RESUME       0x0a
0047 
0048 static void cypress_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
0049                          bool enable)
0050 {
0051     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0052     u32 tmp, bif;
0053 
0054     tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
0055     if (enable) {
0056         if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
0057             (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
0058             if (!pi->boot_in_gen2) {
0059                 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
0060                 bif |= CG_CLIENT_REQ(0xd);
0061                 WREG32(CG_BIF_REQ_AND_RSP, bif);
0062 
0063                 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
0064                 tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
0065                 tmp |= LC_GEN2_EN_STRAP;
0066 
0067                 tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
0068                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
0069                 udelay(10);
0070                 tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
0071                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
0072             }
0073         }
0074     } else {
0075         if (!pi->boot_in_gen2) {
0076             tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
0077             tmp &= ~LC_GEN2_EN_STRAP;
0078         }
0079         if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
0080             (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
0081             WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
0082     }
0083 }
0084 
0085 static void cypress_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
0086                          bool enable)
0087 {
0088     cypress_enable_bif_dynamic_pcie_gen2(rdev, enable);
0089 
0090     if (enable)
0091         WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
0092     else
0093         WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
0094 }
0095 
0096 #if 0
0097 static int cypress_enter_ulp_state(struct radeon_device *rdev)
0098 {
0099     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0100 
0101     if (pi->gfx_clock_gating) {
0102         WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
0103         WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
0104         WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
0105 
0106         RREG32(GB_ADDR_CONFIG);
0107     }
0108 
0109     WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
0110          ~HOST_SMC_MSG_MASK);
0111 
0112     udelay(7000);
0113 
0114     return 0;
0115 }
0116 #endif
0117 
0118 static void cypress_gfx_clock_gating_enable(struct radeon_device *rdev,
0119                         bool enable)
0120 {
0121     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
0122 
0123     if (enable) {
0124         if (eg_pi->light_sleep) {
0125             WREG32(GRBM_GFX_INDEX, 0xC0000000);
0126 
0127             WREG32_CG(CG_CGLS_TILE_0, 0xFFFFFFFF);
0128             WREG32_CG(CG_CGLS_TILE_1, 0xFFFFFFFF);
0129             WREG32_CG(CG_CGLS_TILE_2, 0xFFFFFFFF);
0130             WREG32_CG(CG_CGLS_TILE_3, 0xFFFFFFFF);
0131             WREG32_CG(CG_CGLS_TILE_4, 0xFFFFFFFF);
0132             WREG32_CG(CG_CGLS_TILE_5, 0xFFFFFFFF);
0133             WREG32_CG(CG_CGLS_TILE_6, 0xFFFFFFFF);
0134             WREG32_CG(CG_CGLS_TILE_7, 0xFFFFFFFF);
0135             WREG32_CG(CG_CGLS_TILE_8, 0xFFFFFFFF);
0136             WREG32_CG(CG_CGLS_TILE_9, 0xFFFFFFFF);
0137             WREG32_CG(CG_CGLS_TILE_10, 0xFFFFFFFF);
0138             WREG32_CG(CG_CGLS_TILE_11, 0xFFFFFFFF);
0139 
0140             WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN);
0141         }
0142         WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
0143     } else {
0144         WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
0145         WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
0146         WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
0147         RREG32(GB_ADDR_CONFIG);
0148 
0149         if (eg_pi->light_sleep) {
0150             WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN);
0151 
0152             WREG32(GRBM_GFX_INDEX, 0xC0000000);
0153 
0154             WREG32_CG(CG_CGLS_TILE_0, 0);
0155             WREG32_CG(CG_CGLS_TILE_1, 0);
0156             WREG32_CG(CG_CGLS_TILE_2, 0);
0157             WREG32_CG(CG_CGLS_TILE_3, 0);
0158             WREG32_CG(CG_CGLS_TILE_4, 0);
0159             WREG32_CG(CG_CGLS_TILE_5, 0);
0160             WREG32_CG(CG_CGLS_TILE_6, 0);
0161             WREG32_CG(CG_CGLS_TILE_7, 0);
0162             WREG32_CG(CG_CGLS_TILE_8, 0);
0163             WREG32_CG(CG_CGLS_TILE_9, 0);
0164             WREG32_CG(CG_CGLS_TILE_10, 0);
0165             WREG32_CG(CG_CGLS_TILE_11, 0);
0166         }
0167     }
0168 }
0169 
0170 static void cypress_mg_clock_gating_enable(struct radeon_device *rdev,
0171                        bool enable)
0172 {
0173     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0174     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
0175 
0176     if (enable) {
0177         u32 cgts_sm_ctrl_reg;
0178 
0179         if (rdev->family == CHIP_CEDAR)
0180             cgts_sm_ctrl_reg = CEDAR_MGCGCGTSSMCTRL_DFLT;
0181         else if (rdev->family == CHIP_REDWOOD)
0182             cgts_sm_ctrl_reg = REDWOOD_MGCGCGTSSMCTRL_DFLT;
0183         else
0184             cgts_sm_ctrl_reg = CYPRESS_MGCGCGTSSMCTRL_DFLT;
0185 
0186         WREG32(GRBM_GFX_INDEX, 0xC0000000);
0187 
0188         WREG32_CG(CG_CGTT_LOCAL_0, CYPRESS_MGCGTTLOCAL0_DFLT);
0189         WREG32_CG(CG_CGTT_LOCAL_1, CYPRESS_MGCGTTLOCAL1_DFLT & 0xFFFFCFFF);
0190         WREG32_CG(CG_CGTT_LOCAL_2, CYPRESS_MGCGTTLOCAL2_DFLT);
0191         WREG32_CG(CG_CGTT_LOCAL_3, CYPRESS_MGCGTTLOCAL3_DFLT);
0192 
0193         if (pi->mgcgtssm)
0194             WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
0195 
0196         if (eg_pi->mcls) {
0197             WREG32_P(MC_CITF_MISC_RD_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
0198             WREG32_P(MC_CITF_MISC_WR_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
0199             WREG32_P(MC_CITF_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
0200             WREG32_P(MC_HUB_MISC_HUB_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
0201             WREG32_P(MC_HUB_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
0202             WREG32_P(MC_HUB_MISC_SIP_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
0203             WREG32_P(MC_XPB_CLK_GAT, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
0204             WREG32_P(VM_L2_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
0205         }
0206     } else {
0207         WREG32(GRBM_GFX_INDEX, 0xC0000000);
0208 
0209         WREG32_CG(CG_CGTT_LOCAL_0, 0xFFFFFFFF);
0210         WREG32_CG(CG_CGTT_LOCAL_1, 0xFFFFFFFF);
0211         WREG32_CG(CG_CGTT_LOCAL_2, 0xFFFFFFFF);
0212         WREG32_CG(CG_CGTT_LOCAL_3, 0xFFFFFFFF);
0213 
0214         if (pi->mgcgtssm)
0215             WREG32(CGTS_SM_CTRL_REG, 0x81f44bc0);
0216     }
0217 }
0218 
0219 void cypress_enable_spread_spectrum(struct radeon_device *rdev,
0220                     bool enable)
0221 {
0222     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0223 
0224     if (enable) {
0225         if (pi->sclk_ss)
0226             WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
0227 
0228         if (pi->mclk_ss)
0229             WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN);
0230     } else {
0231         WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
0232         WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
0233         WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN);
0234         WREG32_P(MPLL_CNTL_MODE, 0, ~SS_DSMODE_EN);
0235     }
0236 }
0237 
0238 void cypress_start_dpm(struct radeon_device *rdev)
0239 {
0240     WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
0241 }
0242 
0243 void cypress_enable_sclk_control(struct radeon_device *rdev,
0244                  bool enable)
0245 {
0246     if (enable)
0247         WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
0248     else
0249         WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
0250 }
0251 
0252 void cypress_enable_mclk_control(struct radeon_device *rdev,
0253                  bool enable)
0254 {
0255     if (enable)
0256         WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
0257     else
0258         WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
0259 }
0260 
0261 int cypress_notify_smc_display_change(struct radeon_device *rdev,
0262                       bool has_display)
0263 {
0264     PPSMC_Msg msg = has_display ?
0265         (PPSMC_Msg)PPSMC_MSG_HasDisplay : (PPSMC_Msg)PPSMC_MSG_NoDisplay;
0266 
0267     if (rv770_send_msg_to_smc(rdev, msg) != PPSMC_Result_OK)
0268         return -EINVAL;
0269 
0270     return 0;
0271 }
0272 
0273 void cypress_program_response_times(struct radeon_device *rdev)
0274 {
0275     u32 reference_clock;
0276     u32 mclk_switch_limit;
0277 
0278     reference_clock = radeon_get_xclk(rdev);
0279     mclk_switch_limit = (460 * reference_clock) / 100;
0280 
0281     rv770_write_smc_soft_register(rdev,
0282                       RV770_SMC_SOFT_REGISTER_mclk_switch_lim,
0283                       mclk_switch_limit);
0284 
0285     rv770_write_smc_soft_register(rdev,
0286                       RV770_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
0287 
0288     rv770_write_smc_soft_register(rdev,
0289                       RV770_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
0290 
0291     rv770_program_response_times(rdev);
0292 
0293     if (ASIC_IS_LOMBOK(rdev))
0294         rv770_write_smc_soft_register(rdev,
0295                           RV770_SMC_SOFT_REGISTER_is_asic_lombok, 1);
0296 
0297 }
0298 
0299 static int cypress_pcie_performance_request(struct radeon_device *rdev,
0300                         u8 perf_req, bool advertise)
0301 {
0302 #if defined(CONFIG_ACPI)
0303     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
0304 #endif
0305     u32 tmp;
0306 
0307     udelay(10);
0308     tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
0309     if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) && (tmp & LC_CURRENT_DATA_RATE))
0310         return 0;
0311 
0312 #if defined(CONFIG_ACPI)
0313     if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) ||
0314         (perf_req == PCIE_PERF_REQ_PECI_GEN2)) {
0315         eg_pi->pcie_performance_request_registered = true;
0316         return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
0317     } else if ((perf_req == PCIE_PERF_REQ_REMOVE_REGISTRY) &&
0318            eg_pi->pcie_performance_request_registered) {
0319         eg_pi->pcie_performance_request_registered = false;
0320         return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
0321     }
0322 #endif
0323 
0324     return 0;
0325 }
0326 
0327 void cypress_advertise_gen2_capability(struct radeon_device *rdev)
0328 {
0329     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0330     u32 tmp;
0331 
0332 #if defined(CONFIG_ACPI)
0333     radeon_acpi_pcie_notify_device_ready(rdev);
0334 #endif
0335 
0336     tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
0337 
0338     if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
0339         (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
0340         pi->pcie_gen2 = true;
0341     else
0342         pi->pcie_gen2 = false;
0343 
0344     if (!pi->pcie_gen2)
0345         cypress_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true);
0346 
0347 }
0348 
0349 static enum radeon_pcie_gen cypress_get_maximum_link_speed(struct radeon_ps *radeon_state)
0350 {
0351     struct rv7xx_ps *state = rv770_get_ps(radeon_state);
0352 
0353     if (state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
0354         return 1;
0355     return 0;
0356 }
0357 
0358 void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
0359                              struct radeon_ps *radeon_new_state,
0360                              struct radeon_ps *radeon_current_state)
0361 {
0362     enum radeon_pcie_gen pcie_link_speed_target =
0363         cypress_get_maximum_link_speed(radeon_new_state);
0364     enum radeon_pcie_gen pcie_link_speed_current =
0365         cypress_get_maximum_link_speed(radeon_current_state);
0366     u8 request;
0367 
0368     if (pcie_link_speed_target < pcie_link_speed_current) {
0369         if (pcie_link_speed_target == RADEON_PCIE_GEN1)
0370             request = PCIE_PERF_REQ_PECI_GEN1;
0371         else if (pcie_link_speed_target == RADEON_PCIE_GEN2)
0372             request = PCIE_PERF_REQ_PECI_GEN2;
0373         else
0374             request = PCIE_PERF_REQ_PECI_GEN3;
0375 
0376         cypress_pcie_performance_request(rdev, request, false);
0377     }
0378 }
0379 
0380 void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev,
0381                               struct radeon_ps *radeon_new_state,
0382                               struct radeon_ps *radeon_current_state)
0383 {
0384     enum radeon_pcie_gen pcie_link_speed_target =
0385         cypress_get_maximum_link_speed(radeon_new_state);
0386     enum radeon_pcie_gen pcie_link_speed_current =
0387         cypress_get_maximum_link_speed(radeon_current_state);
0388     u8 request;
0389 
0390     if (pcie_link_speed_target > pcie_link_speed_current) {
0391         if (pcie_link_speed_target == RADEON_PCIE_GEN1)
0392             request = PCIE_PERF_REQ_PECI_GEN1;
0393         else if (pcie_link_speed_target == RADEON_PCIE_GEN2)
0394             request = PCIE_PERF_REQ_PECI_GEN2;
0395         else
0396             request = PCIE_PERF_REQ_PECI_GEN3;
0397 
0398         cypress_pcie_performance_request(rdev, request, false);
0399     }
0400 }
0401 
0402 static int cypress_populate_voltage_value(struct radeon_device *rdev,
0403                       struct atom_voltage_table *table,
0404                       u16 value, RV770_SMC_VOLTAGE_VALUE *voltage)
0405 {
0406     unsigned int i;
0407 
0408     for (i = 0; i < table->count; i++) {
0409         if (value <= table->entries[i].value) {
0410             voltage->index = (u8)i;
0411             voltage->value = cpu_to_be16(table->entries[i].value);
0412             break;
0413         }
0414     }
0415 
0416     if (i == table->count)
0417         return -EINVAL;
0418 
0419     return 0;
0420 }
0421 
0422 u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
0423 {
0424     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0425     u8 result = 0;
0426     bool strobe_mode = false;
0427 
0428     if (pi->mem_gddr5) {
0429         if (mclk <= pi->mclk_strobe_mode_threshold)
0430             strobe_mode = true;
0431         result = cypress_get_mclk_frequency_ratio(rdev, mclk, strobe_mode);
0432 
0433         if (strobe_mode)
0434             result |= SMC_STROBE_ENABLE;
0435     }
0436 
0437     return result;
0438 }
0439 
0440 u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf)
0441 {
0442     u32 ref_clk = rdev->clock.mpll.reference_freq;
0443     u32 vco = clkf * ref_clk;
0444 
0445     /* 100 Mhz ref clk */
0446     if (ref_clk == 10000) {
0447         if (vco > 500000)
0448             return 0xC6;
0449         if (vco > 400000)
0450             return 0x9D;
0451         if (vco > 330000)
0452             return 0x6C;
0453         if (vco > 250000)
0454             return 0x2B;
0455         if (vco >  160000)
0456             return 0x5B;
0457         if (vco > 120000)
0458             return 0x0A;
0459         return 0x4B;
0460     }
0461 
0462     /* 27 Mhz ref clk */
0463     if (vco > 250000)
0464         return 0x8B;
0465     if (vco > 200000)
0466         return 0xCC;
0467     if (vco > 150000)
0468         return 0x9B;
0469     return 0x6B;
0470 }
0471 
0472 static int cypress_populate_mclk_value(struct radeon_device *rdev,
0473                        u32 engine_clock, u32 memory_clock,
0474                        RV7XX_SMC_MCLK_VALUE *mclk,
0475                        bool strobe_mode, bool dll_state_on)
0476 {
0477     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0478 
0479     u32 mpll_ad_func_cntl =
0480         pi->clk_regs.rv770.mpll_ad_func_cntl;
0481     u32 mpll_ad_func_cntl_2 =
0482         pi->clk_regs.rv770.mpll_ad_func_cntl_2;
0483     u32 mpll_dq_func_cntl =
0484         pi->clk_regs.rv770.mpll_dq_func_cntl;
0485     u32 mpll_dq_func_cntl_2 =
0486         pi->clk_regs.rv770.mpll_dq_func_cntl_2;
0487     u32 mclk_pwrmgt_cntl =
0488         pi->clk_regs.rv770.mclk_pwrmgt_cntl;
0489     u32 dll_cntl =
0490         pi->clk_regs.rv770.dll_cntl;
0491     u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;
0492     u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2;
0493     struct atom_clock_dividers dividers;
0494     u32 ibias;
0495     u32 dll_speed;
0496     int ret;
0497     u32 mc_seq_misc7;
0498 
0499     ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
0500                          memory_clock, strobe_mode, &dividers);
0501     if (ret)
0502         return ret;
0503 
0504     if (!strobe_mode) {
0505         mc_seq_misc7 = RREG32(MC_SEQ_MISC7);
0506 
0507         if(mc_seq_misc7 & 0x8000000)
0508             dividers.post_div = 1;
0509     }
0510 
0511     ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
0512 
0513     mpll_ad_func_cntl &= ~(CLKR_MASK |
0514                    YCLK_POST_DIV_MASK |
0515                    CLKF_MASK |
0516                    CLKFRAC_MASK |
0517                    IBIAS_MASK);
0518     mpll_ad_func_cntl |= CLKR(dividers.ref_div);
0519     mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);
0520     mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);
0521     mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);
0522     mpll_ad_func_cntl |= IBIAS(ibias);
0523 
0524     if (dividers.vco_mode)
0525         mpll_ad_func_cntl_2 |= VCO_MODE;
0526     else
0527         mpll_ad_func_cntl_2 &= ~VCO_MODE;
0528 
0529     if (pi->mem_gddr5) {
0530         mpll_dq_func_cntl &= ~(CLKR_MASK |
0531                        YCLK_POST_DIV_MASK |
0532                        CLKF_MASK |
0533                        CLKFRAC_MASK |
0534                        IBIAS_MASK);
0535         mpll_dq_func_cntl |= CLKR(dividers.ref_div);
0536         mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);
0537         mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);
0538         mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);
0539         mpll_dq_func_cntl |= IBIAS(ibias);
0540 
0541         if (strobe_mode)
0542             mpll_dq_func_cntl &= ~PDNB;
0543         else
0544             mpll_dq_func_cntl |= PDNB;
0545 
0546         if (dividers.vco_mode)
0547             mpll_dq_func_cntl_2 |= VCO_MODE;
0548         else
0549             mpll_dq_func_cntl_2 &= ~VCO_MODE;
0550     }
0551 
0552     if (pi->mclk_ss) {
0553         struct radeon_atom_ss ss;
0554         u32 vco_freq = memory_clock * dividers.post_div;
0555 
0556         if (radeon_atombios_get_asic_ss_info(rdev, &ss,
0557                              ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
0558             u32 reference_clock = rdev->clock.mpll.reference_freq;
0559             u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
0560             u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
0561             u32 clk_v = ss.percentage *
0562                 (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
0563 
0564             mpll_ss1 &= ~CLKV_MASK;
0565             mpll_ss1 |= CLKV(clk_v);
0566 
0567             mpll_ss2 &= ~CLKS_MASK;
0568             mpll_ss2 |= CLKS(clk_s);
0569         }
0570     }
0571 
0572     dll_speed = rv740_get_dll_speed(pi->mem_gddr5,
0573                     memory_clock);
0574 
0575     mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
0576     mclk_pwrmgt_cntl |= DLL_SPEED(dll_speed);
0577     if (dll_state_on)
0578         mclk_pwrmgt_cntl |= (MRDCKA0_PDNB |
0579                      MRDCKA1_PDNB |
0580                      MRDCKB0_PDNB |
0581                      MRDCKB1_PDNB |
0582                      MRDCKC0_PDNB |
0583                      MRDCKC1_PDNB |
0584                      MRDCKD0_PDNB |
0585                      MRDCKD1_PDNB);
0586     else
0587         mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
0588                       MRDCKA1_PDNB |
0589                       MRDCKB0_PDNB |
0590                       MRDCKB1_PDNB |
0591                       MRDCKC0_PDNB |
0592                       MRDCKC1_PDNB |
0593                       MRDCKD0_PDNB |
0594                       MRDCKD1_PDNB);
0595 
0596     mclk->mclk770.mclk_value = cpu_to_be32(memory_clock);
0597     mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
0598     mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
0599     mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
0600     mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
0601     mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
0602     mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
0603     mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1);
0604     mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
0605 
0606     return 0;
0607 }
0608 
0609 u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev,
0610                     u32 memory_clock, bool strobe_mode)
0611 {
0612     u8 mc_para_index;
0613 
0614     if (rdev->family >= CHIP_BARTS) {
0615         if (strobe_mode) {
0616             if (memory_clock < 10000)
0617                 mc_para_index = 0x00;
0618             else if (memory_clock > 47500)
0619                 mc_para_index = 0x0f;
0620             else
0621                 mc_para_index = (u8)((memory_clock - 10000) / 2500);
0622         } else {
0623             if (memory_clock < 65000)
0624                 mc_para_index = 0x00;
0625             else if (memory_clock > 135000)
0626                 mc_para_index = 0x0f;
0627             else
0628                 mc_para_index = (u8)((memory_clock - 60000) / 5000);
0629         }
0630     } else {
0631         if (strobe_mode) {
0632             if (memory_clock < 10000)
0633                 mc_para_index = 0x00;
0634             else if (memory_clock > 47500)
0635                 mc_para_index = 0x0f;
0636             else
0637                 mc_para_index = (u8)((memory_clock - 10000) / 2500);
0638         } else {
0639             if (memory_clock < 40000)
0640                 mc_para_index = 0x00;
0641             else if (memory_clock > 115000)
0642                 mc_para_index = 0x0f;
0643             else
0644                 mc_para_index = (u8)((memory_clock - 40000) / 5000);
0645         }
0646     }
0647     return mc_para_index;
0648 }
0649 
0650 static int cypress_populate_mvdd_value(struct radeon_device *rdev,
0651                        u32 mclk,
0652                        RV770_SMC_VOLTAGE_VALUE *voltage)
0653 {
0654     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0655     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
0656 
0657     if (!pi->mvdd_control) {
0658         voltage->index = eg_pi->mvdd_high_index;
0659         voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
0660         return 0;
0661     }
0662 
0663     if (mclk <= pi->mvdd_split_frequency) {
0664         voltage->index = eg_pi->mvdd_low_index;
0665         voltage->value = cpu_to_be16(MVDD_LOW_VALUE);
0666     } else {
0667         voltage->index = eg_pi->mvdd_high_index;
0668         voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
0669     }
0670 
0671     return 0;
0672 }
0673 
0674 int cypress_convert_power_level_to_smc(struct radeon_device *rdev,
0675                        struct rv7xx_pl *pl,
0676                        RV770_SMC_HW_PERFORMANCE_LEVEL *level,
0677                        u8 watermark_level)
0678 {
0679     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0680     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
0681     int ret;
0682     bool dll_state_on;
0683 
0684     level->gen2PCIE = pi->pcie_gen2 ?
0685         ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
0686     level->gen2XSP  = (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0;
0687     level->backbias = (pl->flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? 1 : 0;
0688     level->displayWatermark = watermark_level;
0689 
0690     ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk);
0691     if (ret)
0692         return ret;
0693 
0694     level->mcFlags =  0;
0695     if (pi->mclk_stutter_mode_threshold &&
0696         (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
0697         !eg_pi->uvd_enabled) {
0698         level->mcFlags |= SMC_MC_STUTTER_EN;
0699         if (eg_pi->sclk_deep_sleep)
0700             level->stateFlags |= PPSMC_STATEFLAG_AUTO_PULSE_SKIP;
0701         else
0702             level->stateFlags &= ~PPSMC_STATEFLAG_AUTO_PULSE_SKIP;
0703     }
0704 
0705     if (pi->mem_gddr5) {
0706         if (pl->mclk > pi->mclk_edc_enable_threshold)
0707             level->mcFlags |= SMC_MC_EDC_RD_FLAG;
0708 
0709         if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
0710             level->mcFlags |= SMC_MC_EDC_WR_FLAG;
0711 
0712         level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
0713 
0714         if (level->strobeMode & SMC_STROBE_ENABLE) {
0715             if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=
0716                 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
0717                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
0718             else
0719                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
0720         } else
0721             dll_state_on = eg_pi->dll_default_on;
0722 
0723         ret = cypress_populate_mclk_value(rdev,
0724                           pl->sclk,
0725                           pl->mclk,
0726                           &level->mclk,
0727                           (level->strobeMode & SMC_STROBE_ENABLE) != 0,
0728                           dll_state_on);
0729     } else {
0730         ret = cypress_populate_mclk_value(rdev,
0731                           pl->sclk,
0732                           pl->mclk,
0733                           &level->mclk,
0734                           true,
0735                           true);
0736     }
0737     if (ret)
0738         return ret;
0739 
0740     ret = cypress_populate_voltage_value(rdev,
0741                          &eg_pi->vddc_voltage_table,
0742                          pl->vddc,
0743                          &level->vddc);
0744     if (ret)
0745         return ret;
0746 
0747     if (eg_pi->vddci_control) {
0748         ret = cypress_populate_voltage_value(rdev,
0749                              &eg_pi->vddci_voltage_table,
0750                              pl->vddci,
0751                              &level->vddci);
0752         if (ret)
0753             return ret;
0754     }
0755 
0756     ret = cypress_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
0757 
0758     return ret;
0759 }
0760 
0761 static int cypress_convert_power_state_to_smc(struct radeon_device *rdev,
0762                           struct radeon_ps *radeon_state,
0763                           RV770_SMC_SWSTATE *smc_state)
0764 {
0765     struct rv7xx_ps *state = rv770_get_ps(radeon_state);
0766     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
0767     int ret;
0768 
0769     if (!(radeon_state->caps & ATOM_PPLIB_DISALLOW_ON_DC))
0770         smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
0771 
0772     ret = cypress_convert_power_level_to_smc(rdev,
0773                          &state->low,
0774                          &smc_state->levels[0],
0775                          PPSMC_DISPLAY_WATERMARK_LOW);
0776     if (ret)
0777         return ret;
0778 
0779     ret = cypress_convert_power_level_to_smc(rdev,
0780                          &state->medium,
0781                          &smc_state->levels[1],
0782                          PPSMC_DISPLAY_WATERMARK_LOW);
0783     if (ret)
0784         return ret;
0785 
0786     ret = cypress_convert_power_level_to_smc(rdev,
0787                          &state->high,
0788                          &smc_state->levels[2],
0789                          PPSMC_DISPLAY_WATERMARK_HIGH);
0790     if (ret)
0791         return ret;
0792 
0793     smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
0794     smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
0795     smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3;
0796 
0797     if (eg_pi->dynamic_ac_timing) {
0798         smc_state->levels[0].ACIndex = 2;
0799         smc_state->levels[1].ACIndex = 3;
0800         smc_state->levels[2].ACIndex = 4;
0801     } else {
0802         smc_state->levels[0].ACIndex = 0;
0803         smc_state->levels[1].ACIndex = 0;
0804         smc_state->levels[2].ACIndex = 0;
0805     }
0806 
0807     rv770_populate_smc_sp(rdev, radeon_state, smc_state);
0808 
0809     return rv770_populate_smc_t(rdev, radeon_state, smc_state);
0810 }
0811 
0812 static void cypress_convert_mc_registers(struct evergreen_mc_reg_entry *entry,
0813                      SMC_Evergreen_MCRegisterSet *data,
0814                      u32 num_entries, u32 valid_flag)
0815 {
0816     u32 i, j;
0817 
0818     for (i = 0, j = 0; j < num_entries; j++) {
0819         if (valid_flag & (1 << j)) {
0820             data->value[i] = cpu_to_be32(entry->mc_data[j]);
0821             i++;
0822         }
0823     }
0824 }
0825 
0826 static void cypress_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
0827                               struct rv7xx_pl *pl,
0828                               SMC_Evergreen_MCRegisterSet *mc_reg_table_data)
0829 {
0830     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
0831     u32 i = 0;
0832 
0833     for (i = 0; i < eg_pi->mc_reg_table.num_entries; i++) {
0834         if (pl->mclk <=
0835             eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
0836             break;
0837     }
0838 
0839     if ((i == eg_pi->mc_reg_table.num_entries) && (i > 0))
0840         --i;
0841 
0842     cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[i],
0843                      mc_reg_table_data,
0844                      eg_pi->mc_reg_table.last,
0845                      eg_pi->mc_reg_table.valid_flag);
0846 }
0847 
0848 static void cypress_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
0849                         struct radeon_ps *radeon_state,
0850                         SMC_Evergreen_MCRegisters *mc_reg_table)
0851 {
0852     struct rv7xx_ps *state = rv770_get_ps(radeon_state);
0853 
0854     cypress_convert_mc_reg_table_entry_to_smc(rdev,
0855                           &state->low,
0856                           &mc_reg_table->data[2]);
0857     cypress_convert_mc_reg_table_entry_to_smc(rdev,
0858                           &state->medium,
0859                           &mc_reg_table->data[3]);
0860     cypress_convert_mc_reg_table_entry_to_smc(rdev,
0861                           &state->high,
0862                           &mc_reg_table->data[4]);
0863 }
0864 
0865 int cypress_upload_sw_state(struct radeon_device *rdev,
0866                 struct radeon_ps *radeon_new_state)
0867 {
0868     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0869     u16 address = pi->state_table_start +
0870         offsetof(RV770_SMC_STATETABLE, driverState);
0871     RV770_SMC_SWSTATE state = { 0 };
0872     int ret;
0873 
0874     ret = cypress_convert_power_state_to_smc(rdev, radeon_new_state, &state);
0875     if (ret)
0876         return ret;
0877 
0878     return rv770_copy_bytes_to_smc(rdev, address, (u8 *)&state,
0879                     sizeof(RV770_SMC_SWSTATE),
0880                     pi->sram_end);
0881 }
0882 
0883 int cypress_upload_mc_reg_table(struct radeon_device *rdev,
0884                 struct radeon_ps *radeon_new_state)
0885 {
0886     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0887     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
0888     SMC_Evergreen_MCRegisters mc_reg_table = { 0 };
0889     u16 address;
0890 
0891     cypress_convert_mc_reg_table_to_smc(rdev, radeon_new_state, &mc_reg_table);
0892 
0893     address = eg_pi->mc_reg_table_start +
0894         (u16)offsetof(SMC_Evergreen_MCRegisters, data[2]);
0895 
0896     return rv770_copy_bytes_to_smc(rdev, address,
0897                        (u8 *)&mc_reg_table.data[2],
0898                        sizeof(SMC_Evergreen_MCRegisterSet) * 3,
0899                        pi->sram_end);
0900 }
0901 
0902 u32 cypress_calculate_burst_time(struct radeon_device *rdev,
0903                  u32 engine_clock, u32 memory_clock)
0904 {
0905     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0906     u32 multiplier = pi->mem_gddr5 ? 1 : 2;
0907     u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2);
0908     u32 burst_time;
0909 
0910     if (result <= 4)
0911         burst_time = 0;
0912     else if (result < 8)
0913         burst_time = result - 4;
0914     else {
0915         burst_time = result / 2 ;
0916         if (burst_time > 18)
0917             burst_time = 18;
0918     }
0919 
0920     return burst_time;
0921 }
0922 
0923 void cypress_program_memory_timing_parameters(struct radeon_device *rdev,
0924                           struct radeon_ps *radeon_new_state)
0925 {
0926     struct rv7xx_ps *new_state = rv770_get_ps(radeon_new_state);
0927     u32 mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);
0928 
0929     mc_arb_burst_time &= ~(STATE1_MASK | STATE2_MASK | STATE3_MASK);
0930 
0931     mc_arb_burst_time |= STATE1(cypress_calculate_burst_time(rdev,
0932                                  new_state->low.sclk,
0933                                  new_state->low.mclk));
0934     mc_arb_burst_time |= STATE2(cypress_calculate_burst_time(rdev,
0935                                  new_state->medium.sclk,
0936                                  new_state->medium.mclk));
0937     mc_arb_burst_time |= STATE3(cypress_calculate_burst_time(rdev,
0938                                  new_state->high.sclk,
0939                                  new_state->high.mclk));
0940 
0941     rv730_program_memory_timing_parameters(rdev, radeon_new_state);
0942 
0943     WREG32(MC_ARB_BURST_TIME, mc_arb_burst_time);
0944 }
0945 
0946 static void cypress_populate_mc_reg_addresses(struct radeon_device *rdev,
0947                           SMC_Evergreen_MCRegisters *mc_reg_table)
0948 {
0949     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
0950     u32 i, j;
0951 
0952     for (i = 0, j = 0; j < eg_pi->mc_reg_table.last; j++) {
0953         if (eg_pi->mc_reg_table.valid_flag & (1 << j)) {
0954             mc_reg_table->address[i].s0 =
0955                 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0);
0956             mc_reg_table->address[i].s1 =
0957                 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1);
0958             i++;
0959         }
0960     }
0961 
0962     mc_reg_table->last = (u8)i;
0963 }
0964 
0965 static void cypress_set_mc_reg_address_table(struct radeon_device *rdev)
0966 {
0967     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
0968     u32 i = 0;
0969 
0970     eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2;
0971     eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2;
0972     i++;
0973 
0974     eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2;
0975     eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2;
0976     i++;
0977 
0978     eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2;
0979     eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2;
0980     i++;
0981 
0982     eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2;
0983     eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2;
0984     i++;
0985 
0986     eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D0_LP >> 2;
0987     eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2;
0988     i++;
0989 
0990     eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2;
0991     eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2;
0992     i++;
0993 
0994     eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2;
0995     eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2;
0996     i++;
0997 
0998     eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2;
0999     eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2;
1000     i++;
1001 
1002     eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
1003     eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_EMRS >> 2;
1004     i++;
1005 
1006     eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
1007     eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS >> 2;
1008     i++;
1009 
1010     eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
1011     eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS1 >> 2;
1012     i++;
1013 
1014     eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC1 >> 2;
1015     eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC1 >> 2;
1016     i++;
1017 
1018     eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RESERVE_M >> 2;
1019     eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RESERVE_M >> 2;
1020     i++;
1021 
1022     eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC3 >> 2;
1023     eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC3 >> 2;
1024     i++;
1025 
1026     eg_pi->mc_reg_table.last = (u8)i;
1027 }
1028 
1029 static void cypress_retrieve_ac_timing_for_one_entry(struct radeon_device *rdev,
1030                              struct evergreen_mc_reg_entry *entry)
1031 {
1032     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1033     u32 i;
1034 
1035     for (i = 0; i < eg_pi->mc_reg_table.last; i++)
1036         entry->mc_data[i] =
1037             RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
1038 
1039 }
1040 
1041 static void cypress_retrieve_ac_timing_for_all_ranges(struct radeon_device *rdev,
1042                               struct atom_memory_clock_range_table *range_table)
1043 {
1044     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1045     u32 i, j;
1046 
1047     for (i = 0; i < range_table->num_entries; i++) {
1048         eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max =
1049             range_table->mclk[i];
1050         radeon_atom_set_ac_timing(rdev, range_table->mclk[i]);
1051         cypress_retrieve_ac_timing_for_one_entry(rdev,
1052                              &eg_pi->mc_reg_table.mc_reg_table_entry[i]);
1053     }
1054 
1055     eg_pi->mc_reg_table.num_entries = range_table->num_entries;
1056     eg_pi->mc_reg_table.valid_flag = 0;
1057 
1058     for (i = 0; i < eg_pi->mc_reg_table.last; i++) {
1059         for (j = 1; j < range_table->num_entries; j++) {
1060             if (eg_pi->mc_reg_table.mc_reg_table_entry[j-1].mc_data[i] !=
1061                 eg_pi->mc_reg_table.mc_reg_table_entry[j].mc_data[i]) {
1062                 eg_pi->mc_reg_table.valid_flag |= (1 << i);
1063                 break;
1064             }
1065         }
1066     }
1067 }
1068 
1069 static int cypress_initialize_mc_reg_table(struct radeon_device *rdev)
1070 {
1071     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1072     u8 module_index = rv770_get_memory_module_index(rdev);
1073     struct atom_memory_clock_range_table range_table = { 0 };
1074     int ret;
1075 
1076     ret = radeon_atom_get_mclk_range_table(rdev,
1077                            pi->mem_gddr5,
1078                            module_index, &range_table);
1079     if (ret)
1080         return ret;
1081 
1082     cypress_retrieve_ac_timing_for_all_ranges(rdev, &range_table);
1083 
1084     return 0;
1085 }
1086 
1087 static void cypress_wait_for_mc_sequencer(struct radeon_device *rdev, u8 value)
1088 {
1089     u32 i, j;
1090     u32 channels = 2;
1091 
1092     if ((rdev->family == CHIP_CYPRESS) ||
1093         (rdev->family == CHIP_HEMLOCK))
1094         channels = 4;
1095     else if (rdev->family == CHIP_CEDAR)
1096         channels = 1;
1097 
1098     for (i = 0; i < channels; i++) {
1099         if ((rdev->family == CHIP_CYPRESS) ||
1100             (rdev->family == CHIP_HEMLOCK)) {
1101             WREG32_P(MC_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);
1102             WREG32_P(MC_CG_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);
1103         } else {
1104             WREG32_P(MC_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);
1105             WREG32_P(MC_CG_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);
1106         }
1107         for (j = 0; j < rdev->usec_timeout; j++) {
1108             if (((RREG32(MC_SEQ_CG) & CG_SEQ_RESP_MASK) >> CG_SEQ_RESP_SHIFT) == value)
1109                 break;
1110             udelay(1);
1111         }
1112     }
1113 }
1114 
1115 static void cypress_force_mc_use_s1(struct radeon_device *rdev,
1116                     struct radeon_ps *radeon_boot_state)
1117 {
1118     struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
1119     u32 strobe_mode;
1120     u32 mc_seq_cg;
1121     int i;
1122 
1123     if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
1124         return;
1125 
1126     radeon_atom_set_ac_timing(rdev, boot_state->low.mclk);
1127     radeon_mc_wait_for_idle(rdev);
1128 
1129     if ((rdev->family == CHIP_CYPRESS) ||
1130         (rdev->family == CHIP_HEMLOCK)) {
1131         WREG32(MC_CONFIG_MCD, 0xf);
1132         WREG32(MC_CG_CONFIG_MCD, 0xf);
1133     } else {
1134         WREG32(MC_CONFIG, 0xf);
1135         WREG32(MC_CG_CONFIG, 0xf);
1136     }
1137 
1138     for (i = 0; i < rdev->num_crtc; i++)
1139         radeon_wait_for_vblank(rdev, i);
1140 
1141     WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);
1142     cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND);
1143 
1144     strobe_mode = cypress_get_strobe_mode_settings(rdev,
1145                                boot_state->low.mclk);
1146 
1147     mc_seq_cg = CG_SEQ_REQ(MC_CG_SEQ_DRAMCONF_S1);
1148     mc_seq_cg |= SEQ_CG_RESP(strobe_mode);
1149     WREG32(MC_SEQ_CG, mc_seq_cg);
1150 
1151     for (i = 0; i < rdev->usec_timeout; i++) {
1152         if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
1153             break;
1154         udelay(1);
1155     }
1156 
1157     mc_seq_cg &= ~CG_SEQ_REQ_MASK;
1158     mc_seq_cg |= CG_SEQ_REQ(MC_CG_SEQ_YCLK_RESUME);
1159     WREG32(MC_SEQ_CG, mc_seq_cg);
1160 
1161     cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME);
1162 }
1163 
1164 static void cypress_copy_ac_timing_from_s1_to_s0(struct radeon_device *rdev)
1165 {
1166     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1167     u32 value;
1168     u32 i;
1169 
1170     for (i = 0; i < eg_pi->mc_reg_table.last; i++) {
1171         value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
1172         WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value);
1173     }
1174 }
1175 
1176 static void cypress_force_mc_use_s0(struct radeon_device *rdev,
1177                     struct radeon_ps *radeon_boot_state)
1178 {
1179     struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
1180     u32 strobe_mode;
1181     u32 mc_seq_cg;
1182     int i;
1183 
1184     cypress_copy_ac_timing_from_s1_to_s0(rdev);
1185     radeon_mc_wait_for_idle(rdev);
1186 
1187     if ((rdev->family == CHIP_CYPRESS) ||
1188         (rdev->family == CHIP_HEMLOCK)) {
1189         WREG32(MC_CONFIG_MCD, 0xf);
1190         WREG32(MC_CG_CONFIG_MCD, 0xf);
1191     } else {
1192         WREG32(MC_CONFIG, 0xf);
1193         WREG32(MC_CG_CONFIG, 0xf);
1194     }
1195 
1196     for (i = 0; i < rdev->num_crtc; i++)
1197         radeon_wait_for_vblank(rdev, i);
1198 
1199     WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);
1200     cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND);
1201 
1202     strobe_mode = cypress_get_strobe_mode_settings(rdev,
1203                                boot_state->low.mclk);
1204 
1205     mc_seq_cg = CG_SEQ_REQ(MC_CG_SEQ_DRAMCONF_S0);
1206     mc_seq_cg |= SEQ_CG_RESP(strobe_mode);
1207     WREG32(MC_SEQ_CG, mc_seq_cg);
1208 
1209     for (i = 0; i < rdev->usec_timeout; i++) {
1210         if (!(RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE))
1211             break;
1212         udelay(1);
1213     }
1214 
1215     mc_seq_cg &= ~CG_SEQ_REQ_MASK;
1216     mc_seq_cg |= CG_SEQ_REQ(MC_CG_SEQ_YCLK_RESUME);
1217     WREG32(MC_SEQ_CG, mc_seq_cg);
1218 
1219     cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME);
1220 }
1221 
1222 static int cypress_populate_initial_mvdd_value(struct radeon_device *rdev,
1223                            RV770_SMC_VOLTAGE_VALUE *voltage)
1224 {
1225     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1226 
1227     voltage->index = eg_pi->mvdd_high_index;
1228     voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
1229 
1230     return 0;
1231 }
1232 
1233 int cypress_populate_smc_initial_state(struct radeon_device *rdev,
1234                        struct radeon_ps *radeon_initial_state,
1235                        RV770_SMC_STATETABLE *table)
1236 {
1237     struct rv7xx_ps *initial_state = rv770_get_ps(radeon_initial_state);
1238     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1239     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1240     u32 a_t;
1241 
1242     table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1243         cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl);
1244     table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1245         cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2);
1246     table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1247         cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl);
1248     table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1249         cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl_2);
1250     table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1251         cpu_to_be32(pi->clk_regs.rv770.mclk_pwrmgt_cntl);
1252     table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =
1253         cpu_to_be32(pi->clk_regs.rv770.dll_cntl);
1254 
1255     table->initialState.levels[0].mclk.mclk770.vMPLL_SS =
1256         cpu_to_be32(pi->clk_regs.rv770.mpll_ss1);
1257     table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
1258         cpu_to_be32(pi->clk_regs.rv770.mpll_ss2);
1259 
1260     table->initialState.levels[0].mclk.mclk770.mclk_value =
1261         cpu_to_be32(initial_state->low.mclk);
1262 
1263     table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1264         cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl);
1265     table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1266         cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_2);
1267     table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1268         cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_3);
1269     table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
1270         cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum);
1271     table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
1272         cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum_2);
1273 
1274     table->initialState.levels[0].sclk.sclk_value =
1275         cpu_to_be32(initial_state->low.sclk);
1276 
1277     table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
1278 
1279     table->initialState.levels[0].ACIndex = 0;
1280 
1281     cypress_populate_voltage_value(rdev,
1282                        &eg_pi->vddc_voltage_table,
1283                        initial_state->low.vddc,
1284                        &table->initialState.levels[0].vddc);
1285 
1286     if (eg_pi->vddci_control)
1287         cypress_populate_voltage_value(rdev,
1288                            &eg_pi->vddci_voltage_table,
1289                            initial_state->low.vddci,
1290                            &table->initialState.levels[0].vddci);
1291 
1292     cypress_populate_initial_mvdd_value(rdev,
1293                         &table->initialState.levels[0].mvdd);
1294 
1295     a_t = CG_R(0xffff) | CG_L(0);
1296     table->initialState.levels[0].aT = cpu_to_be32(a_t);
1297 
1298     table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
1299 
1300 
1301     if (pi->boot_in_gen2)
1302         table->initialState.levels[0].gen2PCIE = 1;
1303     else
1304         table->initialState.levels[0].gen2PCIE = 0;
1305     if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
1306         table->initialState.levels[0].gen2XSP = 1;
1307     else
1308         table->initialState.levels[0].gen2XSP = 0;
1309 
1310     if (pi->mem_gddr5) {
1311         table->initialState.levels[0].strobeMode =
1312             cypress_get_strobe_mode_settings(rdev,
1313                              initial_state->low.mclk);
1314 
1315         if (initial_state->low.mclk > pi->mclk_edc_enable_threshold)
1316             table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG;
1317         else
1318             table->initialState.levels[0].mcFlags =  0;
1319     }
1320 
1321     table->initialState.levels[1] = table->initialState.levels[0];
1322     table->initialState.levels[2] = table->initialState.levels[0];
1323 
1324     table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
1325 
1326     return 0;
1327 }
1328 
1329 int cypress_populate_smc_acpi_state(struct radeon_device *rdev,
1330                     RV770_SMC_STATETABLE *table)
1331 {
1332     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1333     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1334     u32 mpll_ad_func_cntl =
1335         pi->clk_regs.rv770.mpll_ad_func_cntl;
1336     u32 mpll_ad_func_cntl_2 =
1337         pi->clk_regs.rv770.mpll_ad_func_cntl_2;
1338     u32 mpll_dq_func_cntl =
1339         pi->clk_regs.rv770.mpll_dq_func_cntl;
1340     u32 mpll_dq_func_cntl_2 =
1341         pi->clk_regs.rv770.mpll_dq_func_cntl_2;
1342     u32 spll_func_cntl =
1343         pi->clk_regs.rv770.cg_spll_func_cntl;
1344     u32 spll_func_cntl_2 =
1345         pi->clk_regs.rv770.cg_spll_func_cntl_2;
1346     u32 spll_func_cntl_3 =
1347         pi->clk_regs.rv770.cg_spll_func_cntl_3;
1348     u32 mclk_pwrmgt_cntl =
1349         pi->clk_regs.rv770.mclk_pwrmgt_cntl;
1350     u32 dll_cntl =
1351         pi->clk_regs.rv770.dll_cntl;
1352 
1353     table->ACPIState = table->initialState;
1354 
1355     table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
1356 
1357     if (pi->acpi_vddc) {
1358         cypress_populate_voltage_value(rdev,
1359                            &eg_pi->vddc_voltage_table,
1360                            pi->acpi_vddc,
1361                            &table->ACPIState.levels[0].vddc);
1362         if (pi->pcie_gen2) {
1363             if (pi->acpi_pcie_gen2)
1364                 table->ACPIState.levels[0].gen2PCIE = 1;
1365             else
1366                 table->ACPIState.levels[0].gen2PCIE = 0;
1367         } else
1368             table->ACPIState.levels[0].gen2PCIE = 0;
1369         if (pi->acpi_pcie_gen2)
1370             table->ACPIState.levels[0].gen2XSP = 1;
1371         else
1372             table->ACPIState.levels[0].gen2XSP = 0;
1373     } else {
1374         cypress_populate_voltage_value(rdev,
1375                            &eg_pi->vddc_voltage_table,
1376                            pi->min_vddc_in_table,
1377                            &table->ACPIState.levels[0].vddc);
1378         table->ACPIState.levels[0].gen2PCIE = 0;
1379     }
1380 
1381     if (eg_pi->acpi_vddci) {
1382         if (eg_pi->vddci_control) {
1383             cypress_populate_voltage_value(rdev,
1384                                &eg_pi->vddci_voltage_table,
1385                                eg_pi->acpi_vddci,
1386                                &table->ACPIState.levels[0].vddci);
1387         }
1388     }
1389 
1390     mpll_ad_func_cntl &= ~PDNB;
1391 
1392     mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN;
1393 
1394     if (pi->mem_gddr5)
1395         mpll_dq_func_cntl &= ~PDNB;
1396     mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS;
1397 
1398     mclk_pwrmgt_cntl |= (MRDCKA0_RESET |
1399                  MRDCKA1_RESET |
1400                  MRDCKB0_RESET |
1401                  MRDCKB1_RESET |
1402                  MRDCKC0_RESET |
1403                  MRDCKC1_RESET |
1404                  MRDCKD0_RESET |
1405                  MRDCKD1_RESET);
1406 
1407     mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
1408                   MRDCKA1_PDNB |
1409                   MRDCKB0_PDNB |
1410                   MRDCKB1_PDNB |
1411                   MRDCKC0_PDNB |
1412                   MRDCKC1_PDNB |
1413                   MRDCKD0_PDNB |
1414                   MRDCKD1_PDNB);
1415 
1416     dll_cntl |= (MRDCKA0_BYPASS |
1417              MRDCKA1_BYPASS |
1418              MRDCKB0_BYPASS |
1419              MRDCKB1_BYPASS |
1420              MRDCKC0_BYPASS |
1421              MRDCKC1_BYPASS |
1422              MRDCKD0_BYPASS |
1423              MRDCKD1_BYPASS);
1424 
1425     /* evergreen only */
1426     if (rdev->family <= CHIP_HEMLOCK)
1427         spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
1428 
1429     spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
1430     spll_func_cntl_2 |= SCLK_MUX_SEL(4);
1431 
1432     table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1433         cpu_to_be32(mpll_ad_func_cntl);
1434     table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1435         cpu_to_be32(mpll_ad_func_cntl_2);
1436     table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1437         cpu_to_be32(mpll_dq_func_cntl);
1438     table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1439         cpu_to_be32(mpll_dq_func_cntl_2);
1440     table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1441         cpu_to_be32(mclk_pwrmgt_cntl);
1442     table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
1443 
1444     table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
1445 
1446     table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1447         cpu_to_be32(spll_func_cntl);
1448     table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1449         cpu_to_be32(spll_func_cntl_2);
1450     table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1451         cpu_to_be32(spll_func_cntl_3);
1452 
1453     table->ACPIState.levels[0].sclk.sclk_value = 0;
1454 
1455     cypress_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
1456 
1457     if (eg_pi->dynamic_ac_timing)
1458         table->ACPIState.levels[0].ACIndex = 1;
1459 
1460     table->ACPIState.levels[1] = table->ACPIState.levels[0];
1461     table->ACPIState.levels[2] = table->ACPIState.levels[0];
1462 
1463     return 0;
1464 }
1465 
1466 static void cypress_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
1467                               struct atom_voltage_table *voltage_table)
1468 {
1469     unsigned int i, diff;
1470 
1471     if (voltage_table->count <= MAX_NO_VREG_STEPS)
1472         return;
1473 
1474     diff = voltage_table->count - MAX_NO_VREG_STEPS;
1475 
1476     for (i= 0; i < MAX_NO_VREG_STEPS; i++)
1477         voltage_table->entries[i] = voltage_table->entries[i + diff];
1478 
1479     voltage_table->count = MAX_NO_VREG_STEPS;
1480 }
1481 
1482 int cypress_construct_voltage_tables(struct radeon_device *rdev)
1483 {
1484     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1485     int ret;
1486 
1487     ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0,
1488                         &eg_pi->vddc_voltage_table);
1489     if (ret)
1490         return ret;
1491 
1492     if (eg_pi->vddc_voltage_table.count > MAX_NO_VREG_STEPS)
1493         cypress_trim_voltage_table_to_fit_state_table(rdev,
1494                                   &eg_pi->vddc_voltage_table);
1495 
1496     if (eg_pi->vddci_control) {
1497         ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0,
1498                             &eg_pi->vddci_voltage_table);
1499         if (ret)
1500             return ret;
1501 
1502         if (eg_pi->vddci_voltage_table.count > MAX_NO_VREG_STEPS)
1503             cypress_trim_voltage_table_to_fit_state_table(rdev,
1504                                       &eg_pi->vddci_voltage_table);
1505     }
1506 
1507     return 0;
1508 }
1509 
1510 static void cypress_populate_smc_voltage_table(struct radeon_device *rdev,
1511                            struct atom_voltage_table *voltage_table,
1512                            RV770_SMC_STATETABLE *table)
1513 {
1514     unsigned int i;
1515 
1516     for (i = 0; i < voltage_table->count; i++) {
1517         table->highSMIO[i] = 0;
1518         table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
1519     }
1520 }
1521 
1522 int cypress_populate_smc_voltage_tables(struct radeon_device *rdev,
1523                     RV770_SMC_STATETABLE *table)
1524 {
1525     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1526     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1527     unsigned char i;
1528 
1529     if (eg_pi->vddc_voltage_table.count) {
1530         cypress_populate_smc_voltage_table(rdev,
1531                            &eg_pi->vddc_voltage_table,
1532                            table);
1533 
1534         table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDC] = 0;
1535         table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDC] =
1536             cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
1537 
1538         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
1539             if (pi->max_vddc_in_table <=
1540                 eg_pi->vddc_voltage_table.entries[i].value) {
1541                 table->maxVDDCIndexInPPTable = i;
1542                 break;
1543             }
1544         }
1545     }
1546 
1547     if (eg_pi->vddci_voltage_table.count) {
1548         cypress_populate_smc_voltage_table(rdev,
1549                            &eg_pi->vddci_voltage_table,
1550                            table);
1551 
1552         table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0;
1553         table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] =
1554             cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
1555     }
1556 
1557     return 0;
1558 }
1559 
1560 static u32 cypress_get_mclk_split_point(struct atom_memory_info *memory_info)
1561 {
1562     if ((memory_info->mem_type == MEM_TYPE_GDDR3) ||
1563         (memory_info->mem_type == MEM_TYPE_DDR3))
1564         return 30000;
1565 
1566     return 0;
1567 }
1568 
1569 int cypress_get_mvdd_configuration(struct radeon_device *rdev)
1570 {
1571     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1572     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1573     u8 module_index;
1574     struct atom_memory_info memory_info;
1575     u32 tmp = RREG32(GENERAL_PWRMGT);
1576 
1577     if (!(tmp & BACKBIAS_PAD_EN)) {
1578         eg_pi->mvdd_high_index = 0;
1579         eg_pi->mvdd_low_index = 1;
1580         pi->mvdd_control = false;
1581         return 0;
1582     }
1583 
1584     if (tmp & BACKBIAS_VALUE)
1585         eg_pi->mvdd_high_index = 1;
1586     else
1587         eg_pi->mvdd_high_index = 0;
1588 
1589     eg_pi->mvdd_low_index =
1590         (eg_pi->mvdd_high_index == 0) ? 1 : 0;
1591 
1592     module_index = rv770_get_memory_module_index(rdev);
1593 
1594     if (radeon_atom_get_memory_info(rdev, module_index, &memory_info)) {
1595         pi->mvdd_control = false;
1596         return 0;
1597     }
1598 
1599     pi->mvdd_split_frequency =
1600         cypress_get_mclk_split_point(&memory_info);
1601 
1602     if (pi->mvdd_split_frequency == 0) {
1603         pi->mvdd_control = false;
1604         return 0;
1605     }
1606 
1607     return 0;
1608 }
1609 
1610 static int cypress_init_smc_table(struct radeon_device *rdev,
1611                   struct radeon_ps *radeon_boot_state)
1612 {
1613     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1614     RV770_SMC_STATETABLE *table = &pi->smc_statetable;
1615     int ret;
1616 
1617     memset(table, 0, sizeof(RV770_SMC_STATETABLE));
1618 
1619     cypress_populate_smc_voltage_tables(rdev, table);
1620 
1621     switch (rdev->pm.int_thermal_type) {
1622     case THERMAL_TYPE_EVERGREEN:
1623     case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
1624         table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
1625         break;
1626     case THERMAL_TYPE_NONE:
1627         table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
1628         break;
1629     default:
1630         table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
1631         break;
1632     }
1633 
1634     if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1635         table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1636 
1637     if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1638         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
1639 
1640     if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1641         table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1642 
1643     if (pi->mem_gddr5)
1644         table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1645 
1646     ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table);
1647     if (ret)
1648         return ret;
1649 
1650     ret = cypress_populate_smc_acpi_state(rdev, table);
1651     if (ret)
1652         return ret;
1653 
1654     table->driverState = table->initialState;
1655 
1656     return rv770_copy_bytes_to_smc(rdev,
1657                        pi->state_table_start,
1658                        (u8 *)table, sizeof(RV770_SMC_STATETABLE),
1659                        pi->sram_end);
1660 }
1661 
1662 int cypress_populate_mc_reg_table(struct radeon_device *rdev,
1663                   struct radeon_ps *radeon_boot_state)
1664 {
1665     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1666     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1667     struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
1668     SMC_Evergreen_MCRegisters mc_reg_table = { 0 };
1669 
1670     rv770_write_smc_soft_register(rdev,
1671                       RV770_SMC_SOFT_REGISTER_seq_index, 1);
1672 
1673     cypress_populate_mc_reg_addresses(rdev, &mc_reg_table);
1674 
1675     cypress_convert_mc_reg_table_entry_to_smc(rdev,
1676                           &boot_state->low,
1677                           &mc_reg_table.data[0]);
1678 
1679     cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[0],
1680                      &mc_reg_table.data[1], eg_pi->mc_reg_table.last,
1681                      eg_pi->mc_reg_table.valid_flag);
1682 
1683     cypress_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, &mc_reg_table);
1684 
1685     return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start,
1686                        (u8 *)&mc_reg_table, sizeof(SMC_Evergreen_MCRegisters),
1687                        pi->sram_end);
1688 }
1689 
1690 int cypress_get_table_locations(struct radeon_device *rdev)
1691 {
1692     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1693     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1694     u32 tmp;
1695     int ret;
1696 
1697     ret = rv770_read_smc_sram_dword(rdev,
1698                     EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
1699                     EVERGREEN_SMC_FIRMWARE_HEADER_stateTable,
1700                     &tmp, pi->sram_end);
1701     if (ret)
1702         return ret;
1703 
1704     pi->state_table_start = (u16)tmp;
1705 
1706     ret = rv770_read_smc_sram_dword(rdev,
1707                     EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
1708                     EVERGREEN_SMC_FIRMWARE_HEADER_softRegisters,
1709                     &tmp, pi->sram_end);
1710     if (ret)
1711         return ret;
1712 
1713     pi->soft_regs_start = (u16)tmp;
1714 
1715     ret = rv770_read_smc_sram_dword(rdev,
1716                     EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
1717                     EVERGREEN_SMC_FIRMWARE_HEADER_mcRegisterTable,
1718                     &tmp, pi->sram_end);
1719     if (ret)
1720         return ret;
1721 
1722     eg_pi->mc_reg_table_start = (u16)tmp;
1723 
1724     return 0;
1725 }
1726 
1727 void cypress_enable_display_gap(struct radeon_device *rdev)
1728 {
1729     u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
1730 
1731     tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
1732     tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1733         DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
1734 
1735     tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
1736     tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
1737         DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
1738     WREG32(CG_DISPLAY_GAP_CNTL, tmp);
1739 }
1740 
1741 static void cypress_program_display_gap(struct radeon_device *rdev)
1742 {
1743     u32 tmp, pipe;
1744     int i;
1745 
1746     tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
1747     if (rdev->pm.dpm.new_active_crtc_count > 0)
1748         tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1749     else
1750         tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1751 
1752     if (rdev->pm.dpm.new_active_crtc_count > 1)
1753         tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1754     else
1755         tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1756 
1757     WREG32(CG_DISPLAY_GAP_CNTL, tmp);
1758 
1759     tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
1760     pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
1761 
1762     if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
1763         (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
1764         /* find the first active crtc */
1765         for (i = 0; i < rdev->num_crtc; i++) {
1766             if (rdev->pm.dpm.new_active_crtcs & (1 << i))
1767                 break;
1768         }
1769         if (i == rdev->num_crtc)
1770             pipe = 0;
1771         else
1772             pipe = i;
1773 
1774         tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
1775         tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
1776         WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
1777     }
1778 
1779     cypress_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
1780 }
1781 
1782 void cypress_dpm_setup_asic(struct radeon_device *rdev)
1783 {
1784     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1785 
1786     rv740_read_clock_registers(rdev);
1787     rv770_read_voltage_smio_registers(rdev);
1788     rv770_get_max_vddc(rdev);
1789     rv770_get_memory_type(rdev);
1790 
1791     if (eg_pi->pcie_performance_request)
1792         eg_pi->pcie_performance_request_registered = false;
1793 
1794     if (eg_pi->pcie_performance_request)
1795         cypress_advertise_gen2_capability(rdev);
1796 
1797     rv770_get_pcie_gen2_status(rdev);
1798 
1799     rv770_enable_acpi_pm(rdev);
1800 }
1801 
1802 int cypress_dpm_enable(struct radeon_device *rdev)
1803 {
1804     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1805     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1806     struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1807     int ret;
1808 
1809     if (pi->gfx_clock_gating)
1810         rv770_restore_cgcg(rdev);
1811 
1812     if (rv770_dpm_enabled(rdev))
1813         return -EINVAL;
1814 
1815     if (pi->voltage_control) {
1816         rv770_enable_voltage_control(rdev, true);
1817         ret = cypress_construct_voltage_tables(rdev);
1818         if (ret) {
1819             DRM_ERROR("cypress_construct_voltage_tables failed\n");
1820             return ret;
1821         }
1822     }
1823 
1824     if (pi->mvdd_control) {
1825         ret = cypress_get_mvdd_configuration(rdev);
1826         if (ret) {
1827             DRM_ERROR("cypress_get_mvdd_configuration failed\n");
1828             return ret;
1829         }
1830     }
1831 
1832     if (eg_pi->dynamic_ac_timing) {
1833         cypress_set_mc_reg_address_table(rdev);
1834         cypress_force_mc_use_s0(rdev, boot_ps);
1835         ret = cypress_initialize_mc_reg_table(rdev);
1836         if (ret)
1837             eg_pi->dynamic_ac_timing = false;
1838         cypress_force_mc_use_s1(rdev, boot_ps);
1839     }
1840 
1841     if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1842         rv770_enable_backbias(rdev, true);
1843 
1844     if (pi->dynamic_ss)
1845         cypress_enable_spread_spectrum(rdev, true);
1846 
1847     if (pi->thermal_protection)
1848         rv770_enable_thermal_protection(rdev, true);
1849 
1850     rv770_setup_bsp(rdev);
1851     rv770_program_git(rdev);
1852     rv770_program_tp(rdev);
1853     rv770_program_tpp(rdev);
1854     rv770_program_sstp(rdev);
1855     rv770_program_engine_speed_parameters(rdev);
1856     cypress_enable_display_gap(rdev);
1857     rv770_program_vc(rdev);
1858 
1859     if (pi->dynamic_pcie_gen2)
1860         cypress_enable_dynamic_pcie_gen2(rdev, true);
1861 
1862     ret = rv770_upload_firmware(rdev);
1863     if (ret) {
1864         DRM_ERROR("rv770_upload_firmware failed\n");
1865         return ret;
1866     }
1867 
1868     ret = cypress_get_table_locations(rdev);
1869     if (ret) {
1870         DRM_ERROR("cypress_get_table_locations failed\n");
1871         return ret;
1872     }
1873     ret = cypress_init_smc_table(rdev, boot_ps);
1874     if (ret) {
1875         DRM_ERROR("cypress_init_smc_table failed\n");
1876         return ret;
1877     }
1878     if (eg_pi->dynamic_ac_timing) {
1879         ret = cypress_populate_mc_reg_table(rdev, boot_ps);
1880         if (ret) {
1881             DRM_ERROR("cypress_populate_mc_reg_table failed\n");
1882             return ret;
1883         }
1884     }
1885 
1886     cypress_program_response_times(rdev);
1887 
1888     r7xx_start_smc(rdev);
1889 
1890     ret = cypress_notify_smc_display_change(rdev, false);
1891     if (ret) {
1892         DRM_ERROR("cypress_notify_smc_display_change failed\n");
1893         return ret;
1894     }
1895     cypress_enable_sclk_control(rdev, true);
1896 
1897     if (eg_pi->memory_transition)
1898         cypress_enable_mclk_control(rdev, true);
1899 
1900     cypress_start_dpm(rdev);
1901 
1902     if (pi->gfx_clock_gating)
1903         cypress_gfx_clock_gating_enable(rdev, true);
1904 
1905     if (pi->mg_clock_gating)
1906         cypress_mg_clock_gating_enable(rdev, true);
1907 
1908     rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1909 
1910     return 0;
1911 }
1912 
1913 void cypress_dpm_disable(struct radeon_device *rdev)
1914 {
1915     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1916     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1917     struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1918 
1919     if (!rv770_dpm_enabled(rdev))
1920         return;
1921 
1922     rv770_clear_vc(rdev);
1923 
1924     if (pi->thermal_protection)
1925         rv770_enable_thermal_protection(rdev, false);
1926 
1927     if (pi->dynamic_pcie_gen2)
1928         cypress_enable_dynamic_pcie_gen2(rdev, false);
1929 
1930     if (rdev->irq.installed &&
1931         r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1932         rdev->irq.dpm_thermal = false;
1933         radeon_irq_set(rdev);
1934     }
1935 
1936     if (pi->gfx_clock_gating)
1937         cypress_gfx_clock_gating_enable(rdev, false);
1938 
1939     if (pi->mg_clock_gating)
1940         cypress_mg_clock_gating_enable(rdev, false);
1941 
1942     rv770_stop_dpm(rdev);
1943     r7xx_stop_smc(rdev);
1944 
1945     cypress_enable_spread_spectrum(rdev, false);
1946 
1947     if (eg_pi->dynamic_ac_timing)
1948         cypress_force_mc_use_s1(rdev, boot_ps);
1949 
1950     rv770_reset_smio_status(rdev);
1951 }
1952 
1953 int cypress_dpm_set_power_state(struct radeon_device *rdev)
1954 {
1955     struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1956     struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
1957     struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
1958     int ret;
1959 
1960     ret = rv770_restrict_performance_levels_before_switch(rdev);
1961     if (ret) {
1962         DRM_ERROR("rv770_restrict_performance_levels_before_switch failed\n");
1963         return ret;
1964     }
1965     if (eg_pi->pcie_performance_request)
1966         cypress_notify_link_speed_change_before_state_change(rdev, new_ps, old_ps);
1967 
1968     rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1969     ret = rv770_halt_smc(rdev);
1970     if (ret) {
1971         DRM_ERROR("rv770_halt_smc failed\n");
1972         return ret;
1973     }
1974     ret = cypress_upload_sw_state(rdev, new_ps);
1975     if (ret) {
1976         DRM_ERROR("cypress_upload_sw_state failed\n");
1977         return ret;
1978     }
1979     if (eg_pi->dynamic_ac_timing) {
1980         ret = cypress_upload_mc_reg_table(rdev, new_ps);
1981         if (ret) {
1982             DRM_ERROR("cypress_upload_mc_reg_table failed\n");
1983             return ret;
1984         }
1985     }
1986 
1987     cypress_program_memory_timing_parameters(rdev, new_ps);
1988 
1989     ret = rv770_resume_smc(rdev);
1990     if (ret) {
1991         DRM_ERROR("rv770_resume_smc failed\n");
1992         return ret;
1993     }
1994     ret = rv770_set_sw_state(rdev);
1995     if (ret) {
1996         DRM_ERROR("rv770_set_sw_state failed\n");
1997         return ret;
1998     }
1999     rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
2000 
2001     if (eg_pi->pcie_performance_request)
2002         cypress_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
2003 
2004     return 0;
2005 }
2006 
2007 #if 0
2008 void cypress_dpm_reset_asic(struct radeon_device *rdev)
2009 {
2010     rv770_restrict_performance_levels_before_switch(rdev);
2011     rv770_set_boot_state(rdev);
2012 }
2013 #endif
2014 
2015 void cypress_dpm_display_configuration_changed(struct radeon_device *rdev)
2016 {
2017     cypress_program_display_gap(rdev);
2018 }
2019 
2020 int cypress_dpm_init(struct radeon_device *rdev)
2021 {
2022     struct rv7xx_power_info *pi;
2023     struct evergreen_power_info *eg_pi;
2024     struct atom_clock_dividers dividers;
2025     int ret;
2026 
2027     eg_pi = kzalloc(sizeof(struct evergreen_power_info), GFP_KERNEL);
2028     if (eg_pi == NULL)
2029         return -ENOMEM;
2030     rdev->pm.dpm.priv = eg_pi;
2031     pi = &eg_pi->rv7xx;
2032 
2033     rv770_get_max_vddc(rdev);
2034 
2035     eg_pi->ulv.supported = false;
2036     pi->acpi_vddc = 0;
2037     eg_pi->acpi_vddci = 0;
2038     pi->min_vddc_in_table = 0;
2039     pi->max_vddc_in_table = 0;
2040 
2041     ret = r600_get_platform_caps(rdev);
2042     if (ret)
2043         return ret;
2044 
2045     ret = rv7xx_parse_power_table(rdev);
2046     if (ret)
2047         return ret;
2048 
2049     if (rdev->pm.dpm.voltage_response_time == 0)
2050         rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
2051     if (rdev->pm.dpm.backbias_response_time == 0)
2052         rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
2053 
2054     ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2055                          0, false, &dividers);
2056     if (ret)
2057         pi->ref_div = dividers.ref_div + 1;
2058     else
2059         pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
2060 
2061     pi->mclk_strobe_mode_threshold = 40000;
2062     pi->mclk_edc_enable_threshold = 40000;
2063     eg_pi->mclk_edc_wr_enable_threshold = 40000;
2064 
2065     pi->rlp = RV770_RLP_DFLT;
2066     pi->rmp = RV770_RMP_DFLT;
2067     pi->lhp = RV770_LHP_DFLT;
2068     pi->lmp = RV770_LMP_DFLT;
2069 
2070     pi->voltage_control =
2071         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
2072 
2073     pi->mvdd_control =
2074         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
2075 
2076     eg_pi->vddci_control =
2077         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
2078 
2079     rv770_get_engine_memory_ss(rdev);
2080 
2081     pi->asi = RV770_ASI_DFLT;
2082     pi->pasi = CYPRESS_HASI_DFLT;
2083     pi->vrc = CYPRESS_VRC_DFLT;
2084 
2085     pi->power_gating = false;
2086 
2087     if ((rdev->family == CHIP_CYPRESS) ||
2088         (rdev->family == CHIP_HEMLOCK))
2089         pi->gfx_clock_gating = false;
2090     else
2091         pi->gfx_clock_gating = true;
2092 
2093     pi->mg_clock_gating = true;
2094     pi->mgcgtssm = true;
2095     eg_pi->ls_clock_gating = false;
2096     eg_pi->sclk_deep_sleep = false;
2097 
2098     pi->dynamic_pcie_gen2 = true;
2099 
2100     if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
2101         pi->thermal_protection = true;
2102     else
2103         pi->thermal_protection = false;
2104 
2105     pi->display_gap = true;
2106 
2107     if (rdev->flags & RADEON_IS_MOBILITY)
2108         pi->dcodt = true;
2109     else
2110         pi->dcodt = false;
2111 
2112     pi->ulps = true;
2113 
2114     eg_pi->dynamic_ac_timing = true;
2115     eg_pi->abm = true;
2116     eg_pi->mcls = true;
2117     eg_pi->light_sleep = true;
2118     eg_pi->memory_transition = true;
2119 #if defined(CONFIG_ACPI)
2120     eg_pi->pcie_performance_request =
2121         radeon_acpi_is_pcie_performance_request_supported(rdev);
2122 #else
2123     eg_pi->pcie_performance_request = false;
2124 #endif
2125 
2126     if ((rdev->family == CHIP_CYPRESS) ||
2127         (rdev->family == CHIP_HEMLOCK) ||
2128         (rdev->family == CHIP_JUNIPER))
2129         eg_pi->dll_default_on = true;
2130     else
2131         eg_pi->dll_default_on = false;
2132 
2133     eg_pi->sclk_deep_sleep = false;
2134     pi->mclk_stutter_mode_threshold = 0;
2135 
2136     pi->sram_end = SMC_RAM_END;
2137 
2138     return 0;
2139 }
2140 
2141 void cypress_dpm_fini(struct radeon_device *rdev)
2142 {
2143     int i;
2144 
2145     for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2146         kfree(rdev->pm.dpm.ps[i].ps_priv);
2147     }
2148     kfree(rdev->pm.dpm.ps);
2149     kfree(rdev->pm.dpm.priv);
2150 }
2151 
2152 bool cypress_dpm_vblank_too_short(struct radeon_device *rdev)
2153 {
2154     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2155     u32 vblank_time = r600_dpm_get_vblank_time(rdev);
2156     /* we never hit the non-gddr5 limit so disable it */
2157     u32 switch_limit = pi->mem_gddr5 ? 450 : 0;
2158 
2159     if (vblank_time < switch_limit)
2160         return true;
2161     else
2162         return false;
2163 
2164 }
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