drm/radeon/ci_dpm.h

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __CI_DPM_H__
0024 #define __CI_DPM_H__
0025
0026 #include "ppsmc.h"
0027 #include "radeon.h"
0028
0029 #define SMU__NUM_SCLK_DPM_STATE  8
0030 #define SMU__NUM_MCLK_DPM_LEVELS 6
0031 #define SMU__NUM_LCLK_DPM_LEVELS 8
0032 #define SMU__NUM_PCIE_DPM_LEVELS 8
0033 #include "smu7_discrete.h"
0034
0035 #define CISLANDS_MAX_HARDWARE_POWERLEVELS 2
0036
0037 #define CISLANDS_UNUSED_GPIO_PIN 0x7F
0038
0039 struct ci_pl {
0040     u32 mclk;
0041     u32 sclk;
0042     enum radeon_pcie_gen pcie_gen;
0043     u16 pcie_lane;
0044 };
0045
0046 struct ci_ps {
0047     u16 performance_level_count;
0048     bool dc_compatible;
0049     u32 sclk_t;
0050     struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS];
0051 };
0052
0053 struct ci_dpm_level {
0054     bool enabled;
0055     u32 value;
0056     u32 param1;
0057 };
0058
0059 #define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5
0060 #define MAX_REGULAR_DPM_NUMBER 8
0061 #define CISLAND_MINIMUM_ENGINE_CLOCK 800
0062
0063 struct ci_single_dpm_table {
0064     u32 count;
0065     struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
0066 };
0067
0068 struct ci_dpm_table {
0069     struct ci_single_dpm_table sclk_table;
0070     struct ci_single_dpm_table mclk_table;
0071     struct ci_single_dpm_table pcie_speed_table;
0072     struct ci_single_dpm_table vddc_table;
0073     struct ci_single_dpm_table vddci_table;
0074     struct ci_single_dpm_table mvdd_table;
0075 };
0076
0077 struct ci_mc_reg_entry {
0078     u32 mclk_max;
0079     u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
0080 };
0081
0082 struct ci_mc_reg_table {
0083     u8 last;
0084     u8 num_entries;
0085     u16 valid_flag;
0086     struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
0087     SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
0088 };
0089
0090 struct ci_ulv_parm
0091 {
0092     bool supported;
0093     u32 cg_ulv_parameter;
0094     u32 volt_change_delay;
0095     struct ci_pl pl;
0096 };
0097
0098 #define CISLANDS_MAX_LEAKAGE_COUNT  8
0099
0100 struct ci_leakage_voltage {
0101     u16 count;
0102     u16 leakage_id[CISLANDS_MAX_LEAKAGE_COUNT];
0103     u16 actual_voltage[CISLANDS_MAX_LEAKAGE_COUNT];
0104 };
0105
0106 struct ci_dpm_level_enable_mask {
0107     u32 uvd_dpm_enable_mask;
0108     u32 vce_dpm_enable_mask;
0109     u32 acp_dpm_enable_mask;
0110     u32 samu_dpm_enable_mask;
0111     u32 sclk_dpm_enable_mask;
0112     u32 mclk_dpm_enable_mask;
0113     u32 pcie_dpm_enable_mask;
0114 };
0115
0116 struct ci_vbios_boot_state
0117 {
0118     u16 mvdd_bootup_value;
0119     u16 vddc_bootup_value;
0120     u16 vddci_bootup_value;
0121     u32 sclk_bootup_value;
0122     u32 mclk_bootup_value;
0123     u16 pcie_gen_bootup_value;
0124     u16 pcie_lane_bootup_value;
0125 };
0126
0127 struct ci_clock_registers {
0128     u32 cg_spll_func_cntl;
0129     u32 cg_spll_func_cntl_2;
0130     u32 cg_spll_func_cntl_3;
0131     u32 cg_spll_func_cntl_4;
0132     u32 cg_spll_spread_spectrum;
0133     u32 cg_spll_spread_spectrum_2;
0134     u32 dll_cntl;
0135     u32 mclk_pwrmgt_cntl;
0136     u32 mpll_ad_func_cntl;
0137     u32 mpll_dq_func_cntl;
0138     u32 mpll_func_cntl;
0139     u32 mpll_func_cntl_1;
0140     u32 mpll_func_cntl_2;
0141     u32 mpll_ss1;
0142     u32 mpll_ss2;
0143 };
0144
0145 struct ci_thermal_temperature_setting {
0146     s32 temperature_low;
0147     s32 temperature_high;
0148     s32 temperature_shutdown;
0149 };
0150
0151 struct ci_pcie_perf_range {
0152     u16 max;
0153     u16 min;
0154 };
0155
0156 enum ci_pt_config_reg_type {
0157     CISLANDS_CONFIGREG_MMR = 0,
0158     CISLANDS_CONFIGREG_SMC_IND,
0159     CISLANDS_CONFIGREG_DIDT_IND,
0160     CISLANDS_CONFIGREG_CACHE,
0161     CISLANDS_CONFIGREG_MAX
0162 };
0163
0164 #define POWERCONTAINMENT_FEATURE_BAPM            0x00000001
0165 #define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002
0166 #define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004
0167
0168 struct ci_pt_config_reg {
0169     u32 offset;
0170     u32 mask;
0171     u32 shift;
0172     u32 value;
0173     enum ci_pt_config_reg_type type;
0174 };
0175
0176 struct ci_pt_defaults {
0177     u8 svi_load_line_en;
0178     u8 svi_load_line_vddc;
0179     u8 tdc_vddc_throttle_release_limit_perc;
0180     u8 tdc_mawt;
0181     u8 tdc_waterfall_ctl;
0182     u8 dte_ambient_temp_base;
0183     u32 display_cac;
0184     u32 bapm_temp_gradient;
0185     u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
0186     u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
0187 };
0188
0189 #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
0190 #define DPMTABLE_OD_UPDATE_MCLK     0x00000002
0191 #define DPMTABLE_UPDATE_SCLK        0x00000004
0192 #define DPMTABLE_UPDATE_MCLK        0x00000008
0193
0194 struct ci_power_info {
0195     struct ci_dpm_table dpm_table;
0196     u32 voltage_control;
0197     u32 mvdd_control;
0198     u32 vddci_control;
0199     u32 active_auto_throttle_sources;
0200     struct ci_clock_registers clock_registers;
0201     u16 acpi_vddc;
0202     u16 acpi_vddci;
0203     enum radeon_pcie_gen force_pcie_gen;
0204     enum radeon_pcie_gen acpi_pcie_gen;
0205     struct ci_leakage_voltage vddc_leakage;
0206     struct ci_leakage_voltage vddci_leakage;
0207     u16 max_vddc_in_pp_table;
0208     u16 min_vddc_in_pp_table;
0209     u16 max_vddci_in_pp_table;
0210     u16 min_vddci_in_pp_table;
0211     u32 mclk_strobe_mode_threshold;
0212     u32 mclk_stutter_mode_threshold;
0213     u32 mclk_edc_enable_threshold;
0214     u32 mclk_edc_wr_enable_threshold;
0215     struct ci_vbios_boot_state vbios_boot_state;
0216     /* smc offsets */
0217     u32 sram_end;
0218     u32 dpm_table_start;
0219     u32 soft_regs_start;
0220     u32 mc_reg_table_start;
0221     u32 fan_table_start;
0222     u32 arb_table_start;
0223     /* smc tables */
0224     SMU7_Discrete_DpmTable smc_state_table;
0225     SMU7_Discrete_MCRegisters smc_mc_reg_table;
0226     SMU7_Discrete_PmFuses smc_powertune_table;
0227     /* other stuff */
0228     struct ci_mc_reg_table mc_reg_table;
0229     struct atom_voltage_table vddc_voltage_table;
0230     struct atom_voltage_table vddci_voltage_table;
0231     struct atom_voltage_table mvdd_voltage_table;
0232     struct ci_ulv_parm ulv;
0233     u32 power_containment_features;
0234     const struct ci_pt_defaults *powertune_defaults;
0235     u32 dte_tj_offset;
0236     bool vddc_phase_shed_control;
0237     struct ci_thermal_temperature_setting thermal_temp_setting;
0238     struct ci_dpm_level_enable_mask dpm_level_enable_mask;
0239     u32 need_update_smu7_dpm_table;
0240     u32 sclk_dpm_key_disabled;
0241     u32 mclk_dpm_key_disabled;
0242     u32 pcie_dpm_key_disabled;
0243     u32 thermal_sclk_dpm_enabled;
0244     struct ci_pcie_perf_range pcie_gen_performance;
0245     struct ci_pcie_perf_range pcie_lane_performance;
0246     struct ci_pcie_perf_range pcie_gen_powersaving;
0247     struct ci_pcie_perf_range pcie_lane_powersaving;
0248     u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS];
0249     u32 mclk_activity_target;
0250     u32 low_sclk_interrupt_t;
0251     u32 last_mclk_dpm_enable_mask;
0252     u32 sys_pcie_mask;
0253     /* caps */
0254     bool caps_power_containment;
0255     bool caps_cac;
0256     bool caps_sq_ramping;
0257     bool caps_db_ramping;
0258     bool caps_td_ramping;
0259     bool caps_tcp_ramping;
0260     bool caps_fps;
0261     bool caps_sclk_ds;
0262     bool caps_sclk_ss_support;
0263     bool caps_mclk_ss_support;
0264     bool caps_uvd_dpm;
0265     bool caps_vce_dpm;
0266     bool caps_samu_dpm;
0267     bool caps_acp_dpm;
0268     bool caps_automatic_dc_transition;
0269     bool caps_sclk_throttle_low_notification;
0270     bool caps_dynamic_ac_timing;
0271     bool caps_od_fuzzy_fan_control_support;
0272     /* flags */
0273     bool thermal_protection;
0274     bool pcie_performance_request;
0275     bool dynamic_ss;
0276     bool dll_default_on;
0277     bool cac_enabled;
0278     bool uvd_enabled;
0279     bool battery_state;
0280     bool pspp_notify_required;
0281     bool mem_gddr5;
0282     bool enable_bapm_feature;
0283     bool enable_tdc_limit_feature;
0284     bool enable_pkg_pwr_tracking_feature;
0285     bool use_pcie_performance_levels;
0286     bool use_pcie_powersaving_levels;
0287     bool uvd_power_gated;
0288     /* driver states */
0289     struct radeon_ps current_rps;
0290     struct ci_ps current_ps;
0291     struct radeon_ps requested_rps;
0292     struct ci_ps requested_ps;
0293     /* fan control */
0294     bool fan_ctrl_is_in_default_mode;
0295     bool fan_is_controlled_by_smc;
0296     u32 t_min;
0297     u32 fan_ctrl_default_mode;
0298 };
0299
0300 #define CISLANDS_VOLTAGE_CONTROL_NONE                   0x0
0301 #define CISLANDS_VOLTAGE_CONTROL_BY_GPIO                0x1
0302 #define CISLANDS_VOLTAGE_CONTROL_BY_SVID2               0x2
0303
0304 #define CISLANDS_Q88_FORMAT_CONVERSION_UNIT             256
0305
0306 #define CISLANDS_VRC_DFLT0                              0x3FFFC000
0307 #define CISLANDS_VRC_DFLT1                              0x000400
0308 #define CISLANDS_VRC_DFLT2                              0xC00080
0309 #define CISLANDS_VRC_DFLT3                              0xC00200
0310 #define CISLANDS_VRC_DFLT4                              0xC01680
0311 #define CISLANDS_VRC_DFLT5                              0xC00033
0312 #define CISLANDS_VRC_DFLT6                              0xC00033
0313 #define CISLANDS_VRC_DFLT7                              0x3FFFC000
0314
0315 #define CISLANDS_CGULVPARAMETER_DFLT                    0x00040035
0316 #define CISLAND_TARGETACTIVITY_DFLT                     30
0317 #define CISLAND_MCLK_TARGETACTIVITY_DFLT                10
0318
0319 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
0320 #define PCIE_PERF_REQ_FORCE_LOWPOWER    1
0321 #define PCIE_PERF_REQ_PECI_GEN1         2
0322 #define PCIE_PERF_REQ_PECI_GEN2         3
0323 #define PCIE_PERF_REQ_PECI_GEN3         4
0324
0325 int ci_copy_bytes_to_smc(struct radeon_device *rdev,
0326              u32 smc_start_address,
0327              const u8 *src, u32 byte_count, u32 limit);
0328 void ci_start_smc(struct radeon_device *rdev);
0329 void ci_reset_smc(struct radeon_device *rdev);
0330 int ci_program_jump_on_start(struct radeon_device *rdev);
0331 void ci_stop_smc_clock(struct radeon_device *rdev);
0332 void ci_start_smc_clock(struct radeon_device *rdev);
0333 bool ci_is_smc_running(struct radeon_device *rdev);
0334 PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev);
0335 int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit);
0336 int ci_read_smc_sram_dword(struct radeon_device *rdev,
0337                u32 smc_address, u32 *value, u32 limit);
0338 int ci_write_smc_sram_dword(struct radeon_device *rdev,
0339                 u32 smc_address, u32 value, u32 limit);
0340
0341 #endif