drm/radeon/cayman_blit_shaders.h

0001 /*
0002  * Copyright 2010 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0021  * DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors:
0024  *     Alex Deucher <alexander.deucher@amd.com>
0025  */
0026
0027 #ifndef CAYMAN_BLIT_SHADERS_H
0028 #define CAYMAN_BLIT_SHADERS_H
0029
0030 /*
0031  * evergreen cards need to use the 3D engine to blit data which requires
0032  * quite a bit of hw state setup.  Rather than pull the whole 3D driver
0033  * (which normally generates the 3D state) into the DRM, we opt to use
0034  * statically generated state tables.  The register state and shaders
0035  * were hand generated to support blitting functionality.  See the 3D
0036  * driver or documentation for descriptions of the registers and
0037  * shader instructions.
0038  */
0039 static const u32 cayman_default_state[] = {
0040     0xc0066900,
0041     0x00000000,
0042     0x00000060, /* DB_RENDER_CONTROL */
0043     0x00000000, /* DB_COUNT_CONTROL */
0044     0x00000000, /* DB_DEPTH_VIEW */
0045     0x0000002a, /* DB_RENDER_OVERRIDE */
0046     0x00000000, /* DB_RENDER_OVERRIDE2 */
0047     0x00000000, /* DB_HTILE_DATA_BASE */
0048
0049     0xc0026900,
0050     0x0000000a,
0051     0x00000000, /* DB_STENCIL_CLEAR */
0052     0x00000000, /* DB_DEPTH_CLEAR */
0053
0054     0xc0036900,
0055     0x0000000f,
0056     0x00000000, /* DB_DEPTH_INFO */
0057     0x00000000, /* DB_Z_INFO */
0058     0x00000000, /* DB_STENCIL_INFO */
0059
0060     0xc0016900,
0061     0x00000080,
0062     0x00000000, /* PA_SC_WINDOW_OFFSET */
0063
0064     0xc00d6900,
0065     0x00000083,
0066     0x0000ffff, /* PA_SC_CLIPRECT_RULE */
0067     0x00000000, /* PA_SC_CLIPRECT_0_TL */
0068     0x20002000, /* PA_SC_CLIPRECT_0_BR */
0069     0x00000000,
0070     0x20002000,
0071     0x00000000,
0072     0x20002000,
0073     0x00000000,
0074     0x20002000,
0075     0xaaaaaaaa, /* PA_SC_EDGERULE */
0076     0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
0077     0x0000000f, /* CB_TARGET_MASK */
0078     0x0000000f, /* CB_SHADER_MASK */
0079
0080     0xc0226900,
0081     0x00000094,
0082     0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
0083     0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
0084     0x80000000,
0085     0x20002000,
0086     0x80000000,
0087     0x20002000,
0088     0x80000000,
0089     0x20002000,
0090     0x80000000,
0091     0x20002000,
0092     0x80000000,
0093     0x20002000,
0094     0x80000000,
0095     0x20002000,
0096     0x80000000,
0097     0x20002000,
0098     0x80000000,
0099     0x20002000,
0100     0x80000000,
0101     0x20002000,
0102     0x80000000,
0103     0x20002000,
0104     0x80000000,
0105     0x20002000,
0106     0x80000000,
0107     0x20002000,
0108     0x80000000,
0109     0x20002000,
0110     0x80000000,
0111     0x20002000,
0112     0x80000000,
0113     0x20002000,
0114     0x00000000, /* PA_SC_VPORT_ZMIN_0 */
0115     0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
0116
0117     0xc0016900,
0118     0x000000d4,
0119     0x00000000, /* SX_MISC */
0120
0121     0xc0026900,
0122     0x000000d9,
0123     0x00000000, /* CP_RINGID */
0124     0x00000000, /* CP_VMID */
0125
0126     0xc0096900,
0127     0x00000100,
0128     0x00ffffff, /* VGT_MAX_VTX_INDX */
0129     0x00000000, /* VGT_MIN_VTX_INDX */
0130     0x00000000, /* VGT_INDX_OFFSET */
0131     0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
0132     0x00000000, /* SX_ALPHA_TEST_CONTROL */
0133     0x00000000, /* CB_BLEND_RED */
0134     0x00000000, /* CB_BLEND_GREEN */
0135     0x00000000, /* CB_BLEND_BLUE */
0136     0x00000000, /* CB_BLEND_ALPHA */
0137
0138     0xc0016900,
0139     0x00000187,
0140     0x00000100, /* SPI_VS_OUT_ID_0 */
0141
0142     0xc0026900,
0143     0x00000191,
0144     0x00000100, /* SPI_PS_INPUT_CNTL_0 */
0145     0x00000101, /* SPI_PS_INPUT_CNTL_1 */
0146
0147     0xc0016900,
0148     0x000001b1,
0149     0x00000000, /* SPI_VS_OUT_CONFIG */
0150
0151     0xc0106900,
0152     0x000001b3,
0153     0x20000001, /* SPI_PS_IN_CONTROL_0 */
0154     0x00000000, /* SPI_PS_IN_CONTROL_1 */
0155     0x00000000, /* SPI_INTERP_CONTROL_0 */
0156     0x00000000, /* SPI_INPUT_Z */
0157     0x00000000, /* SPI_FOG_CNTL */
0158     0x00100000, /* SPI_BARYC_CNTL */
0159     0x00000000, /* SPI_PS_IN_CONTROL_2 */
0160     0x00000000, /* SPI_COMPUTE_INPUT_CNTL */
0161     0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */
0162     0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */
0163     0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */
0164     0x00000000, /* SPI_GPR_MGMT */
0165     0x00000000, /* SPI_LDS_MGMT */
0166     0x00000000, /* SPI_STACK_MGMT */
0167     0x00000000, /* SPI_WAVE_MGMT_1 */
0168     0x00000000, /* SPI_WAVE_MGMT_2 */
0169
0170     0xc0016900,
0171     0x000001e0,
0172     0x00000000, /* CB_BLEND0_CONTROL */
0173
0174     0xc00e6900,
0175     0x00000200,
0176     0x00000000, /* DB_DEPTH_CONTROL */
0177     0x00000000, /* DB_EQAA */
0178     0x00cc0010, /* CB_COLOR_CONTROL */
0179     0x00000210, /* DB_SHADER_CONTROL */
0180     0x00010000, /* PA_CL_CLIP_CNTL */
0181     0x00000004, /* PA_SU_SC_MODE_CNTL */
0182     0x00000100, /* PA_CL_VTE_CNTL */
0183     0x00000000, /* PA_CL_VS_OUT_CNTL */
0184     0x00000000, /* PA_CL_NANINF_CNTL */
0185     0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
0186     0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
0187     0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
0188     0x00000000, /*  */
0189     0x00000000, /*  */
0190
0191     0xc0026900,
0192     0x00000229,
0193     0x00000000, /* SQ_PGM_START_FS */
0194     0x00000000,
0195
0196     0xc0016900,
0197     0x0000023b,
0198     0x00000000, /* SQ_LDS_ALLOC_PS */
0199
0200     0xc0066900,
0201     0x00000240,
0202     0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
0203     0x00000000,
0204     0x00000000,
0205     0x00000000,
0206     0x00000000,
0207     0x00000000,
0208
0209     0xc0046900,
0210     0x00000247,
0211     0x00000000, /* SQ_GS_VERT_ITEMSIZE */
0212     0x00000000,
0213     0x00000000,
0214     0x00000000,
0215
0216     0xc0116900,
0217     0x00000280,
0218     0x00000000, /* PA_SU_POINT_SIZE */
0219     0x00000000, /* PA_SU_POINT_MINMAX */
0220     0x00000008, /* PA_SU_LINE_CNTL */
0221     0x00000000, /* PA_SC_LINE_STIPPLE */
0222     0x00000000, /* VGT_OUTPUT_PATH_CNTL */
0223     0x00000000, /* VGT_HOS_CNTL */
0224     0x00000000,
0225     0x00000000,
0226     0x00000000,
0227     0x00000000,
0228     0x00000000,
0229     0x00000000,
0230     0x00000000,
0231     0x00000000,
0232     0x00000000,
0233     0x00000000,
0234     0x00000000, /* VGT_GS_MODE */
0235
0236     0xc0026900,
0237     0x00000292,
0238     0x00000000, /* PA_SC_MODE_CNTL_0 */
0239     0x00000000, /* PA_SC_MODE_CNTL_1 */
0240
0241     0xc0016900,
0242     0x000002a1,
0243     0x00000000, /* VGT_PRIMITIVEID_EN */
0244
0245     0xc0016900,
0246     0x000002a5,
0247     0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
0248
0249     0xc0026900,
0250     0x000002a8,
0251     0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
0252     0x00000000,
0253
0254     0xc0026900,
0255     0x000002ad,
0256     0x00000000, /* VGT_REUSE_OFF */
0257     0x00000000,
0258
0259     0xc0016900,
0260     0x000002d5,
0261     0x00000000, /* VGT_SHADER_STAGES_EN */
0262
0263     0xc0016900,
0264     0x000002dc,
0265     0x0000aa00, /* DB_ALPHA_TO_MASK */
0266
0267     0xc0066900,
0268     0x000002de,
0269     0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
0270     0x00000000,
0271     0x00000000,
0272     0x00000000,
0273     0x00000000,
0274     0x00000000,
0275
0276     0xc0026900,
0277     0x000002e5,
0278     0x00000000, /* VGT_STRMOUT_CONFIG */
0279     0x00000000,
0280
0281     0xc01b6900,
0282     0x000002f5,
0283     0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
0284     0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
0285     0x00000000, /* PA_SC_LINE_CNTL */
0286     0x00000000, /* PA_SC_AA_CONFIG */
0287     0x00000005, /* PA_SU_VTX_CNTL */
0288     0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
0289     0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
0290     0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
0291     0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
0292     0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
0293     0x00000000,
0294     0x00000000,
0295     0x00000000,
0296     0x00000000,
0297     0x00000000,
0298     0x00000000,
0299     0x00000000,
0300     0x00000000,
0301     0x00000000,
0302     0x00000000,
0303     0x00000000,
0304     0x00000000,
0305     0x00000000,
0306     0x00000000,
0307     0x00000000,
0308     0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
0309     0xffffffff,
0310
0311     0xc0026900,
0312     0x00000316,
0313     0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
0314     0x00000010, /*  */
0315 };
0316
0317 static const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);
0318
0319 #endif