drm/radeon/atom-names.h

0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Author: Stanislaw Skowronek
0023  */
0024
0025 #ifndef ATOM_NAMES_H
0026 #define ATOM_NAMES_H
0027
0028 #include "atom.h"
0029
0030 #ifdef ATOM_DEBUG
0031
0032 #define ATOM_OP_NAMES_CNT 123
0033 static char *atom_op_names[ATOM_OP_NAMES_CNT] = {
0034 "RESERVED", "MOVE_REG", "MOVE_PS", "MOVE_WS", "MOVE_FB", "MOVE_PLL",
0035 "MOVE_MC", "AND_REG", "AND_PS", "AND_WS", "AND_FB", "AND_PLL", "AND_MC",
0036 "OR_REG", "OR_PS", "OR_WS", "OR_FB", "OR_PLL", "OR_MC", "SHIFT_LEFT_REG",
0037 "SHIFT_LEFT_PS", "SHIFT_LEFT_WS", "SHIFT_LEFT_FB", "SHIFT_LEFT_PLL",
0038 "SHIFT_LEFT_MC", "SHIFT_RIGHT_REG", "SHIFT_RIGHT_PS", "SHIFT_RIGHT_WS",
0039 "SHIFT_RIGHT_FB", "SHIFT_RIGHT_PLL", "SHIFT_RIGHT_MC", "MUL_REG",
0040 "MUL_PS", "MUL_WS", "MUL_FB", "MUL_PLL", "MUL_MC", "DIV_REG", "DIV_PS",
0041 "DIV_WS", "DIV_FB", "DIV_PLL", "DIV_MC", "ADD_REG", "ADD_PS", "ADD_WS",
0042 "ADD_FB", "ADD_PLL", "ADD_MC", "SUB_REG", "SUB_PS", "SUB_WS", "SUB_FB",
0043 "SUB_PLL", "SUB_MC", "SET_ATI_PORT", "SET_PCI_PORT", "SET_SYS_IO_PORT",
0044 "SET_REG_BLOCK", "SET_FB_BASE", "COMPARE_REG", "COMPARE_PS",
0045 "COMPARE_WS", "COMPARE_FB", "COMPARE_PLL", "COMPARE_MC", "SWITCH",
0046 "JUMP", "JUMP_EQUAL", "JUMP_BELOW", "JUMP_ABOVE", "JUMP_BELOW_OR_EQUAL",
0047 "JUMP_ABOVE_OR_EQUAL", "JUMP_NOT_EQUAL", "TEST_REG", "TEST_PS", "TEST_WS",
0048 "TEST_FB", "TEST_PLL", "TEST_MC", "DELAY_MILLISEC", "DELAY_MICROSEC",
0049 "CALL_TABLE", "REPEAT", "CLEAR_REG", "CLEAR_PS", "CLEAR_WS", "CLEAR_FB",
0050 "CLEAR_PLL", "CLEAR_MC", "NOP", "EOT", "MASK_REG", "MASK_PS", "MASK_WS",
0051 "MASK_FB", "MASK_PLL", "MASK_MC", "POST_CARD", "BEEP", "SAVE_REG",
0052 "RESTORE_REG", "SET_DATA_BLOCK", "XOR_REG", "XOR_PS", "XOR_WS", "XOR_FB",
0053 "XOR_PLL", "XOR_MC", "SHL_REG", "SHL_PS", "SHL_WS", "SHL_FB", "SHL_PLL",
0054 "SHL_MC", "SHR_REG", "SHR_PS", "SHR_WS", "SHR_FB", "SHR_PLL", "SHR_MC",
0055 "DEBUG", "CTB_DS",
0056 };
0057
0058 #define ATOM_TABLE_NAMES_CNT 74
0059 static char *atom_table_names[ATOM_TABLE_NAMES_CNT] = {
0060 "ASIC_Init", "GetDisplaySurfaceSize", "ASIC_RegistersInit",
0061 "VRAM_BlockVenderDetection", "SetClocksRatio", "MemoryControllerInit",
0062 "GPIO_PinInit", "MemoryParamAdjust", "DVOEncoderControl",
0063 "GPIOPinControl", "SetEngineClock", "SetMemoryClock", "SetPixelClock",
0064 "DynamicClockGating", "ResetMemoryDLL", "ResetMemoryDevice",
0065 "MemoryPLLInit", "EnableMemorySelfRefresh", "AdjustMemoryController",
0066 "EnableASIC_StaticPwrMgt", "ASIC_StaticPwrMgtStatusChange",
0067 "DAC_LoadDetection", "TMDS2EncoderControl", "LCD1OutputControl",
0068 "DAC1EncoderControl", "DAC2EncoderControl", "DVOOutputControl",
0069 "CV1OutputControl", "SetCRTC_DPM_State", "TVEncoderControl",
0070 "TMDS1EncoderControl", "LVDSEncoderControl", "TV1OutputControl",
0071 "EnableScaler", "BlankCRTC", "EnableCRTC", "GetPixelClock",
0072 "EnableVGA_Render", "EnableVGA_Access", "SetCRTC_Timing",
0073 "SetCRTC_OverScan", "SetCRTC_Replication", "SelectCRTC_Source",
0074 "EnableGraphSurfaces", "UpdateCRTC_DoubleBufferRegisters",
0075 "LUT_AutoFill", "EnableHW_IconCursor", "GetMemoryClock",
0076 "GetEngineClock", "SetCRTC_UsingDTDTiming", "TVBootUpStdPinDetection",
0077 "DFP2OutputControl", "VRAM_BlockDetectionByStrap", "MemoryCleanUp",
0078 "ReadEDIDFromHWAssistedI2C", "WriteOneByteToHWAssistedI2C",
0079 "ReadHWAssistedI2CStatus", "SpeedFanControl", "PowerConnectorDetection",
0080 "MC_Synchronization", "ComputeMemoryEnginePLL", "MemoryRefreshConversion",
0081 "VRAM_GetCurrentInfoBlock", "DynamicMemorySettings", "MemoryTraining",
0082 "EnableLVDS_SS", "DFP1OutputControl", "SetVoltage", "CRT1OutputControl",
0083 "CRT2OutputControl", "SetupHWAssistedI2CStatus", "ClockSource",
0084 "MemoryDeviceInit", "EnableYUV",
0085 };
0086
0087 #define ATOM_IO_NAMES_CNT 5
0088 static char *atom_io_names[ATOM_IO_NAMES_CNT] = {
0089 "MM", "PLL", "MC", "PCIE", "PCIE PORT",
0090 };
0091
0092 #else
0093
0094 #define ATOM_OP_NAMES_CNT 0
0095 #define ATOM_TABLE_NAMES_CNT 0
0096 #define ATOM_IO_NAMES_CNT 0
0097
0098 #endif
0099
0100 #endif