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0001 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
0002  * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
0003  */
0004 /*
0005  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
0006  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
0007  * All Rights Reserved.
0008  *
0009  * Permission is hereby granted, free of charge, to any person obtaining a
0010  * copy of this software and associated documentation files (the "Software"),
0011  * to deal in the Software without restriction, including without limitation
0012  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0013  * and/or sell copies of the Software, and to permit persons to whom the
0014  * Software is furnished to do so, subject to the following conditions:
0015  *
0016  * The above copyright notice and this permission notice (including the next
0017  * paragraph) shall be included in all copies or substantial portions of the
0018  * Software.
0019  *
0020  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0021  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0022  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0023  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
0024  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0025  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0026  * DEALINGS IN THE SOFTWARE.
0027  *
0028  * Authors:
0029  *    Gareth Hughes <gareth@valinux.com>
0030  */
0031 
0032 #include <linux/delay.h>
0033 #include <linux/dma-mapping.h>
0034 #include <linux/firmware.h>
0035 #include <linux/module.h>
0036 #include <linux/platform_device.h>
0037 #include <linux/slab.h>
0038 #include <linux/uaccess.h>
0039 
0040 #include <drm/drm_device.h>
0041 #include <drm/drm_file.h>
0042 #include <drm/drm_legacy.h>
0043 #include <drm/drm_print.h>
0044 #include <drm/r128_drm.h>
0045 
0046 #include "r128_drv.h"
0047 
0048 #define R128_FIFO_DEBUG     0
0049 
0050 #define FIRMWARE_NAME       "r128/r128_cce.bin"
0051 
0052 MODULE_FIRMWARE(FIRMWARE_NAME);
0053 
0054 static int R128_READ_PLL(struct drm_device *dev, int addr)
0055 {
0056     drm_r128_private_t *dev_priv = dev->dev_private;
0057 
0058     R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
0059     return R128_READ(R128_CLOCK_CNTL_DATA);
0060 }
0061 
0062 #if R128_FIFO_DEBUG
0063 static void r128_status(drm_r128_private_t *dev_priv)
0064 {
0065     printk("GUI_STAT           = 0x%08x\n",
0066            (unsigned int)R128_READ(R128_GUI_STAT));
0067     printk("PM4_STAT           = 0x%08x\n",
0068            (unsigned int)R128_READ(R128_PM4_STAT));
0069     printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
0070            (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
0071     printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
0072            (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
0073     printk("PM4_MICRO_CNTL     = 0x%08x\n",
0074            (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
0075     printk("PM4_BUFFER_CNTL    = 0x%08x\n",
0076            (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
0077 }
0078 #endif
0079 
0080 /* ================================================================
0081  * Engine, FIFO control
0082  */
0083 
0084 static int r128_do_pixcache_flush(drm_r128_private_t *dev_priv)
0085 {
0086     u32 tmp;
0087     int i;
0088 
0089     tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
0090     R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
0091 
0092     for (i = 0; i < dev_priv->usec_timeout; i++) {
0093         if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY))
0094             return 0;
0095         udelay(1);
0096     }
0097 
0098 #if R128_FIFO_DEBUG
0099     DRM_ERROR("failed!\n");
0100 #endif
0101     return -EBUSY;
0102 }
0103 
0104 static int r128_do_wait_for_fifo(drm_r128_private_t *dev_priv, int entries)
0105 {
0106     int i;
0107 
0108     for (i = 0; i < dev_priv->usec_timeout; i++) {
0109         int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
0110         if (slots >= entries)
0111             return 0;
0112         udelay(1);
0113     }
0114 
0115 #if R128_FIFO_DEBUG
0116     DRM_ERROR("failed!\n");
0117 #endif
0118     return -EBUSY;
0119 }
0120 
0121 static int r128_do_wait_for_idle(drm_r128_private_t *dev_priv)
0122 {
0123     int i, ret;
0124 
0125     ret = r128_do_wait_for_fifo(dev_priv, 64);
0126     if (ret)
0127         return ret;
0128 
0129     for (i = 0; i < dev_priv->usec_timeout; i++) {
0130         if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
0131             r128_do_pixcache_flush(dev_priv);
0132             return 0;
0133         }
0134         udelay(1);
0135     }
0136 
0137 #if R128_FIFO_DEBUG
0138     DRM_ERROR("failed!\n");
0139 #endif
0140     return -EBUSY;
0141 }
0142 
0143 /* ================================================================
0144  * CCE control, initialization
0145  */
0146 
0147 /* Load the microcode for the CCE */
0148 static int r128_cce_load_microcode(drm_r128_private_t *dev_priv)
0149 {
0150     struct platform_device *pdev;
0151     const struct firmware *fw;
0152     const __be32 *fw_data;
0153     int rc, i;
0154 
0155     DRM_DEBUG("\n");
0156 
0157     pdev = platform_device_register_simple("r128_cce", 0, NULL, 0);
0158     if (IS_ERR(pdev)) {
0159         pr_err("r128_cce: Failed to register firmware\n");
0160         return PTR_ERR(pdev);
0161     }
0162     rc = request_firmware(&fw, FIRMWARE_NAME, &pdev->dev);
0163     platform_device_unregister(pdev);
0164     if (rc) {
0165         pr_err("r128_cce: Failed to load firmware \"%s\"\n",
0166                FIRMWARE_NAME);
0167         return rc;
0168     }
0169 
0170     if (fw->size != 256 * 8) {
0171         pr_err("r128_cce: Bogus length %zu in firmware \"%s\"\n",
0172                fw->size, FIRMWARE_NAME);
0173         rc = -EINVAL;
0174         goto out_release;
0175     }
0176 
0177     r128_do_wait_for_idle(dev_priv);
0178 
0179     fw_data = (const __be32 *)fw->data;
0180     R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
0181     for (i = 0; i < 256; i++) {
0182         R128_WRITE(R128_PM4_MICROCODE_DATAH,
0183                be32_to_cpup(&fw_data[i * 2]));
0184         R128_WRITE(R128_PM4_MICROCODE_DATAL,
0185                be32_to_cpup(&fw_data[i * 2 + 1]));
0186     }
0187 
0188 out_release:
0189     release_firmware(fw);
0190     return rc;
0191 }
0192 
0193 /* Flush any pending commands to the CCE.  This should only be used just
0194  * prior to a wait for idle, as it informs the engine that the command
0195  * stream is ending.
0196  */
0197 static void r128_do_cce_flush(drm_r128_private_t *dev_priv)
0198 {
0199     u32 tmp;
0200 
0201     tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
0202     R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
0203 }
0204 
0205 /* Wait for the CCE to go idle.
0206  */
0207 int r128_do_cce_idle(drm_r128_private_t *dev_priv)
0208 {
0209     int i;
0210 
0211     for (i = 0; i < dev_priv->usec_timeout; i++) {
0212         if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
0213             int pm4stat = R128_READ(R128_PM4_STAT);
0214             if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
0215                  dev_priv->cce_fifo_size) &&
0216                 !(pm4stat & (R128_PM4_BUSY |
0217                      R128_PM4_GUI_ACTIVE))) {
0218                 return r128_do_pixcache_flush(dev_priv);
0219             }
0220         }
0221         udelay(1);
0222     }
0223 
0224 #if R128_FIFO_DEBUG
0225     DRM_ERROR("failed!\n");
0226     r128_status(dev_priv);
0227 #endif
0228     return -EBUSY;
0229 }
0230 
0231 /* Start the Concurrent Command Engine.
0232  */
0233 static void r128_do_cce_start(drm_r128_private_t *dev_priv)
0234 {
0235     r128_do_wait_for_idle(dev_priv);
0236 
0237     R128_WRITE(R128_PM4_BUFFER_CNTL,
0238            dev_priv->cce_mode | dev_priv->ring.size_l2qw
0239            | R128_PM4_BUFFER_CNTL_NOUPDATE);
0240     R128_READ(R128_PM4_BUFFER_ADDR);    /* as per the sample code */
0241     R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
0242 
0243     dev_priv->cce_running = 1;
0244 }
0245 
0246 /* Reset the Concurrent Command Engine.  This will not flush any pending
0247  * commands, so you must wait for the CCE command stream to complete
0248  * before calling this routine.
0249  */
0250 static void r128_do_cce_reset(drm_r128_private_t *dev_priv)
0251 {
0252     R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
0253     R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
0254     dev_priv->ring.tail = 0;
0255 }
0256 
0257 /* Stop the Concurrent Command Engine.  This will not flush any pending
0258  * commands, so you must flush the command stream and wait for the CCE
0259  * to go idle before calling this routine.
0260  */
0261 static void r128_do_cce_stop(drm_r128_private_t *dev_priv)
0262 {
0263     R128_WRITE(R128_PM4_MICRO_CNTL, 0);
0264     R128_WRITE(R128_PM4_BUFFER_CNTL,
0265            R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
0266 
0267     dev_priv->cce_running = 0;
0268 }
0269 
0270 /* Reset the engine.  This will stop the CCE if it is running.
0271  */
0272 static int r128_do_engine_reset(struct drm_device *dev)
0273 {
0274     drm_r128_private_t *dev_priv = dev->dev_private;
0275     u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
0276 
0277     r128_do_pixcache_flush(dev_priv);
0278 
0279     clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
0280     mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
0281 
0282     R128_WRITE_PLL(R128_MCLK_CNTL,
0283                mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
0284 
0285     gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
0286 
0287     /* Taken from the sample code - do not change */
0288     R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
0289     R128_READ(R128_GEN_RESET_CNTL);
0290     R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
0291     R128_READ(R128_GEN_RESET_CNTL);
0292 
0293     R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
0294     R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
0295     R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
0296 
0297     /* Reset the CCE ring */
0298     r128_do_cce_reset(dev_priv);
0299 
0300     /* The CCE is no longer running after an engine reset */
0301     dev_priv->cce_running = 0;
0302 
0303     /* Reset any pending vertex, indirect buffers */
0304     r128_freelist_reset(dev);
0305 
0306     return 0;
0307 }
0308 
0309 static void r128_cce_init_ring_buffer(struct drm_device *dev,
0310                       drm_r128_private_t *dev_priv)
0311 {
0312     u32 ring_start;
0313     u32 tmp;
0314 
0315     DRM_DEBUG("\n");
0316 
0317     /* The manual (p. 2) says this address is in "VM space".  This
0318      * means it's an offset from the start of AGP space.
0319      */
0320 #if IS_ENABLED(CONFIG_AGP)
0321     if (!dev_priv->is_pci)
0322         ring_start = dev_priv->cce_ring->offset - dev->agp->base;
0323     else
0324 #endif
0325         ring_start = dev_priv->cce_ring->offset -
0326             (unsigned long)dev->sg->virtual;
0327 
0328     R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
0329 
0330     R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
0331     R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
0332 
0333     /* Set watermark control */
0334     R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
0335            ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
0336            | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
0337            | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
0338            | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
0339 
0340     /* Force read.  Why?  Because it's in the examples... */
0341     R128_READ(R128_PM4_BUFFER_ADDR);
0342 
0343     /* Turn on bus mastering */
0344     tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
0345     R128_WRITE(R128_BUS_CNTL, tmp);
0346 }
0347 
0348 static int r128_do_init_cce(struct drm_device *dev, drm_r128_init_t *init)
0349 {
0350     drm_r128_private_t *dev_priv;
0351     int rc;
0352 
0353     DRM_DEBUG("\n");
0354 
0355     if (dev->dev_private) {
0356         DRM_DEBUG("called when already initialized\n");
0357         return -EINVAL;
0358     }
0359 
0360     dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL);
0361     if (dev_priv == NULL)
0362         return -ENOMEM;
0363 
0364     dev_priv->is_pci = init->is_pci;
0365 
0366     if (dev_priv->is_pci && !dev->sg) {
0367         DRM_ERROR("PCI GART memory not allocated!\n");
0368         dev->dev_private = (void *)dev_priv;
0369         r128_do_cleanup_cce(dev);
0370         return -EINVAL;
0371     }
0372 
0373     dev_priv->usec_timeout = init->usec_timeout;
0374     if (dev_priv->usec_timeout < 1 ||
0375         dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
0376         DRM_DEBUG("TIMEOUT problem!\n");
0377         dev->dev_private = (void *)dev_priv;
0378         r128_do_cleanup_cce(dev);
0379         return -EINVAL;
0380     }
0381 
0382     dev_priv->cce_mode = init->cce_mode;
0383 
0384     /* GH: Simple idle check.
0385      */
0386     atomic_set(&dev_priv->idle_count, 0);
0387 
0388     /* We don't support anything other than bus-mastering ring mode,
0389      * but the ring can be in either AGP or PCI space for the ring
0390      * read pointer.
0391      */
0392     if ((init->cce_mode != R128_PM4_192BM) &&
0393         (init->cce_mode != R128_PM4_128BM_64INDBM) &&
0394         (init->cce_mode != R128_PM4_64BM_128INDBM) &&
0395         (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
0396         DRM_DEBUG("Bad cce_mode!\n");
0397         dev->dev_private = (void *)dev_priv;
0398         r128_do_cleanup_cce(dev);
0399         return -EINVAL;
0400     }
0401 
0402     switch (init->cce_mode) {
0403     case R128_PM4_NONPM4:
0404         dev_priv->cce_fifo_size = 0;
0405         break;
0406     case R128_PM4_192PIO:
0407     case R128_PM4_192BM:
0408         dev_priv->cce_fifo_size = 192;
0409         break;
0410     case R128_PM4_128PIO_64INDBM:
0411     case R128_PM4_128BM_64INDBM:
0412         dev_priv->cce_fifo_size = 128;
0413         break;
0414     case R128_PM4_64PIO_128INDBM:
0415     case R128_PM4_64BM_128INDBM:
0416     case R128_PM4_64PIO_64VCBM_64INDBM:
0417     case R128_PM4_64BM_64VCBM_64INDBM:
0418     case R128_PM4_64PIO_64VCPIO_64INDPIO:
0419         dev_priv->cce_fifo_size = 64;
0420         break;
0421     }
0422 
0423     switch (init->fb_bpp) {
0424     case 16:
0425         dev_priv->color_fmt = R128_DATATYPE_RGB565;
0426         break;
0427     case 32:
0428     default:
0429         dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
0430         break;
0431     }
0432     dev_priv->front_offset = init->front_offset;
0433     dev_priv->front_pitch = init->front_pitch;
0434     dev_priv->back_offset = init->back_offset;
0435     dev_priv->back_pitch = init->back_pitch;
0436 
0437     switch (init->depth_bpp) {
0438     case 16:
0439         dev_priv->depth_fmt = R128_DATATYPE_RGB565;
0440         break;
0441     case 24:
0442     case 32:
0443     default:
0444         dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
0445         break;
0446     }
0447     dev_priv->depth_offset = init->depth_offset;
0448     dev_priv->depth_pitch = init->depth_pitch;
0449     dev_priv->span_offset = init->span_offset;
0450 
0451     dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
0452                       (dev_priv->front_offset >> 5));
0453     dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
0454                      (dev_priv->back_offset >> 5));
0455     dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
0456                       (dev_priv->depth_offset >> 5) |
0457                       R128_DST_TILE);
0458     dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
0459                      (dev_priv->span_offset >> 5));
0460 
0461     dev_priv->sarea = drm_legacy_getsarea(dev);
0462     if (!dev_priv->sarea) {
0463         DRM_ERROR("could not find sarea!\n");
0464         dev->dev_private = (void *)dev_priv;
0465         r128_do_cleanup_cce(dev);
0466         return -EINVAL;
0467     }
0468 
0469     dev_priv->mmio = drm_legacy_findmap(dev, init->mmio_offset);
0470     if (!dev_priv->mmio) {
0471         DRM_ERROR("could not find mmio region!\n");
0472         dev->dev_private = (void *)dev_priv;
0473         r128_do_cleanup_cce(dev);
0474         return -EINVAL;
0475     }
0476     dev_priv->cce_ring = drm_legacy_findmap(dev, init->ring_offset);
0477     if (!dev_priv->cce_ring) {
0478         DRM_ERROR("could not find cce ring region!\n");
0479         dev->dev_private = (void *)dev_priv;
0480         r128_do_cleanup_cce(dev);
0481         return -EINVAL;
0482     }
0483     dev_priv->ring_rptr = drm_legacy_findmap(dev, init->ring_rptr_offset);
0484     if (!dev_priv->ring_rptr) {
0485         DRM_ERROR("could not find ring read pointer!\n");
0486         dev->dev_private = (void *)dev_priv;
0487         r128_do_cleanup_cce(dev);
0488         return -EINVAL;
0489     }
0490     dev->agp_buffer_token = init->buffers_offset;
0491     dev->agp_buffer_map = drm_legacy_findmap(dev, init->buffers_offset);
0492     if (!dev->agp_buffer_map) {
0493         DRM_ERROR("could not find dma buffer region!\n");
0494         dev->dev_private = (void *)dev_priv;
0495         r128_do_cleanup_cce(dev);
0496         return -EINVAL;
0497     }
0498 
0499     if (!dev_priv->is_pci) {
0500         dev_priv->agp_textures =
0501             drm_legacy_findmap(dev, init->agp_textures_offset);
0502         if (!dev_priv->agp_textures) {
0503             DRM_ERROR("could not find agp texture region!\n");
0504             dev->dev_private = (void *)dev_priv;
0505             r128_do_cleanup_cce(dev);
0506             return -EINVAL;
0507         }
0508     }
0509 
0510     dev_priv->sarea_priv =
0511         (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
0512                   init->sarea_priv_offset);
0513 
0514 #if IS_ENABLED(CONFIG_AGP)
0515     if (!dev_priv->is_pci) {
0516         drm_legacy_ioremap_wc(dev_priv->cce_ring, dev);
0517         drm_legacy_ioremap_wc(dev_priv->ring_rptr, dev);
0518         drm_legacy_ioremap_wc(dev->agp_buffer_map, dev);
0519         if (!dev_priv->cce_ring->handle ||
0520             !dev_priv->ring_rptr->handle ||
0521             !dev->agp_buffer_map->handle) {
0522             DRM_ERROR("Could not ioremap agp regions!\n");
0523             dev->dev_private = (void *)dev_priv;
0524             r128_do_cleanup_cce(dev);
0525             return -ENOMEM;
0526         }
0527     } else
0528 #endif
0529     {
0530         dev_priv->cce_ring->handle =
0531             (void *)(unsigned long)dev_priv->cce_ring->offset;
0532         dev_priv->ring_rptr->handle =
0533             (void *)(unsigned long)dev_priv->ring_rptr->offset;
0534         dev->agp_buffer_map->handle =
0535             (void *)(unsigned long)dev->agp_buffer_map->offset;
0536     }
0537 
0538 #if IS_ENABLED(CONFIG_AGP)
0539     if (!dev_priv->is_pci)
0540         dev_priv->cce_buffers_offset = dev->agp->base;
0541     else
0542 #endif
0543         dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual;
0544 
0545     dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
0546     dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
0547                   + init->ring_size / sizeof(u32));
0548     dev_priv->ring.size = init->ring_size;
0549     dev_priv->ring.size_l2qw = order_base_2(init->ring_size / 8);
0550 
0551     dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
0552 
0553     dev_priv->ring.high_mark = 128;
0554 
0555     dev_priv->sarea_priv->last_frame = 0;
0556     R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
0557 
0558     dev_priv->sarea_priv->last_dispatch = 0;
0559     R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
0560 
0561 #if IS_ENABLED(CONFIG_AGP)
0562     if (dev_priv->is_pci) {
0563 #endif
0564         dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
0565         dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
0566         dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
0567         dev_priv->gart_info.addr = NULL;
0568         dev_priv->gart_info.bus_addr = 0;
0569         dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
0570         rc = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
0571         if (rc) {
0572             DRM_ERROR("failed to init PCI GART!\n");
0573             dev->dev_private = (void *)dev_priv;
0574             r128_do_cleanup_cce(dev);
0575             return rc;
0576         }
0577         R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
0578 #if IS_ENABLED(CONFIG_AGP)
0579     }
0580 #endif
0581 
0582     r128_cce_init_ring_buffer(dev, dev_priv);
0583     rc = r128_cce_load_microcode(dev_priv);
0584 
0585     dev->dev_private = (void *)dev_priv;
0586 
0587     r128_do_engine_reset(dev);
0588 
0589     if (rc) {
0590         DRM_ERROR("Failed to load firmware!\n");
0591         r128_do_cleanup_cce(dev);
0592     }
0593 
0594     return rc;
0595 }
0596 
0597 int r128_do_cleanup_cce(struct drm_device *dev)
0598 {
0599 
0600     /* Make sure interrupts are disabled here because the uninstall ioctl
0601      * may not have been called from userspace and after dev_private
0602      * is freed, it's too late.
0603      */
0604     if (dev->irq_enabled)
0605         drm_legacy_irq_uninstall(dev);
0606 
0607     if (dev->dev_private) {
0608         drm_r128_private_t *dev_priv = dev->dev_private;
0609 
0610 #if IS_ENABLED(CONFIG_AGP)
0611         if (!dev_priv->is_pci) {
0612             if (dev_priv->cce_ring != NULL)
0613                 drm_legacy_ioremapfree(dev_priv->cce_ring, dev);
0614             if (dev_priv->ring_rptr != NULL)
0615                 drm_legacy_ioremapfree(dev_priv->ring_rptr, dev);
0616             if (dev->agp_buffer_map != NULL) {
0617                 drm_legacy_ioremapfree(dev->agp_buffer_map, dev);
0618                 dev->agp_buffer_map = NULL;
0619             }
0620         } else
0621 #endif
0622         {
0623             if (dev_priv->gart_info.bus_addr)
0624                 if (!drm_ati_pcigart_cleanup(dev,
0625                             &dev_priv->gart_info))
0626                     DRM_ERROR
0627                         ("failed to cleanup PCI GART!\n");
0628         }
0629 
0630         kfree(dev->dev_private);
0631         dev->dev_private = NULL;
0632     }
0633 
0634     return 0;
0635 }
0636 
0637 int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
0638 {
0639     drm_r128_init_t *init = data;
0640 
0641     DRM_DEBUG("\n");
0642 
0643     LOCK_TEST_WITH_RETURN(dev, file_priv);
0644 
0645     switch (init->func) {
0646     case R128_INIT_CCE:
0647         return r128_do_init_cce(dev, init);
0648     case R128_CLEANUP_CCE:
0649         return r128_do_cleanup_cce(dev);
0650     }
0651 
0652     return -EINVAL;
0653 }
0654 
0655 int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
0656 {
0657     drm_r128_private_t *dev_priv = dev->dev_private;
0658     DRM_DEBUG("\n");
0659 
0660     LOCK_TEST_WITH_RETURN(dev, file_priv);
0661 
0662     DEV_INIT_TEST_WITH_RETURN(dev_priv);
0663 
0664     if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
0665         DRM_DEBUG("while CCE running\n");
0666         return 0;
0667     }
0668 
0669     r128_do_cce_start(dev_priv);
0670 
0671     return 0;
0672 }
0673 
0674 /* Stop the CCE.  The engine must have been idled before calling this
0675  * routine.
0676  */
0677 int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
0678 {
0679     drm_r128_private_t *dev_priv = dev->dev_private;
0680     drm_r128_cce_stop_t *stop = data;
0681     int ret;
0682     DRM_DEBUG("\n");
0683 
0684     LOCK_TEST_WITH_RETURN(dev, file_priv);
0685 
0686     DEV_INIT_TEST_WITH_RETURN(dev_priv);
0687 
0688     /* Flush any pending CCE commands.  This ensures any outstanding
0689      * commands are exectuted by the engine before we turn it off.
0690      */
0691     if (stop->flush)
0692         r128_do_cce_flush(dev_priv);
0693 
0694     /* If we fail to make the engine go idle, we return an error
0695      * code so that the DRM ioctl wrapper can try again.
0696      */
0697     if (stop->idle) {
0698         ret = r128_do_cce_idle(dev_priv);
0699         if (ret)
0700             return ret;
0701     }
0702 
0703     /* Finally, we can turn off the CCE.  If the engine isn't idle,
0704      * we will get some dropped triangles as they won't be fully
0705      * rendered before the CCE is shut down.
0706      */
0707     r128_do_cce_stop(dev_priv);
0708 
0709     /* Reset the engine */
0710     r128_do_engine_reset(dev);
0711 
0712     return 0;
0713 }
0714 
0715 /* Just reset the CCE ring.  Called as part of an X Server engine reset.
0716  */
0717 int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
0718 {
0719     drm_r128_private_t *dev_priv = dev->dev_private;
0720     DRM_DEBUG("\n");
0721 
0722     LOCK_TEST_WITH_RETURN(dev, file_priv);
0723 
0724     DEV_INIT_TEST_WITH_RETURN(dev_priv);
0725 
0726     r128_do_cce_reset(dev_priv);
0727 
0728     /* The CCE is no longer running after an engine reset */
0729     dev_priv->cce_running = 0;
0730 
0731     return 0;
0732 }
0733 
0734 int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
0735 {
0736     drm_r128_private_t *dev_priv = dev->dev_private;
0737     DRM_DEBUG("\n");
0738 
0739     LOCK_TEST_WITH_RETURN(dev, file_priv);
0740 
0741     DEV_INIT_TEST_WITH_RETURN(dev_priv);
0742 
0743     if (dev_priv->cce_running)
0744         r128_do_cce_flush(dev_priv);
0745 
0746     return r128_do_cce_idle(dev_priv);
0747 }
0748 
0749 int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
0750 {
0751     DRM_DEBUG("\n");
0752 
0753     LOCK_TEST_WITH_RETURN(dev, file_priv);
0754 
0755     DEV_INIT_TEST_WITH_RETURN(dev->dev_private);
0756 
0757     return r128_do_engine_reset(dev);
0758 }
0759 
0760 int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
0761 {
0762     return -EINVAL;
0763 }
0764 
0765 /* ================================================================
0766  * Freelist management
0767  */
0768 #define R128_BUFFER_USED    0xffffffff
0769 #define R128_BUFFER_FREE    0
0770 
0771 #if 0
0772 static int r128_freelist_init(struct drm_device *dev)
0773 {
0774     struct drm_device_dma *dma = dev->dma;
0775     drm_r128_private_t *dev_priv = dev->dev_private;
0776     struct drm_buf *buf;
0777     drm_r128_buf_priv_t *buf_priv;
0778     drm_r128_freelist_t *entry;
0779     int i;
0780 
0781     dev_priv->head = kzalloc(sizeof(drm_r128_freelist_t), GFP_KERNEL);
0782     if (dev_priv->head == NULL)
0783         return -ENOMEM;
0784 
0785     dev_priv->head->age = R128_BUFFER_USED;
0786 
0787     for (i = 0; i < dma->buf_count; i++) {
0788         buf = dma->buflist[i];
0789         buf_priv = buf->dev_private;
0790 
0791         entry = kmalloc(sizeof(drm_r128_freelist_t), GFP_KERNEL);
0792         if (!entry)
0793             return -ENOMEM;
0794 
0795         entry->age = R128_BUFFER_FREE;
0796         entry->buf = buf;
0797         entry->prev = dev_priv->head;
0798         entry->next = dev_priv->head->next;
0799         if (!entry->next)
0800             dev_priv->tail = entry;
0801 
0802         buf_priv->discard = 0;
0803         buf_priv->dispatched = 0;
0804         buf_priv->list_entry = entry;
0805 
0806         dev_priv->head->next = entry;
0807 
0808         if (dev_priv->head->next)
0809             dev_priv->head->next->prev = entry;
0810     }
0811 
0812     return 0;
0813 
0814 }
0815 #endif
0816 
0817 static struct drm_buf *r128_freelist_get(struct drm_device * dev)
0818 {
0819     struct drm_device_dma *dma = dev->dma;
0820     drm_r128_private_t *dev_priv = dev->dev_private;
0821     drm_r128_buf_priv_t *buf_priv;
0822     struct drm_buf *buf;
0823     int i, t;
0824 
0825     /* FIXME: Optimize -- use freelist code */
0826 
0827     for (i = 0; i < dma->buf_count; i++) {
0828         buf = dma->buflist[i];
0829         buf_priv = buf->dev_private;
0830         if (!buf->file_priv)
0831             return buf;
0832     }
0833 
0834     for (t = 0; t < dev_priv->usec_timeout; t++) {
0835         u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
0836 
0837         for (i = 0; i < dma->buf_count; i++) {
0838             buf = dma->buflist[i];
0839             buf_priv = buf->dev_private;
0840             if (buf->pending && buf_priv->age <= done_age) {
0841                 /* The buffer has been processed, so it
0842                  * can now be used.
0843                  */
0844                 buf->pending = 0;
0845                 return buf;
0846             }
0847         }
0848         udelay(1);
0849     }
0850 
0851     DRM_DEBUG("returning NULL!\n");
0852     return NULL;
0853 }
0854 
0855 void r128_freelist_reset(struct drm_device *dev)
0856 {
0857     struct drm_device_dma *dma = dev->dma;
0858     int i;
0859 
0860     for (i = 0; i < dma->buf_count; i++) {
0861         struct drm_buf *buf = dma->buflist[i];
0862         drm_r128_buf_priv_t *buf_priv = buf->dev_private;
0863         buf_priv->age = 0;
0864     }
0865 }
0866 
0867 /* ================================================================
0868  * CCE command submission
0869  */
0870 
0871 int r128_wait_ring(drm_r128_private_t *dev_priv, int n)
0872 {
0873     drm_r128_ring_buffer_t *ring = &dev_priv->ring;
0874     int i;
0875 
0876     for (i = 0; i < dev_priv->usec_timeout; i++) {
0877         r128_update_ring_snapshot(dev_priv);
0878         if (ring->space >= n)
0879             return 0;
0880         udelay(1);
0881     }
0882 
0883     /* FIXME: This is being ignored... */
0884     DRM_ERROR("failed!\n");
0885     return -EBUSY;
0886 }
0887 
0888 static int r128_cce_get_buffers(struct drm_device *dev,
0889                 struct drm_file *file_priv,
0890                 struct drm_dma *d)
0891 {
0892     int i;
0893     struct drm_buf *buf;
0894 
0895     for (i = d->granted_count; i < d->request_count; i++) {
0896         buf = r128_freelist_get(dev);
0897         if (!buf)
0898             return -EAGAIN;
0899 
0900         buf->file_priv = file_priv;
0901 
0902         if (copy_to_user(&d->request_indices[i], &buf->idx,
0903                      sizeof(buf->idx)))
0904             return -EFAULT;
0905         if (copy_to_user(&d->request_sizes[i], &buf->total,
0906                      sizeof(buf->total)))
0907             return -EFAULT;
0908 
0909         d->granted_count++;
0910     }
0911     return 0;
0912 }
0913 
0914 int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
0915 {
0916     struct drm_device_dma *dma = dev->dma;
0917     int ret = 0;
0918     struct drm_dma *d = data;
0919 
0920     LOCK_TEST_WITH_RETURN(dev, file_priv);
0921 
0922     /* Please don't send us buffers.
0923      */
0924     if (d->send_count != 0) {
0925         DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
0926               task_pid_nr(current), d->send_count);
0927         return -EINVAL;
0928     }
0929 
0930     /* We'll send you buffers.
0931      */
0932     if (d->request_count < 0 || d->request_count > dma->buf_count) {
0933         DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
0934               task_pid_nr(current), d->request_count, dma->buf_count);
0935         return -EINVAL;
0936     }
0937 
0938     d->granted_count = 0;
0939 
0940     if (d->request_count)
0941         ret = r128_cce_get_buffers(dev, file_priv, d);
0942 
0943     return ret;
0944 }
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