drm/pl111/pl111_drm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *
0004  * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
0005  *
0006  * Parts of this file were based on sources as follows:
0007  *
0008  * Copyright (c) 2006-2008 Intel Corporation
0009  * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
0010  * Copyright (C) 2011 Texas Instruments
0011  */
0012
0013 #ifndef _PL111_DRM_H_
0014 #define _PL111_DRM_H_
0015
0016 #include <linux/clk-provider.h>
0017 #include <linux/interrupt.h>
0018
0019 #include <drm/drm_bridge.h>
0020 #include <drm/drm_connector.h>
0021 #include <drm/drm_encoder.h>
0022 #include <drm/drm_gem.h>
0023 #include <drm/drm_panel.h>
0024 #include <drm/drm_simple_kms_helper.h>
0025
0026 /*
0027  * CLCD Controller Internal Register addresses
0028  */
0029 #define CLCD_TIM0       0x00000000
0030 #define CLCD_TIM1       0x00000004
0031 #define CLCD_TIM2       0x00000008
0032 #define CLCD_TIM3       0x0000000c
0033 #define CLCD_UBAS       0x00000010
0034 #define CLCD_LBAS       0x00000014
0035
0036 #define CLCD_PL110_IENB     0x00000018
0037 #define CLCD_PL110_CNTL     0x0000001c
0038 #define CLCD_PL110_STAT     0x00000020
0039 #define CLCD_PL110_INTR     0x00000024
0040 #define CLCD_PL110_UCUR     0x00000028
0041 #define CLCD_PL110_LCUR     0x0000002C
0042
0043 #define CLCD_PL111_CNTL     0x00000018
0044 #define CLCD_PL111_IENB     0x0000001c
0045 #define CLCD_PL111_RIS      0x00000020
0046 #define CLCD_PL111_MIS      0x00000024
0047 #define CLCD_PL111_ICR      0x00000028
0048 #define CLCD_PL111_UCUR     0x0000002c
0049 #define CLCD_PL111_LCUR     0x00000030
0050
0051 #define CLCD_PALL       0x00000200
0052 #define CLCD_PALETTE        0x00000200
0053
0054 #define TIM2_PCD_LO_MASK    GENMASK(4, 0)
0055 #define TIM2_PCD_LO_BITS    5
0056 #define TIM2_CLKSEL     (1 << 5)
0057 #define TIM2_ACB_MASK       GENMASK(10, 6)
0058 #define TIM2_IVS        (1 << 11)
0059 #define TIM2_IHS        (1 << 12)
0060 #define TIM2_IPC        (1 << 13)
0061 #define TIM2_IOE        (1 << 14)
0062 #define TIM2_BCD        (1 << 26)
0063 #define TIM2_PCD_HI_MASK    GENMASK(31, 27)
0064 #define TIM2_PCD_HI_BITS    5
0065 #define TIM2_PCD_HI_SHIFT   27
0066
0067 #define CNTL_LCDEN      (1 << 0)
0068 #define CNTL_LCDBPP1        (0 << 1)
0069 #define CNTL_LCDBPP2        (1 << 1)
0070 #define CNTL_LCDBPP4        (2 << 1)
0071 #define CNTL_LCDBPP8        (3 << 1)
0072 #define CNTL_LCDBPP16       (4 << 1)
0073 #define CNTL_LCDBPP16_565   (6 << 1)
0074 #define CNTL_LCDBPP16_444   (7 << 1)
0075 #define CNTL_LCDBPP24       (5 << 1)
0076 #define CNTL_LCDBW      (1 << 4)
0077 #define CNTL_LCDTFT     (1 << 5)
0078 #define CNTL_LCDMONO8       (1 << 6)
0079 #define CNTL_LCDDUAL        (1 << 7)
0080 #define CNTL_BGR        (1 << 8)
0081 #define CNTL_BEBO       (1 << 9)
0082 #define CNTL_BEPO       (1 << 10)
0083 #define CNTL_LCDPWR     (1 << 11)
0084 #define CNTL_LCDVCOMP(x)    ((x) << 12)
0085 #define CNTL_LDMAFIFOTIME   (1 << 15)
0086 #define CNTL_WATERMARK      (1 << 16)
0087
0088 /* ST Microelectronics variant bits */
0089 #define CNTL_ST_1XBPP_444   0x0
0090 #define CNTL_ST_1XBPP_5551  (1 << 17)
0091 #define CNTL_ST_1XBPP_565   (1 << 18)
0092 #define CNTL_ST_CDWID_12    0x0
0093 #define CNTL_ST_CDWID_16    (1 << 19)
0094 #define CNTL_ST_CDWID_18    (1 << 20)
0095 #define CNTL_ST_CDWID_24    ((1 << 19) | (1 << 20))
0096 #define CNTL_ST_CEAEN       (1 << 21)
0097 #define CNTL_ST_LCDBPP24_PACKED (6 << 1)
0098
0099 #define CLCD_IRQ_NEXTBASE_UPDATE BIT(2)
0100
0101 struct drm_minor;
0102
0103 /**
0104  * struct pl111_variant_data - encodes IP differences
0105  * @name: the name of this variant
0106  * @is_pl110: this is the early PL110 variant
0107  * @is_lcdc: this is the ST Microelectronics Nomadik LCDC variant
0108  * @external_bgr: this is the Versatile Pl110 variant with external
0109  *  BGR/RGB routing
0110  * @broken_clockdivider: the clock divider is broken and we need to
0111  *  use the supplied clock directly
0112  * @broken_vblank: the vblank IRQ is broken on this variant
0113  * @st_bitmux_control: this variant is using the ST Micro bitmux
0114  *  extensions to the control register
0115  * @formats: array of supported pixel formats on this variant
0116  * @nformats: the length of the array of supported pixel formats
0117  * @fb_bpp: desired bits per pixel on the default framebuffer
0118  */
0119 struct pl111_variant_data {
0120     const char *name;
0121     bool is_pl110;
0122     bool is_lcdc;
0123     bool external_bgr;
0124     bool broken_clockdivider;
0125     bool broken_vblank;
0126     bool st_bitmux_control;
0127     const u32 *formats;
0128     unsigned int nformats;
0129     unsigned int fb_bpp;
0130 };
0131
0132 struct pl111_drm_dev_private {
0133     struct drm_device *drm;
0134
0135     struct drm_connector *connector;
0136     struct drm_panel *panel;
0137     struct drm_bridge *bridge;
0138     struct drm_simple_display_pipe pipe;
0139
0140     void *regs;
0141     u32 memory_bw;
0142     u32 ienb;
0143     u32 ctrl;
0144     /* The pixel clock (a reference to our clock divider off of CLCDCLK). */
0145     struct clk *clk;
0146     /* pl111's internal clock divider. */
0147     struct clk_hw clk_div;
0148     /* Lock to sync access to CLCD_TIM2 between the common clock
0149      * subsystem and pl111_display_enable().
0150      */
0151     spinlock_t tim2_lock;
0152     const struct pl111_variant_data *variant;
0153     void (*variant_display_enable) (struct drm_device *drm, u32 format);
0154     void (*variant_display_disable) (struct drm_device *drm);
0155     bool use_device_memory;
0156 };
0157
0158 int pl111_display_init(struct drm_device *dev);
0159 irqreturn_t pl111_irq(int irq, void *data);
0160 void pl111_debugfs_init(struct drm_minor *minor);
0161
0162 #endif /* _PL111_DRM_H_ */