drm/pl111/pl111_display.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
0004  *
0005  * Parts of this file were based on sources as follows:
0006  *
0007  * Copyright (c) 2006-2008 Intel Corporation
0008  * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
0009  * Copyright (C) 2011 Texas Instruments
0010  */
0011
0012 #include <linux/clk.h>
0013 #include <linux/delay.h>
0014 #include <linux/dma-buf.h>
0015 #include <linux/media-bus-format.h>
0016 #include <linux/of_graph.h>
0017
0018 #include <drm/drm_fb_cma_helper.h>
0019 #include <drm/drm_fourcc.h>
0020 #include <drm/drm_framebuffer.h>
0021 #include <drm/drm_gem_atomic_helper.h>
0022 #include <drm/drm_gem_cma_helper.h>
0023 #include <drm/drm_vblank.h>
0024
0025 #include "pl111_drm.h"
0026
0027 irqreturn_t pl111_irq(int irq, void *data)
0028 {
0029     struct pl111_drm_dev_private *priv = data;
0030     u32 irq_stat;
0031     irqreturn_t status = IRQ_NONE;
0032
0033     irq_stat = readl(priv->regs + CLCD_PL111_MIS);
0034
0035     if (!irq_stat)
0036         return IRQ_NONE;
0037
0038     if (irq_stat & CLCD_IRQ_NEXTBASE_UPDATE) {
0039         drm_crtc_handle_vblank(&priv->pipe.crtc);
0040
0041         status = IRQ_HANDLED;
0042     }
0043
0044     /* Clear the interrupt once done */
0045     writel(irq_stat, priv->regs + CLCD_PL111_ICR);
0046
0047     return status;
0048 }
0049
0050 static enum drm_mode_status
0051 pl111_mode_valid(struct drm_simple_display_pipe *pipe,
0052          const struct drm_display_mode *mode)
0053 {
0054     struct drm_device *drm = pipe->crtc.dev;
0055     struct pl111_drm_dev_private *priv = drm->dev_private;
0056     u32 cpp = priv->variant->fb_bpp / 8;
0057     u64 bw;
0058
0059     /*
0060      * We use the pixelclock to also account for interlaced modes, the
0061      * resulting bandwidth is in bytes per second.
0062      */
0063     bw = mode->clock * 1000ULL; /* In Hz */
0064     bw = bw * mode->hdisplay * mode->vdisplay * cpp;
0065     bw = div_u64(bw, mode->htotal * mode->vtotal);
0066
0067     /*
0068      * If no bandwidth constraints, anything goes, else
0069      * check if we are too fast.
0070      */
0071     if (priv->memory_bw && (bw > priv->memory_bw)) {
0072         DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu too fast\n",
0073                   mode->hdisplay, mode->vdisplay,
0074                   mode->clock * 1000, cpp, bw);
0075
0076         return MODE_BAD;
0077     }
0078     DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu bytes/s OK\n",
0079               mode->hdisplay, mode->vdisplay,
0080               mode->clock * 1000, cpp, bw);
0081
0082     return MODE_OK;
0083 }
0084
0085 static int pl111_display_check(struct drm_simple_display_pipe *pipe,
0086                    struct drm_plane_state *pstate,
0087                    struct drm_crtc_state *cstate)
0088 {
0089     const struct drm_display_mode *mode = &cstate->mode;
0090     struct drm_framebuffer *old_fb = pipe->plane.state->fb;
0091     struct drm_framebuffer *fb = pstate->fb;
0092
0093     if (mode->hdisplay % 16)
0094         return -EINVAL;
0095
0096     if (fb) {
0097         u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0);
0098
0099         /* FB base address must be dword aligned. */
0100         if (offset & 3)
0101             return -EINVAL;
0102
0103         /* There's no pitch register -- the mode's hdisplay
0104          * controls it.
0105          */
0106         if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0])
0107             return -EINVAL;
0108
0109         /* We can't change the FB format in a flicker-free
0110          * manner (and only update it during CRTC enable).
0111          */
0112         if (old_fb && old_fb->format != fb->format)
0113             cstate->mode_changed = true;
0114     }
0115
0116     return 0;
0117 }
0118
0119 static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
0120                  struct drm_crtc_state *cstate,
0121                  struct drm_plane_state *plane_state)
0122 {
0123     struct drm_crtc *crtc = &pipe->crtc;
0124     struct drm_plane *plane = &pipe->plane;
0125     struct drm_device *drm = crtc->dev;
0126     struct pl111_drm_dev_private *priv = drm->dev_private;
0127     const struct drm_display_mode *mode = &cstate->mode;
0128     struct drm_framebuffer *fb = plane->state->fb;
0129     struct drm_connector *connector = priv->connector;
0130     struct drm_bridge *bridge = priv->bridge;
0131     bool grayscale = false;
0132     u32 cntl;
0133     u32 ppl, hsw, hfp, hbp;
0134     u32 lpp, vsw, vfp, vbp;
0135     u32 cpl, tim2;
0136     int ret;
0137
0138     ret = clk_set_rate(priv->clk, mode->clock * 1000);
0139     if (ret) {
0140         dev_err(drm->dev,
0141             "Failed to set pixel clock rate to %d: %d\n",
0142             mode->clock * 1000, ret);
0143     }
0144
0145     clk_prepare_enable(priv->clk);
0146
0147     ppl = (mode->hdisplay / 16) - 1;
0148     hsw = mode->hsync_end - mode->hsync_start - 1;
0149     hfp = mode->hsync_start - mode->hdisplay - 1;
0150     hbp = mode->htotal - mode->hsync_end - 1;
0151
0152     lpp = mode->vdisplay - 1;
0153     vsw = mode->vsync_end - mode->vsync_start - 1;
0154     vfp = mode->vsync_start - mode->vdisplay;
0155     vbp = mode->vtotal - mode->vsync_end;
0156
0157     cpl = mode->hdisplay - 1;
0158
0159     writel((ppl << 2) |
0160            (hsw << 8) |
0161            (hfp << 16) |
0162            (hbp << 24),
0163            priv->regs + CLCD_TIM0);
0164     writel(lpp |
0165            (vsw << 10) |
0166            (vfp << 16) |
0167            (vbp << 24),
0168            priv->regs + CLCD_TIM1);
0169
0170     spin_lock(&priv->tim2_lock);
0171
0172     tim2 = readl(priv->regs + CLCD_TIM2);
0173     tim2 &= (TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK);
0174
0175     if (priv->variant->broken_clockdivider)
0176         tim2 |= TIM2_BCD;
0177
0178     if (mode->flags & DRM_MODE_FLAG_NHSYNC)
0179         tim2 |= TIM2_IHS;
0180
0181     if (mode->flags & DRM_MODE_FLAG_NVSYNC)
0182         tim2 |= TIM2_IVS;
0183
0184     if (connector) {
0185         if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
0186             tim2 |= TIM2_IOE;
0187
0188         if (connector->display_info.bus_flags &
0189             DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
0190             tim2 |= TIM2_IPC;
0191
0192         if (connector->display_info.num_bus_formats == 1 &&
0193             connector->display_info.bus_formats[0] ==
0194             MEDIA_BUS_FMT_Y8_1X8)
0195             grayscale = true;
0196
0197         /*
0198          * The AC pin bias frequency is set to max count when using
0199          * grayscale so at least once in a while we will reverse
0200          * polarity and get rid of any DC built up that could
0201          * damage the display.
0202          */
0203         if (grayscale)
0204             tim2 |= TIM2_ACB_MASK;
0205     }
0206
0207     if (bridge) {
0208         const struct drm_bridge_timings *btimings = bridge->timings;
0209
0210         /*
0211          * Here is when things get really fun. Sometimes the bridge
0212          * timings are such that the signal out from PL11x is not
0213          * stable before the receiving bridge (such as a dumb VGA DAC
0214          * or similar) samples it. If that happens, we compensate by
0215          * the only method we have: output the data on the opposite
0216          * edge of the clock so it is for sure stable when it gets
0217          * sampled.
0218          *
0219          * The PL111 manual does not contain proper timining diagrams
0220          * or data for these details, but we know from experiments
0221          * that the setup time is more than 3000 picoseconds (3 ns).
0222          * If we have a bridge that requires the signal to be stable
0223          * earlier than 3000 ps before the clock pulse, we have to
0224          * output the data on the opposite edge to avoid flicker.
0225          */
0226         if (btimings && btimings->setup_time_ps >= 3000)
0227             tim2 ^= TIM2_IPC;
0228     }
0229
0230     tim2 |= cpl << 16;
0231     writel(tim2, priv->regs + CLCD_TIM2);
0232     spin_unlock(&priv->tim2_lock);
0233
0234     writel(0, priv->regs + CLCD_TIM3);
0235
0236     /*
0237      * Detect grayscale bus format. We do not support a grayscale mode
0238      * toward userspace, instead we expose an RGB24 buffer and then the
0239      * hardware will activate its grayscaler to convert to the grayscale
0240      * format.
0241      */
0242     if (grayscale)
0243         cntl = CNTL_LCDEN | CNTL_LCDMONO8;
0244     else
0245         /* Else we assume TFT display */
0246         cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1);
0247
0248     /* On the ST Micro variant, assume all 24 bits are connected */
0249     if (priv->variant->st_bitmux_control)
0250         cntl |= CNTL_ST_CDWID_24;
0251
0252     /*
0253      * Note that the ARM hardware's format reader takes 'r' from
0254      * the low bit, while DRM formats list channels from high bit
0255      * to low bit as you read left to right. The ST Micro version of
0256      * the PL110 (LCDC) however uses the standard DRM format.
0257      */
0258     switch (fb->format->format) {
0259     case DRM_FORMAT_BGR888:
0260         /* Only supported on the ST Micro variant */
0261         if (priv->variant->st_bitmux_control)
0262             cntl |= CNTL_ST_LCDBPP24_PACKED | CNTL_BGR;
0263         break;
0264     case DRM_FORMAT_RGB888:
0265         /* Only supported on the ST Micro variant */
0266         if (priv->variant->st_bitmux_control)
0267             cntl |= CNTL_ST_LCDBPP24_PACKED;
0268         break;
0269     case DRM_FORMAT_ABGR8888:
0270     case DRM_FORMAT_XBGR8888:
0271         if (priv->variant->st_bitmux_control)
0272             cntl |= CNTL_LCDBPP24 | CNTL_BGR;
0273         else
0274             cntl |= CNTL_LCDBPP24;
0275         break;
0276     case DRM_FORMAT_ARGB8888:
0277     case DRM_FORMAT_XRGB8888:
0278         if (priv->variant->st_bitmux_control)
0279             cntl |= CNTL_LCDBPP24;
0280         else
0281             cntl |= CNTL_LCDBPP24 | CNTL_BGR;
0282         break;
0283     case DRM_FORMAT_BGR565:
0284         if (priv->variant->is_pl110)
0285             cntl |= CNTL_LCDBPP16;
0286         else if (priv->variant->st_bitmux_control)
0287             cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565 | CNTL_BGR;
0288         else
0289             cntl |= CNTL_LCDBPP16_565;
0290         break;
0291     case DRM_FORMAT_RGB565:
0292         if (priv->variant->is_pl110)
0293             cntl |= CNTL_LCDBPP16 | CNTL_BGR;
0294         else if (priv->variant->st_bitmux_control)
0295             cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565;
0296         else
0297             cntl |= CNTL_LCDBPP16_565 | CNTL_BGR;
0298         break;
0299     case DRM_FORMAT_ABGR1555:
0300     case DRM_FORMAT_XBGR1555:
0301         cntl |= CNTL_LCDBPP16;
0302         if (priv->variant->st_bitmux_control)
0303             cntl |= CNTL_ST_1XBPP_5551 | CNTL_BGR;
0304         break;
0305     case DRM_FORMAT_ARGB1555:
0306     case DRM_FORMAT_XRGB1555:
0307         cntl |= CNTL_LCDBPP16;
0308         if (priv->variant->st_bitmux_control)
0309             cntl |= CNTL_ST_1XBPP_5551;
0310         else
0311             cntl |= CNTL_BGR;
0312         break;
0313     case DRM_FORMAT_ABGR4444:
0314     case DRM_FORMAT_XBGR4444:
0315         cntl |= CNTL_LCDBPP16_444;
0316         if (priv->variant->st_bitmux_control)
0317             cntl |= CNTL_ST_1XBPP_444 | CNTL_BGR;
0318         break;
0319     case DRM_FORMAT_ARGB4444:
0320     case DRM_FORMAT_XRGB4444:
0321         cntl |= CNTL_LCDBPP16_444;
0322         if (priv->variant->st_bitmux_control)
0323             cntl |= CNTL_ST_1XBPP_444;
0324         else
0325             cntl |= CNTL_BGR;
0326         break;
0327     default:
0328         WARN_ONCE(true, "Unknown FB format 0x%08x\n",
0329               fb->format->format);
0330         break;
0331     }
0332
0333     /* The PL110 in Integrator/Versatile does the BGR routing externally */
0334     if (priv->variant->external_bgr)
0335         cntl &= ~CNTL_BGR;
0336
0337     /* Power sequence: first enable and chill */
0338     writel(cntl, priv->regs + priv->ctrl);
0339
0340     /*
0341      * We expect this delay to stabilize the contrast
0342      * voltage Vee as stipulated by the manual
0343      */
0344     msleep(20);
0345
0346     if (priv->variant_display_enable)
0347         priv->variant_display_enable(drm, fb->format->format);
0348
0349     /* Power Up */
0350     cntl |= CNTL_LCDPWR;
0351     writel(cntl, priv->regs + priv->ctrl);
0352
0353     if (!priv->variant->broken_vblank)
0354         drm_crtc_vblank_on(crtc);
0355 }
0356
0357 static void pl111_display_disable(struct drm_simple_display_pipe *pipe)
0358 {
0359     struct drm_crtc *crtc = &pipe->crtc;
0360     struct drm_device *drm = crtc->dev;
0361     struct pl111_drm_dev_private *priv = drm->dev_private;
0362     u32 cntl;
0363
0364     if (!priv->variant->broken_vblank)
0365         drm_crtc_vblank_off(crtc);
0366
0367     /* Power Down */
0368     cntl = readl(priv->regs + priv->ctrl);
0369     if (cntl & CNTL_LCDPWR) {
0370         cntl &= ~CNTL_LCDPWR;
0371         writel(cntl, priv->regs + priv->ctrl);
0372     }
0373
0374     /*
0375      * We expect this delay to stabilize the contrast voltage Vee as
0376      * stipulated by the manual
0377      */
0378     msleep(20);
0379
0380     if (priv->variant_display_disable)
0381         priv->variant_display_disable(drm);
0382
0383     /* Disable */
0384     writel(0, priv->regs + priv->ctrl);
0385
0386     clk_disable_unprepare(priv->clk);
0387 }
0388
0389 static void pl111_display_update(struct drm_simple_display_pipe *pipe,
0390                  struct drm_plane_state *old_pstate)
0391 {
0392     struct drm_crtc *crtc = &pipe->crtc;
0393     struct drm_device *drm = crtc->dev;
0394     struct pl111_drm_dev_private *priv = drm->dev_private;
0395     struct drm_pending_vblank_event *event = crtc->state->event;
0396     struct drm_plane *plane = &pipe->plane;
0397     struct drm_plane_state *pstate = plane->state;
0398     struct drm_framebuffer *fb = pstate->fb;
0399
0400     if (fb) {
0401         u32 addr = drm_fb_cma_get_gem_addr(fb, pstate, 0);
0402
0403         writel(addr, priv->regs + CLCD_UBAS);
0404     }
0405
0406     if (event) {
0407         crtc->state->event = NULL;
0408
0409         spin_lock_irq(&crtc->dev->event_lock);
0410         if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0)
0411             drm_crtc_arm_vblank_event(crtc, event);
0412         else
0413             drm_crtc_send_vblank_event(crtc, event);
0414         spin_unlock_irq(&crtc->dev->event_lock);
0415     }
0416 }
0417
0418 static int pl111_display_enable_vblank(struct drm_simple_display_pipe *pipe)
0419 {
0420     struct drm_crtc *crtc = &pipe->crtc;
0421     struct drm_device *drm = crtc->dev;
0422     struct pl111_drm_dev_private *priv = drm->dev_private;
0423
0424     writel(CLCD_IRQ_NEXTBASE_UPDATE, priv->regs + priv->ienb);
0425
0426     return 0;
0427 }
0428
0429 static void pl111_display_disable_vblank(struct drm_simple_display_pipe *pipe)
0430 {
0431     struct drm_crtc *crtc = &pipe->crtc;
0432     struct drm_device *drm = crtc->dev;
0433     struct pl111_drm_dev_private *priv = drm->dev_private;
0434
0435     writel(0, priv->regs + priv->ienb);
0436 }
0437
0438 static struct drm_simple_display_pipe_funcs pl111_display_funcs = {
0439     .mode_valid = pl111_mode_valid,
0440     .check = pl111_display_check,
0441     .enable = pl111_display_enable,
0442     .disable = pl111_display_disable,
0443     .update = pl111_display_update,
0444 };
0445
0446 static int pl111_clk_div_choose_div(struct clk_hw *hw, unsigned long rate,
0447                     unsigned long *prate, bool set_parent)
0448 {
0449     int best_div = 1, div;
0450     struct clk_hw *parent = clk_hw_get_parent(hw);
0451     unsigned long best_prate = 0;
0452     unsigned long best_diff = ~0ul;
0453     int max_div = (1 << (TIM2_PCD_LO_BITS + TIM2_PCD_HI_BITS)) - 1;
0454
0455     for (div = 1; div < max_div; div++) {
0456         unsigned long this_prate, div_rate, diff;
0457
0458         if (set_parent)
0459             this_prate = clk_hw_round_rate(parent, rate * div);
0460         else
0461             this_prate = *prate;
0462         div_rate = DIV_ROUND_UP_ULL(this_prate, div);
0463         diff = abs(rate - div_rate);
0464
0465         if (diff < best_diff) {
0466             best_div = div;
0467             best_diff = diff;
0468             best_prate = this_prate;
0469         }
0470     }
0471
0472     *prate = best_prate;
0473     return best_div;
0474 }
0475
0476 static long pl111_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
0477                      unsigned long *prate)
0478 {
0479     int div = pl111_clk_div_choose_div(hw, rate, prate, true);
0480
0481     return DIV_ROUND_UP_ULL(*prate, div);
0482 }
0483
0484 static unsigned long pl111_clk_div_recalc_rate(struct clk_hw *hw,
0485                            unsigned long prate)
0486 {
0487     struct pl111_drm_dev_private *priv =
0488         container_of(hw, struct pl111_drm_dev_private, clk_div);
0489     u32 tim2 = readl(priv->regs + CLCD_TIM2);
0490     int div;
0491
0492     if (tim2 & TIM2_BCD)
0493         return prate;
0494
0495     div = tim2 & TIM2_PCD_LO_MASK;
0496     div |= (tim2 & TIM2_PCD_HI_MASK) >>
0497         (TIM2_PCD_HI_SHIFT - TIM2_PCD_LO_BITS);
0498     div += 2;
0499
0500     return DIV_ROUND_UP_ULL(prate, div);
0501 }
0502
0503 static int pl111_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
0504                   unsigned long prate)
0505 {
0506     struct pl111_drm_dev_private *priv =
0507         container_of(hw, struct pl111_drm_dev_private, clk_div);
0508     int div = pl111_clk_div_choose_div(hw, rate, &prate, false);
0509     u32 tim2;
0510
0511     spin_lock(&priv->tim2_lock);
0512     tim2 = readl(priv->regs + CLCD_TIM2);
0513     tim2 &= ~(TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK);
0514
0515     if (div == 1) {
0516         tim2 |= TIM2_BCD;
0517     } else {
0518         div -= 2;
0519         tim2 |= div & TIM2_PCD_LO_MASK;
0520         tim2 |= (div >> TIM2_PCD_LO_BITS) << TIM2_PCD_HI_SHIFT;
0521     }
0522
0523     writel(tim2, priv->regs + CLCD_TIM2);
0524     spin_unlock(&priv->tim2_lock);
0525
0526     return 0;
0527 }
0528
0529 static const struct clk_ops pl111_clk_div_ops = {
0530     .recalc_rate = pl111_clk_div_recalc_rate,
0531     .round_rate = pl111_clk_div_round_rate,
0532     .set_rate = pl111_clk_div_set_rate,
0533 };
0534
0535 static int
0536 pl111_init_clock_divider(struct drm_device *drm)
0537 {
0538     struct pl111_drm_dev_private *priv = drm->dev_private;
0539     struct clk *parent = devm_clk_get(drm->dev, "clcdclk");
0540     struct clk_hw *div = &priv->clk_div;
0541     const char *parent_name;
0542     struct clk_init_data init = {
0543         .name = "pl111_div",
0544         .ops = &pl111_clk_div_ops,
0545         .parent_names = &parent_name,
0546         .num_parents = 1,
0547         .flags = CLK_SET_RATE_PARENT,
0548     };
0549     int ret;
0550
0551     if (IS_ERR(parent)) {
0552         dev_err(drm->dev, "CLCD: unable to get clcdclk.\n");
0553         return PTR_ERR(parent);
0554     }
0555
0556     spin_lock_init(&priv->tim2_lock);
0557
0558     /* If the clock divider is broken, use the parent directly */
0559     if (priv->variant->broken_clockdivider) {
0560         priv->clk = parent;
0561         return 0;
0562     }
0563     parent_name = __clk_get_name(parent);
0564     div->init = &init;
0565
0566     ret = devm_clk_hw_register(drm->dev, div);
0567
0568     priv->clk = div->clk;
0569     return ret;
0570 }
0571
0572 int pl111_display_init(struct drm_device *drm)
0573 {
0574     struct pl111_drm_dev_private *priv = drm->dev_private;
0575     int ret;
0576
0577     ret = pl111_init_clock_divider(drm);
0578     if (ret)
0579         return ret;
0580
0581     if (!priv->variant->broken_vblank) {
0582         pl111_display_funcs.enable_vblank = pl111_display_enable_vblank;
0583         pl111_display_funcs.disable_vblank = pl111_display_disable_vblank;
0584     }
0585
0586     ret = drm_simple_display_pipe_init(drm, &priv->pipe,
0587                        &pl111_display_funcs,
0588                        priv->variant->formats,
0589                        priv->variant->nformats,
0590                        NULL,
0591                        priv->connector);
0592     if (ret)
0593         return ret;
0594
0595     return 0;
0596 }