drm/panfrost/panfrost_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
0003 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
0004 /*
0005  * Register definitions based on mali_midg_regmap.h
0006  * (C) COPYRIGHT 2010-2018 ARM Limited. All rights reserved.
0007  */
0008 #ifndef __PANFROST_REGS_H__
0009 #define __PANFROST_REGS_H__
0010
0011 #define GPU_ID              0x00
0012 #define GPU_L2_FEATURES         0x004   /* (RO) Level 2 cache features */
0013 #define GPU_CORE_FEATURES       0x008   /* (RO) Shader Core Features */
0014 #define GPU_TILER_FEATURES      0x00C   /* (RO) Tiler Features */
0015 #define GPU_MEM_FEATURES        0x010   /* (RO) Memory system features */
0016 #define   GROUPS_L2_COHERENT        BIT(0)  /* Cores groups are l2 coherent */
0017
0018 #define GPU_MMU_FEATURES        0x014   /* (RO) MMU features */
0019 #define GPU_AS_PRESENT          0x018   /* (RO) Address space slots present */
0020 #define GPU_JS_PRESENT          0x01C   /* (RO) Job slots present */
0021
0022 #define GPU_INT_RAWSTAT         0x20
0023 #define GPU_INT_CLEAR           0x24
0024 #define GPU_INT_MASK            0x28
0025 #define GPU_INT_STAT            0x2c
0026 #define   GPU_IRQ_FAULT         BIT(0)
0027 #define   GPU_IRQ_MULTIPLE_FAULT    BIT(7)
0028 #define   GPU_IRQ_RESET_COMPLETED   BIT(8)
0029 #define   GPU_IRQ_POWER_CHANGED     BIT(9)
0030 #define   GPU_IRQ_POWER_CHANGED_ALL BIT(10)
0031 #define   GPU_IRQ_PERFCNT_SAMPLE_COMPLETED BIT(16)
0032 #define   GPU_IRQ_CLEAN_CACHES_COMPLETED BIT(17)
0033 #define   GPU_IRQ_MASK_ALL           \
0034       (GPU_IRQ_FAULT            |\
0035        GPU_IRQ_MULTIPLE_FAULT       |\
0036        GPU_IRQ_RESET_COMPLETED      |\
0037        GPU_IRQ_POWER_CHANGED        |\
0038        GPU_IRQ_POWER_CHANGED_ALL        |\
0039        GPU_IRQ_PERFCNT_SAMPLE_COMPLETED |\
0040        GPU_IRQ_CLEAN_CACHES_COMPLETED)
0041 #define GPU_IRQ_MASK_ERROR          \
0042     (                   \
0043      GPU_IRQ_FAULT              |\
0044      GPU_IRQ_MULTIPLE_FAULT)
0045 #define GPU_CMD             0x30
0046 #define   GPU_CMD_SOFT_RESET        0x01
0047 #define   GPU_CMD_PERFCNT_CLEAR     0x03
0048 #define   GPU_CMD_PERFCNT_SAMPLE    0x04
0049 #define   GPU_CMD_CLEAN_CACHES      0x07
0050 #define   GPU_CMD_CLEAN_INV_CACHES  0x08
0051 #define GPU_STATUS          0x34
0052 #define   GPU_STATUS_PRFCNT_ACTIVE  BIT(2)
0053 #define GPU_LATEST_FLUSH_ID     0x38
0054 #define GPU_PWR_KEY         0x50    /* (WO) Power manager key register */
0055 #define  GPU_PWR_KEY_UNLOCK     0x2968A819
0056 #define GPU_PWR_OVERRIDE0       0x54    /* (RW) Power manager override settings */
0057 #define GPU_PWR_OVERRIDE1       0x58    /* (RW) Power manager override settings */
0058 #define GPU_FAULT_STATUS        0x3C
0059 #define GPU_FAULT_ADDRESS_LO        0x40
0060 #define GPU_FAULT_ADDRESS_HI        0x44
0061
0062 #define GPU_PERFCNT_BASE_LO     0x60
0063 #define GPU_PERFCNT_BASE_HI     0x64
0064 #define GPU_PERFCNT_CFG         0x68
0065 #define   GPU_PERFCNT_CFG_MODE(x)   (x)
0066 #define   GPU_PERFCNT_CFG_MODE_OFF  0
0067 #define   GPU_PERFCNT_CFG_MODE_MANUAL   1
0068 #define   GPU_PERFCNT_CFG_MODE_TILE 2
0069 #define   GPU_PERFCNT_CFG_AS(x)     ((x) << 4)
0070 #define   GPU_PERFCNT_CFG_SETSEL(x) ((x) << 8)
0071 #define GPU_PRFCNT_JM_EN        0x6c
0072 #define GPU_PRFCNT_SHADER_EN        0x70
0073 #define GPU_PRFCNT_TILER_EN     0x74
0074 #define GPU_PRFCNT_MMU_L2_EN        0x7c
0075
0076 #define GPU_THREAD_MAX_THREADS      0x0A0   /* (RO) Maximum number of threads per core */
0077 #define GPU_THREAD_MAX_WORKGROUP_SIZE   0x0A4   /* (RO) Maximum workgroup size */
0078 #define GPU_THREAD_MAX_BARRIER_SIZE 0x0A8   /* (RO) Maximum threads waiting at a barrier */
0079 #define GPU_THREAD_FEATURES     0x0AC   /* (RO) Thread features */
0080 #define GPU_THREAD_TLS_ALLOC        0x310   /* (RO) Number of threads per core that
0081                          * TLS must be allocated for */
0082
0083 #define GPU_TEXTURE_FEATURES(n)     (0x0B0 + ((n) * 4))
0084 #define GPU_JS_FEATURES(n)      (0x0C0 + ((n) * 4))
0085 #define GPU_AFBC_FEATURES       (0x4C)  /* (RO) AFBC support on Bifrost */
0086
0087 #define GPU_SHADER_PRESENT_LO       0x100   /* (RO) Shader core present bitmap, low word */
0088 #define GPU_SHADER_PRESENT_HI       0x104   /* (RO) Shader core present bitmap, high word */
0089 #define GPU_TILER_PRESENT_LO        0x110   /* (RO) Tiler core present bitmap, low word */
0090 #define GPU_TILER_PRESENT_HI        0x114   /* (RO) Tiler core present bitmap, high word */
0091
0092 #define GPU_L2_PRESENT_LO       0x120   /* (RO) Level 2 cache present bitmap, low word */
0093 #define GPU_L2_PRESENT_HI       0x124   /* (RO) Level 2 cache present bitmap, high word */
0094
0095 #define GPU_COHERENCY_FEATURES      0x300   /* (RO) Coherency features present */
0096 #define   COHERENCY_ACE_LITE        BIT(0)
0097 #define   COHERENCY_ACE         BIT(1)
0098
0099 #define GPU_STACK_PRESENT_LO        0xE00   /* (RO) Core stack present bitmap, low word */
0100 #define GPU_STACK_PRESENT_HI        0xE04   /* (RO) Core stack present bitmap, high word */
0101
0102 #define SHADER_READY_LO         0x140   /* (RO) Shader core ready bitmap, low word */
0103 #define SHADER_READY_HI         0x144   /* (RO) Shader core ready bitmap, high word */
0104
0105 #define TILER_READY_LO          0x150   /* (RO) Tiler core ready bitmap, low word */
0106 #define TILER_READY_HI          0x154   /* (RO) Tiler core ready bitmap, high word */
0107
0108 #define L2_READY_LO         0x160   /* (RO) Level 2 cache ready bitmap, low word */
0109 #define L2_READY_HI         0x164   /* (RO) Level 2 cache ready bitmap, high word */
0110
0111 #define STACK_READY_LO          0xE10   /* (RO) Core stack ready bitmap, low word */
0112 #define STACK_READY_HI          0xE14   /* (RO) Core stack ready bitmap, high word */
0113
0114
0115 #define SHADER_PWRON_LO         0x180   /* (WO) Shader core power on bitmap, low word */
0116 #define SHADER_PWRON_HI         0x184   /* (WO) Shader core power on bitmap, high word */
0117
0118 #define TILER_PWRON_LO          0x190   /* (WO) Tiler core power on bitmap, low word */
0119 #define TILER_PWRON_HI          0x194   /* (WO) Tiler core power on bitmap, high word */
0120
0121 #define L2_PWRON_LO         0x1A0   /* (WO) Level 2 cache power on bitmap, low word */
0122 #define L2_PWRON_HI         0x1A4   /* (WO) Level 2 cache power on bitmap, high word */
0123
0124 #define STACK_PWRON_LO          0xE20   /* (RO) Core stack power on bitmap, low word */
0125 #define STACK_PWRON_HI          0xE24   /* (RO) Core stack power on bitmap, high word */
0126
0127
0128 #define SHADER_PWROFF_LO        0x1C0   /* (WO) Shader core power off bitmap, low word */
0129 #define SHADER_PWROFF_HI        0x1C4   /* (WO) Shader core power off bitmap, high word */
0130
0131 #define TILER_PWROFF_LO         0x1D0   /* (WO) Tiler core power off bitmap, low word */
0132 #define TILER_PWROFF_HI         0x1D4   /* (WO) Tiler core power off bitmap, high word */
0133
0134 #define L2_PWROFF_LO            0x1E0   /* (WO) Level 2 cache power off bitmap, low word */
0135 #define L2_PWROFF_HI            0x1E4   /* (WO) Level 2 cache power off bitmap, high word */
0136
0137 #define STACK_PWROFF_LO         0xE30   /* (RO) Core stack power off bitmap, low word */
0138 #define STACK_PWROFF_HI         0xE34   /* (RO) Core stack power off bitmap, high word */
0139
0140
0141 #define SHADER_PWRTRANS_LO      0x200   /* (RO) Shader core power transition bitmap, low word */
0142 #define SHADER_PWRTRANS_HI      0x204   /* (RO) Shader core power transition bitmap, high word */
0143
0144 #define TILER_PWRTRANS_LO       0x210   /* (RO) Tiler core power transition bitmap, low word */
0145 #define TILER_PWRTRANS_HI       0x214   /* (RO) Tiler core power transition bitmap, high word */
0146
0147 #define L2_PWRTRANS_LO          0x220   /* (RO) Level 2 cache power transition bitmap, low word */
0148 #define L2_PWRTRANS_HI          0x224   /* (RO) Level 2 cache power transition bitmap, high word */
0149
0150 #define STACK_PWRTRANS_LO       0xE40   /* (RO) Core stack power transition bitmap, low word */
0151 #define STACK_PWRTRANS_HI       0xE44   /* (RO) Core stack power transition bitmap, high word */
0152
0153
0154 #define SHADER_PWRACTIVE_LO     0x240   /* (RO) Shader core active bitmap, low word */
0155 #define SHADER_PWRACTIVE_HI     0x244   /* (RO) Shader core active bitmap, high word */
0156
0157 #define TILER_PWRACTIVE_LO      0x250   /* (RO) Tiler core active bitmap, low word */
0158 #define TILER_PWRACTIVE_HI      0x254   /* (RO) Tiler core active bitmap, high word */
0159
0160 #define L2_PWRACTIVE_LO         0x260   /* (RO) Level 2 cache active bitmap, low word */
0161 #define L2_PWRACTIVE_HI         0x264   /* (RO) Level 2 cache active bitmap, high word */
0162
0163 #define GPU_JM_CONFIG           0xF00   /* (RW) Job Manager configuration register (Implementation specific register) */
0164 #define GPU_SHADER_CONFIG       0xF04   /* (RW) Shader core configuration settings (Implementation specific register) */
0165 #define GPU_TILER_CONFIG        0xF08   /* (RW) Tiler core configuration settings (Implementation specific register) */
0166 #define GPU_L2_MMU_CONFIG       0xF0C   /* (RW) Configuration of the L2 cache and MMU (Implementation specific register) */
0167
0168 /* L2_MMU_CONFIG register */
0169 #define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT   23
0170 #define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY     (0x1 << L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT)
0171 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT    24
0172 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS      (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
0173 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_OCTANT   (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
0174 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_QUARTER  (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
0175 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_HALF     (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
0176
0177 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT   26
0178 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES     (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
0179 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_OCTANT  (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
0180 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
0181 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_HALF    (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
0182
0183 #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS_SHIFT   12
0184 #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS     (0x7 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
0185
0186 #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES_SHIFT  15
0187 #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES    (0x7 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
0188
0189 /* SHADER_CONFIG register */
0190 #define SC_ALT_COUNTERS         BIT(3)
0191 #define SC_OVERRIDE_FWD_PIXEL_KILL  BIT(4)
0192 #define SC_SDC_DISABLE_OQ_DISCARD   BIT(6)
0193 #define SC_LS_ALLOW_ATTR_TYPES      BIT(16)
0194 #define SC_LS_PAUSEBUFFER_DISABLE   BIT(16)
0195 #define SC_TLS_HASH_ENABLE      BIT(17)
0196 #define SC_LS_ATTR_CHECK_DISABLE    BIT(18)
0197 #define SC_ENABLE_TEXGRD_FLAGS      BIT(25)
0198 #define SC_VAR_ALGORITHM        BIT(29)
0199 /* End SHADER_CONFIG register */
0200
0201 /* TILER_CONFIG register */
0202 #define TC_CLOCK_GATE_OVERRIDE      BIT(0)
0203
0204 /* JM_CONFIG register */
0205 #define JM_TIMESTAMP_OVERRIDE       BIT(0)
0206 #define JM_CLOCK_GATE_OVERRIDE      BIT(1)
0207 #define JM_JOB_THROTTLE_ENABLE      BIT(2)
0208 #define JM_JOB_THROTTLE_LIMIT_SHIFT 3
0209 #define JM_MAX_JOB_THROTTLE_LIMIT   0x3F
0210 #define JM_FORCE_COHERENCY_FEATURES_SHIFT 2
0211 #define JM_IDVS_GROUP_SIZE_SHIFT    16
0212 #define JM_DEFAULT_IDVS_GROUP_SIZE  0xF
0213 #define JM_MAX_IDVS_GROUP_SIZE      0x3F
0214
0215
0216 /* Job Control regs */
0217 #define JOB_INT_RAWSTAT         0x1000
0218 #define JOB_INT_CLEAR           0x1004
0219 #define JOB_INT_MASK            0x1008
0220 #define JOB_INT_STAT            0x100c
0221 #define JOB_INT_JS_STATE        0x1010
0222 #define JOB_INT_THROTTLE        0x1014
0223
0224 #define MK_JS_MASK(j)           (0x10001 << (j))
0225 #define JOB_INT_MASK_ERR(j)     BIT((j) + 16)
0226 #define JOB_INT_MASK_DONE(j)        BIT(j)
0227
0228 #define JS_BASE             0x1800
0229 #define JS_HEAD_LO(n)           (JS_BASE + ((n) * 0x80) + 0x00)
0230 #define JS_HEAD_HI(n)           (JS_BASE + ((n) * 0x80) + 0x04)
0231 #define JS_TAIL_LO(n)           (JS_BASE + ((n) * 0x80) + 0x08)
0232 #define JS_TAIL_HI(n)           (JS_BASE + ((n) * 0x80) + 0x0c)
0233 #define JS_AFFINITY_LO(n)       (JS_BASE + ((n) * 0x80) + 0x10)
0234 #define JS_AFFINITY_HI(n)       (JS_BASE + ((n) * 0x80) + 0x14)
0235 #define JS_CONFIG(n)            (JS_BASE + ((n) * 0x80) + 0x18)
0236 #define JS_XAFFINITY(n)         (JS_BASE + ((n) * 0x80) + 0x1c)
0237 #define JS_COMMAND(n)           (JS_BASE + ((n) * 0x80) + 0x20)
0238 #define JS_STATUS(n)            (JS_BASE + ((n) * 0x80) + 0x24)
0239 #define JS_HEAD_NEXT_LO(n)      (JS_BASE + ((n) * 0x80) + 0x40)
0240 #define JS_HEAD_NEXT_HI(n)      (JS_BASE + ((n) * 0x80) + 0x44)
0241 #define JS_AFFINITY_NEXT_LO(n)      (JS_BASE + ((n) * 0x80) + 0x50)
0242 #define JS_AFFINITY_NEXT_HI(n)      (JS_BASE + ((n) * 0x80) + 0x54)
0243 #define JS_CONFIG_NEXT(n)       (JS_BASE + ((n) * 0x80) + 0x58)
0244 #define JS_COMMAND_NEXT(n)      (JS_BASE + ((n) * 0x80) + 0x60)
0245 #define JS_FLUSH_ID_NEXT(n)     (JS_BASE + ((n) * 0x80) + 0x70)
0246
0247 /* Possible values of JS_CONFIG and JS_CONFIG_NEXT registers */
0248 #define JS_CONFIG_START_FLUSH_CLEAN     BIT(8)
0249 #define JS_CONFIG_START_FLUSH_CLEAN_INVALIDATE  (3u << 8)
0250 #define JS_CONFIG_START_MMU         BIT(10)
0251 #define JS_CONFIG_JOB_CHAIN_FLAG        BIT(11)
0252 #define JS_CONFIG_END_FLUSH_CLEAN       BIT(12)
0253 #define JS_CONFIG_END_FLUSH_CLEAN_INVALIDATE    (3u << 12)
0254 #define JS_CONFIG_ENABLE_FLUSH_REDUCTION    BIT(14)
0255 #define JS_CONFIG_DISABLE_DESCRIPTOR_WR_BK  BIT(15)
0256 #define JS_CONFIG_THREAD_PRI(n)         ((n) << 16)
0257
0258 #define JS_COMMAND_NOP          0x00
0259 #define JS_COMMAND_START        0x01
0260 #define JS_COMMAND_SOFT_STOP        0x02    /* Gently stop processing a job chain */
0261 #define JS_COMMAND_HARD_STOP        0x03    /* Rudely stop processing a job chain */
0262 #define JS_COMMAND_SOFT_STOP_0      0x04    /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 0 */
0263 #define JS_COMMAND_HARD_STOP_0      0x05    /* Execute HARD_STOP if JOB_CHAIN_FLAG is 0 */
0264 #define JS_COMMAND_SOFT_STOP_1      0x06    /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 1 */
0265 #define JS_COMMAND_HARD_STOP_1      0x07    /* Execute HARD_STOP if JOB_CHAIN_FLAG is 1 */
0266
0267 /* MMU regs */
0268 #define MMU_INT_RAWSTAT         0x2000
0269 #define MMU_INT_CLEAR           0x2004
0270 #define MMU_INT_MASK            0x2008
0271 #define MMU_INT_STAT            0x200c
0272
0273 /* AS_COMMAND register commands */
0274 #define AS_COMMAND_NOP          0x00    /* NOP Operation */
0275 #define AS_COMMAND_UPDATE       0x01    /* Broadcasts the values in AS_TRANSTAB and ASn_MEMATTR to all MMUs */
0276 #define AS_COMMAND_LOCK         0x02    /* Issue a lock region command to all MMUs */
0277 #define AS_COMMAND_UNLOCK       0x03    /* Issue a flush region command to all MMUs */
0278 #define AS_COMMAND_FLUSH        0x04    /* Flush all L2 caches then issue a flush region command to all MMUs
0279                            (deprecated - only for use with T60x) */
0280 #define AS_COMMAND_FLUSH_PT     0x04    /* Flush all L2 caches then issue a flush region command to all MMUs */
0281 #define AS_COMMAND_FLUSH_MEM        0x05    /* Wait for memory accesses to complete, flush all the L1s cache then
0282                            flush all L2 caches then issue a flush region command to all MMUs */
0283
0284 #define MMU_AS(as)          (0x2400 + ((as) << 6))
0285
0286 #define AS_TRANSTAB_LO(as)      (MMU_AS(as) + 0x00) /* (RW) Translation Table Base Address for address space n, low word */
0287 #define AS_TRANSTAB_HI(as)      (MMU_AS(as) + 0x04) /* (RW) Translation Table Base Address for address space n, high word */
0288 #define AS_MEMATTR_LO(as)       (MMU_AS(as) + 0x08) /* (RW) Memory attributes for address space n, low word. */
0289 #define AS_MEMATTR_HI(as)       (MMU_AS(as) + 0x0C) /* (RW) Memory attributes for address space n, high word. */
0290 #define AS_LOCKADDR_LO(as)      (MMU_AS(as) + 0x10) /* (RW) Lock region address for address space n, low word */
0291 #define AS_LOCKADDR_HI(as)      (MMU_AS(as) + 0x14) /* (RW) Lock region address for address space n, high word */
0292 #define AS_COMMAND(as)          (MMU_AS(as) + 0x18) /* (WO) MMU command register for address space n */
0293 #define AS_FAULTSTATUS(as)      (MMU_AS(as) + 0x1C) /* (RO) MMU fault status register for address space n */
0294 #define AS_FAULTADDRESS_LO(as)      (MMU_AS(as) + 0x20) /* (RO) Fault Address for address space n, low word */
0295 #define AS_FAULTADDRESS_HI(as)      (MMU_AS(as) + 0x24) /* (RO) Fault Address for address space n, high word */
0296 #define AS_STATUS(as)           (MMU_AS(as) + 0x28) /* (RO) Status flags for address space n */
0297 /* Additional Bifrost AS registers */
0298 #define AS_TRANSCFG_LO(as)      (MMU_AS(as) + 0x30) /* (RW) Translation table configuration for address space n, low word */
0299 #define AS_TRANSCFG_HI(as)      (MMU_AS(as) + 0x34) /* (RW) Translation table configuration for address space n, high word */
0300 #define AS_FAULTEXTRA_LO(as)        (MMU_AS(as) + 0x38) /* (RO) Secondary fault address for address space n, low word */
0301 #define AS_FAULTEXTRA_HI(as)        (MMU_AS(as) + 0x3C) /* (RO) Secondary fault address for address space n, high word */
0302
0303 /*
0304  * Begin LPAE MMU TRANSTAB register values
0305  */
0306 #define AS_TRANSTAB_LPAE_ADDR_SPACE_MASK    0xfffffffffffff000
0307 #define AS_TRANSTAB_LPAE_ADRMODE_IDENTITY   0x2
0308 #define AS_TRANSTAB_LPAE_ADRMODE_TABLE      0x3
0309 #define AS_TRANSTAB_LPAE_ADRMODE_MASK       0x3
0310 #define AS_TRANSTAB_LPAE_READ_INNER     BIT(2)
0311 #define AS_TRANSTAB_LPAE_SHARE_OUTER        BIT(4)
0312
0313 #define AS_STATUS_AS_ACTIVE         0x01
0314
0315 #define AS_FAULTSTATUS_ACCESS_TYPE_MASK     (0x3 << 8)
0316 #define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC   (0x0 << 8)
0317 #define AS_FAULTSTATUS_ACCESS_TYPE_EX       (0x1 << 8)
0318 #define AS_FAULTSTATUS_ACCESS_TYPE_READ     (0x2 << 8)
0319 #define AS_FAULTSTATUS_ACCESS_TYPE_WRITE    (0x3 << 8)
0320
0321 #define AS_LOCK_REGION_MIN_SIZE                 (1ULL << 15)
0322
0323 #define gpu_write(dev, reg, data) writel(data, dev->iomem + reg)
0324 #define gpu_read(dev, reg) readl(dev->iomem + reg)
0325
0326 #endif