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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
0003 
0004 #include <drm/panfrost_drm.h>
0005 
0006 #include <linux/atomic.h>
0007 #include <linux/bitfield.h>
0008 #include <linux/delay.h>
0009 #include <linux/dma-mapping.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/io.h>
0012 #include <linux/iopoll.h>
0013 #include <linux/io-pgtable.h>
0014 #include <linux/iommu.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/shmem_fs.h>
0018 #include <linux/sizes.h>
0019 
0020 #include "panfrost_device.h"
0021 #include "panfrost_mmu.h"
0022 #include "panfrost_gem.h"
0023 #include "panfrost_features.h"
0024 #include "panfrost_regs.h"
0025 
0026 #define mmu_write(dev, reg, data) writel(data, dev->iomem + reg)
0027 #define mmu_read(dev, reg) readl(dev->iomem + reg)
0028 
0029 static int wait_ready(struct panfrost_device *pfdev, u32 as_nr)
0030 {
0031     int ret;
0032     u32 val;
0033 
0034     /* Wait for the MMU status to indicate there is no active command, in
0035      * case one is pending. */
0036     ret = readl_relaxed_poll_timeout_atomic(pfdev->iomem + AS_STATUS(as_nr),
0037         val, !(val & AS_STATUS_AS_ACTIVE), 10, 100000);
0038 
0039     if (ret) {
0040         /* The GPU hung, let's trigger a reset */
0041         panfrost_device_schedule_reset(pfdev);
0042         dev_err(pfdev->dev, "AS_ACTIVE bit stuck\n");
0043     }
0044 
0045     return ret;
0046 }
0047 
0048 static int write_cmd(struct panfrost_device *pfdev, u32 as_nr, u32 cmd)
0049 {
0050     int status;
0051 
0052     /* write AS_COMMAND when MMU is ready to accept another command */
0053     status = wait_ready(pfdev, as_nr);
0054     if (!status)
0055         mmu_write(pfdev, AS_COMMAND(as_nr), cmd);
0056 
0057     return status;
0058 }
0059 
0060 static void lock_region(struct panfrost_device *pfdev, u32 as_nr,
0061             u64 region_start, u64 size)
0062 {
0063     u8 region_width;
0064     u64 region;
0065     u64 region_end = region_start + size;
0066 
0067     if (!size)
0068         return;
0069 
0070     /*
0071      * The locked region is a naturally aligned power of 2 block encoded as
0072      * log2 minus(1).
0073      * Calculate the desired start/end and look for the highest bit which
0074      * differs. The smallest naturally aligned block must include this bit
0075      * change, the desired region starts with this bit (and subsequent bits)
0076      * zeroed and ends with the bit (and subsequent bits) set to one.
0077      */
0078     region_width = max(fls64(region_start ^ (region_end - 1)),
0079                const_ilog2(AS_LOCK_REGION_MIN_SIZE)) - 1;
0080 
0081     /*
0082      * Mask off the low bits of region_start (which would be ignored by
0083      * the hardware anyway)
0084      */
0085     region_start &= GENMASK_ULL(63, region_width);
0086 
0087     region = region_width | region_start;
0088 
0089     /* Lock the region that needs to be updated */
0090     mmu_write(pfdev, AS_LOCKADDR_LO(as_nr), lower_32_bits(region));
0091     mmu_write(pfdev, AS_LOCKADDR_HI(as_nr), upper_32_bits(region));
0092     write_cmd(pfdev, as_nr, AS_COMMAND_LOCK);
0093 }
0094 
0095 
0096 static int mmu_hw_do_operation_locked(struct panfrost_device *pfdev, int as_nr,
0097                       u64 iova, u64 size, u32 op)
0098 {
0099     if (as_nr < 0)
0100         return 0;
0101 
0102     if (op != AS_COMMAND_UNLOCK)
0103         lock_region(pfdev, as_nr, iova, size);
0104 
0105     /* Run the MMU operation */
0106     write_cmd(pfdev, as_nr, op);
0107 
0108     /* Wait for the flush to complete */
0109     return wait_ready(pfdev, as_nr);
0110 }
0111 
0112 static int mmu_hw_do_operation(struct panfrost_device *pfdev,
0113                    struct panfrost_mmu *mmu,
0114                    u64 iova, u64 size, u32 op)
0115 {
0116     int ret;
0117 
0118     spin_lock(&pfdev->as_lock);
0119     ret = mmu_hw_do_operation_locked(pfdev, mmu->as, iova, size, op);
0120     spin_unlock(&pfdev->as_lock);
0121     return ret;
0122 }
0123 
0124 static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
0125 {
0126     int as_nr = mmu->as;
0127     struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg;
0128     u64 transtab = cfg->arm_mali_lpae_cfg.transtab;
0129     u64 memattr = cfg->arm_mali_lpae_cfg.memattr;
0130 
0131     mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
0132 
0133     mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), lower_32_bits(transtab));
0134     mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), upper_32_bits(transtab));
0135 
0136     /* Need to revisit mem attrs.
0137      * NC is the default, Mali driver is inner WT.
0138      */
0139     mmu_write(pfdev, AS_MEMATTR_LO(as_nr), lower_32_bits(memattr));
0140     mmu_write(pfdev, AS_MEMATTR_HI(as_nr), upper_32_bits(memattr));
0141 
0142     write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE);
0143 }
0144 
0145 static void panfrost_mmu_disable(struct panfrost_device *pfdev, u32 as_nr)
0146 {
0147     mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
0148 
0149     mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), 0);
0150     mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), 0);
0151 
0152     mmu_write(pfdev, AS_MEMATTR_LO(as_nr), 0);
0153     mmu_write(pfdev, AS_MEMATTR_HI(as_nr), 0);
0154 
0155     write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE);
0156 }
0157 
0158 u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
0159 {
0160     int as;
0161 
0162     spin_lock(&pfdev->as_lock);
0163 
0164     as = mmu->as;
0165     if (as >= 0) {
0166         int en = atomic_inc_return(&mmu->as_count);
0167         u32 mask = BIT(as) | BIT(16 + as);
0168 
0169         /*
0170          * AS can be retained by active jobs or a perfcnt context,
0171          * hence the '+ 1' here.
0172          */
0173         WARN_ON(en >= (NUM_JOB_SLOTS + 1));
0174 
0175         list_move(&mmu->list, &pfdev->as_lru_list);
0176 
0177         if (pfdev->as_faulty_mask & mask) {
0178             /* Unhandled pagefault on this AS, the MMU was
0179              * disabled. We need to re-enable the MMU after
0180              * clearing+unmasking the AS interrupts.
0181              */
0182             mmu_write(pfdev, MMU_INT_CLEAR, mask);
0183             mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask);
0184             pfdev->as_faulty_mask &= ~mask;
0185             panfrost_mmu_enable(pfdev, mmu);
0186         }
0187 
0188         goto out;
0189     }
0190 
0191     /* Check for a free AS */
0192     as = ffz(pfdev->as_alloc_mask);
0193     if (!(BIT(as) & pfdev->features.as_present)) {
0194         struct panfrost_mmu *lru_mmu;
0195 
0196         list_for_each_entry_reverse(lru_mmu, &pfdev->as_lru_list, list) {
0197             if (!atomic_read(&lru_mmu->as_count))
0198                 break;
0199         }
0200         WARN_ON(&lru_mmu->list == &pfdev->as_lru_list);
0201 
0202         list_del_init(&lru_mmu->list);
0203         as = lru_mmu->as;
0204 
0205         WARN_ON(as < 0);
0206         lru_mmu->as = -1;
0207     }
0208 
0209     /* Assign the free or reclaimed AS to the FD */
0210     mmu->as = as;
0211     set_bit(as, &pfdev->as_alloc_mask);
0212     atomic_set(&mmu->as_count, 1);
0213     list_add(&mmu->list, &pfdev->as_lru_list);
0214 
0215     dev_dbg(pfdev->dev, "Assigned AS%d to mmu %p, alloc_mask=%lx", as, mmu, pfdev->as_alloc_mask);
0216 
0217     panfrost_mmu_enable(pfdev, mmu);
0218 
0219 out:
0220     spin_unlock(&pfdev->as_lock);
0221     return as;
0222 }
0223 
0224 void panfrost_mmu_as_put(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
0225 {
0226     atomic_dec(&mmu->as_count);
0227     WARN_ON(atomic_read(&mmu->as_count) < 0);
0228 }
0229 
0230 void panfrost_mmu_reset(struct panfrost_device *pfdev)
0231 {
0232     struct panfrost_mmu *mmu, *mmu_tmp;
0233 
0234     spin_lock(&pfdev->as_lock);
0235 
0236     pfdev->as_alloc_mask = 0;
0237     pfdev->as_faulty_mask = 0;
0238 
0239     list_for_each_entry_safe(mmu, mmu_tmp, &pfdev->as_lru_list, list) {
0240         mmu->as = -1;
0241         atomic_set(&mmu->as_count, 0);
0242         list_del_init(&mmu->list);
0243     }
0244 
0245     spin_unlock(&pfdev->as_lock);
0246 
0247     mmu_write(pfdev, MMU_INT_CLEAR, ~0);
0248     mmu_write(pfdev, MMU_INT_MASK, ~0);
0249 }
0250 
0251 static size_t get_pgsize(u64 addr, size_t size)
0252 {
0253     if (addr & (SZ_2M - 1) || size < SZ_2M)
0254         return SZ_4K;
0255 
0256     return SZ_2M;
0257 }
0258 
0259 static void panfrost_mmu_flush_range(struct panfrost_device *pfdev,
0260                      struct panfrost_mmu *mmu,
0261                      u64 iova, u64 size)
0262 {
0263     if (mmu->as < 0)
0264         return;
0265 
0266     pm_runtime_get_noresume(pfdev->dev);
0267 
0268     /* Flush the PTs only if we're already awake */
0269     if (pm_runtime_active(pfdev->dev))
0270         mmu_hw_do_operation(pfdev, mmu, iova, size, AS_COMMAND_FLUSH_PT);
0271 
0272     pm_runtime_put_sync_autosuspend(pfdev->dev);
0273 }
0274 
0275 static int mmu_map_sg(struct panfrost_device *pfdev, struct panfrost_mmu *mmu,
0276               u64 iova, int prot, struct sg_table *sgt)
0277 {
0278     unsigned int count;
0279     struct scatterlist *sgl;
0280     struct io_pgtable_ops *ops = mmu->pgtbl_ops;
0281     u64 start_iova = iova;
0282 
0283     for_each_sgtable_dma_sg(sgt, sgl, count) {
0284         unsigned long paddr = sg_dma_address(sgl);
0285         size_t len = sg_dma_len(sgl);
0286 
0287         dev_dbg(pfdev->dev, "map: as=%d, iova=%llx, paddr=%lx, len=%zx", mmu->as, iova, paddr, len);
0288 
0289         while (len) {
0290             size_t pgsize = get_pgsize(iova | paddr, len);
0291 
0292             ops->map(ops, iova, paddr, pgsize, prot, GFP_KERNEL);
0293             iova += pgsize;
0294             paddr += pgsize;
0295             len -= pgsize;
0296         }
0297     }
0298 
0299     panfrost_mmu_flush_range(pfdev, mmu, start_iova, iova - start_iova);
0300 
0301     return 0;
0302 }
0303 
0304 int panfrost_mmu_map(struct panfrost_gem_mapping *mapping)
0305 {
0306     struct panfrost_gem_object *bo = mapping->obj;
0307     struct drm_gem_shmem_object *shmem = &bo->base;
0308     struct drm_gem_object *obj = &shmem->base;
0309     struct panfrost_device *pfdev = to_panfrost_device(obj->dev);
0310     struct sg_table *sgt;
0311     int prot = IOMMU_READ | IOMMU_WRITE;
0312 
0313     if (WARN_ON(mapping->active))
0314         return 0;
0315 
0316     if (bo->noexec)
0317         prot |= IOMMU_NOEXEC;
0318 
0319     sgt = drm_gem_shmem_get_pages_sgt(shmem);
0320     if (WARN_ON(IS_ERR(sgt)))
0321         return PTR_ERR(sgt);
0322 
0323     mmu_map_sg(pfdev, mapping->mmu, mapping->mmnode.start << PAGE_SHIFT,
0324            prot, sgt);
0325     mapping->active = true;
0326 
0327     return 0;
0328 }
0329 
0330 void panfrost_mmu_unmap(struct panfrost_gem_mapping *mapping)
0331 {
0332     struct panfrost_gem_object *bo = mapping->obj;
0333     struct drm_gem_object *obj = &bo->base.base;
0334     struct panfrost_device *pfdev = to_panfrost_device(obj->dev);
0335     struct io_pgtable_ops *ops = mapping->mmu->pgtbl_ops;
0336     u64 iova = mapping->mmnode.start << PAGE_SHIFT;
0337     size_t len = mapping->mmnode.size << PAGE_SHIFT;
0338     size_t unmapped_len = 0;
0339 
0340     if (WARN_ON(!mapping->active))
0341         return;
0342 
0343     dev_dbg(pfdev->dev, "unmap: as=%d, iova=%llx, len=%zx",
0344         mapping->mmu->as, iova, len);
0345 
0346     while (unmapped_len < len) {
0347         size_t unmapped_page;
0348         size_t pgsize = get_pgsize(iova, len - unmapped_len);
0349 
0350         if (ops->iova_to_phys(ops, iova)) {
0351             unmapped_page = ops->unmap(ops, iova, pgsize, NULL);
0352             WARN_ON(unmapped_page != pgsize);
0353         }
0354         iova += pgsize;
0355         unmapped_len += pgsize;
0356     }
0357 
0358     panfrost_mmu_flush_range(pfdev, mapping->mmu,
0359                  mapping->mmnode.start << PAGE_SHIFT, len);
0360     mapping->active = false;
0361 }
0362 
0363 static void mmu_tlb_inv_context_s1(void *cookie)
0364 {}
0365 
0366 static void mmu_tlb_sync_context(void *cookie)
0367 {
0368     //struct panfrost_mmu *mmu = cookie;
0369     // TODO: Wait 1000 GPU cycles for HW_ISSUE_6367/T60X
0370 }
0371 
0372 static void mmu_tlb_flush_walk(unsigned long iova, size_t size, size_t granule,
0373                    void *cookie)
0374 {
0375     mmu_tlb_sync_context(cookie);
0376 }
0377 
0378 static const struct iommu_flush_ops mmu_tlb_ops = {
0379     .tlb_flush_all  = mmu_tlb_inv_context_s1,
0380     .tlb_flush_walk = mmu_tlb_flush_walk,
0381 };
0382 
0383 static struct panfrost_gem_mapping *
0384 addr_to_mapping(struct panfrost_device *pfdev, int as, u64 addr)
0385 {
0386     struct panfrost_gem_mapping *mapping = NULL;
0387     struct drm_mm_node *node;
0388     u64 offset = addr >> PAGE_SHIFT;
0389     struct panfrost_mmu *mmu;
0390 
0391     spin_lock(&pfdev->as_lock);
0392     list_for_each_entry(mmu, &pfdev->as_lru_list, list) {
0393         if (as == mmu->as)
0394             goto found_mmu;
0395     }
0396     goto out;
0397 
0398 found_mmu:
0399 
0400     spin_lock(&mmu->mm_lock);
0401 
0402     drm_mm_for_each_node(node, &mmu->mm) {
0403         if (offset >= node->start &&
0404             offset < (node->start + node->size)) {
0405             mapping = drm_mm_node_to_panfrost_mapping(node);
0406 
0407             kref_get(&mapping->refcount);
0408             break;
0409         }
0410     }
0411 
0412     spin_unlock(&mmu->mm_lock);
0413 out:
0414     spin_unlock(&pfdev->as_lock);
0415     return mapping;
0416 }
0417 
0418 #define NUM_FAULT_PAGES (SZ_2M / PAGE_SIZE)
0419 
0420 static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as,
0421                        u64 addr)
0422 {
0423     int ret, i;
0424     struct panfrost_gem_mapping *bomapping;
0425     struct panfrost_gem_object *bo;
0426     struct address_space *mapping;
0427     pgoff_t page_offset;
0428     struct sg_table *sgt;
0429     struct page **pages;
0430 
0431     bomapping = addr_to_mapping(pfdev, as, addr);
0432     if (!bomapping)
0433         return -ENOENT;
0434 
0435     bo = bomapping->obj;
0436     if (!bo->is_heap) {
0437         dev_WARN(pfdev->dev, "matching BO is not heap type (GPU VA = %llx)",
0438              bomapping->mmnode.start << PAGE_SHIFT);
0439         ret = -EINVAL;
0440         goto err_bo;
0441     }
0442     WARN_ON(bomapping->mmu->as != as);
0443 
0444     /* Assume 2MB alignment and size multiple */
0445     addr &= ~((u64)SZ_2M - 1);
0446     page_offset = addr >> PAGE_SHIFT;
0447     page_offset -= bomapping->mmnode.start;
0448 
0449     mutex_lock(&bo->base.pages_lock);
0450 
0451     if (!bo->base.pages) {
0452         bo->sgts = kvmalloc_array(bo->base.base.size / SZ_2M,
0453                      sizeof(struct sg_table), GFP_KERNEL | __GFP_ZERO);
0454         if (!bo->sgts) {
0455             mutex_unlock(&bo->base.pages_lock);
0456             ret = -ENOMEM;
0457             goto err_bo;
0458         }
0459 
0460         pages = kvmalloc_array(bo->base.base.size >> PAGE_SHIFT,
0461                        sizeof(struct page *), GFP_KERNEL | __GFP_ZERO);
0462         if (!pages) {
0463             kvfree(bo->sgts);
0464             bo->sgts = NULL;
0465             mutex_unlock(&bo->base.pages_lock);
0466             ret = -ENOMEM;
0467             goto err_bo;
0468         }
0469         bo->base.pages = pages;
0470         bo->base.pages_use_count = 1;
0471     } else {
0472         pages = bo->base.pages;
0473         if (pages[page_offset]) {
0474             /* Pages are already mapped, bail out. */
0475             mutex_unlock(&bo->base.pages_lock);
0476             goto out;
0477         }
0478     }
0479 
0480     mapping = bo->base.base.filp->f_mapping;
0481     mapping_set_unevictable(mapping);
0482 
0483     for (i = page_offset; i < page_offset + NUM_FAULT_PAGES; i++) {
0484         pages[i] = shmem_read_mapping_page(mapping, i);
0485         if (IS_ERR(pages[i])) {
0486             mutex_unlock(&bo->base.pages_lock);
0487             ret = PTR_ERR(pages[i]);
0488             goto err_pages;
0489         }
0490     }
0491 
0492     mutex_unlock(&bo->base.pages_lock);
0493 
0494     sgt = &bo->sgts[page_offset / (SZ_2M / PAGE_SIZE)];
0495     ret = sg_alloc_table_from_pages(sgt, pages + page_offset,
0496                     NUM_FAULT_PAGES, 0, SZ_2M, GFP_KERNEL);
0497     if (ret)
0498         goto err_pages;
0499 
0500     ret = dma_map_sgtable(pfdev->dev, sgt, DMA_BIDIRECTIONAL, 0);
0501     if (ret)
0502         goto err_map;
0503 
0504     mmu_map_sg(pfdev, bomapping->mmu, addr,
0505            IOMMU_WRITE | IOMMU_READ | IOMMU_NOEXEC, sgt);
0506 
0507     bomapping->active = true;
0508 
0509     dev_dbg(pfdev->dev, "mapped page fault @ AS%d %llx", as, addr);
0510 
0511 out:
0512     panfrost_gem_mapping_put(bomapping);
0513 
0514     return 0;
0515 
0516 err_map:
0517     sg_free_table(sgt);
0518 err_pages:
0519     drm_gem_shmem_put_pages(&bo->base);
0520 err_bo:
0521     panfrost_gem_mapping_put(bomapping);
0522     return ret;
0523 }
0524 
0525 static void panfrost_mmu_release_ctx(struct kref *kref)
0526 {
0527     struct panfrost_mmu *mmu = container_of(kref, struct panfrost_mmu,
0528                         refcount);
0529     struct panfrost_device *pfdev = mmu->pfdev;
0530 
0531     spin_lock(&pfdev->as_lock);
0532     if (mmu->as >= 0) {
0533         pm_runtime_get_noresume(pfdev->dev);
0534         if (pm_runtime_active(pfdev->dev))
0535             panfrost_mmu_disable(pfdev, mmu->as);
0536         pm_runtime_put_autosuspend(pfdev->dev);
0537 
0538         clear_bit(mmu->as, &pfdev->as_alloc_mask);
0539         clear_bit(mmu->as, &pfdev->as_in_use_mask);
0540         list_del(&mmu->list);
0541     }
0542     spin_unlock(&pfdev->as_lock);
0543 
0544     free_io_pgtable_ops(mmu->pgtbl_ops);
0545     drm_mm_takedown(&mmu->mm);
0546     kfree(mmu);
0547 }
0548 
0549 void panfrost_mmu_ctx_put(struct panfrost_mmu *mmu)
0550 {
0551     kref_put(&mmu->refcount, panfrost_mmu_release_ctx);
0552 }
0553 
0554 struct panfrost_mmu *panfrost_mmu_ctx_get(struct panfrost_mmu *mmu)
0555 {
0556     kref_get(&mmu->refcount);
0557 
0558     return mmu;
0559 }
0560 
0561 #define PFN_4G      (SZ_4G >> PAGE_SHIFT)
0562 #define PFN_4G_MASK (PFN_4G - 1)
0563 #define PFN_16M     (SZ_16M >> PAGE_SHIFT)
0564 
0565 static void panfrost_drm_mm_color_adjust(const struct drm_mm_node *node,
0566                      unsigned long color,
0567                      u64 *start, u64 *end)
0568 {
0569     /* Executable buffers can't start or end on a 4GB boundary */
0570     if (!(color & PANFROST_BO_NOEXEC)) {
0571         u64 next_seg;
0572 
0573         if ((*start & PFN_4G_MASK) == 0)
0574             (*start)++;
0575 
0576         if ((*end & PFN_4G_MASK) == 0)
0577             (*end)--;
0578 
0579         next_seg = ALIGN(*start, PFN_4G);
0580         if (next_seg - *start <= PFN_16M)
0581             *start = next_seg + 1;
0582 
0583         *end = min(*end, ALIGN(*start, PFN_4G) - 1);
0584     }
0585 }
0586 
0587 struct panfrost_mmu *panfrost_mmu_ctx_create(struct panfrost_device *pfdev)
0588 {
0589     struct panfrost_mmu *mmu;
0590 
0591     mmu = kzalloc(sizeof(*mmu), GFP_KERNEL);
0592     if (!mmu)
0593         return ERR_PTR(-ENOMEM);
0594 
0595     mmu->pfdev = pfdev;
0596     spin_lock_init(&mmu->mm_lock);
0597 
0598     /* 4G enough for now. can be 48-bit */
0599     drm_mm_init(&mmu->mm, SZ_32M >> PAGE_SHIFT, (SZ_4G - SZ_32M) >> PAGE_SHIFT);
0600     mmu->mm.color_adjust = panfrost_drm_mm_color_adjust;
0601 
0602     INIT_LIST_HEAD(&mmu->list);
0603     mmu->as = -1;
0604 
0605     mmu->pgtbl_cfg = (struct io_pgtable_cfg) {
0606         .pgsize_bitmap  = SZ_4K | SZ_2M,
0607         .ias        = FIELD_GET(0xff, pfdev->features.mmu_features),
0608         .oas        = FIELD_GET(0xff00, pfdev->features.mmu_features),
0609         .coherent_walk  = pfdev->coherent,
0610         .tlb        = &mmu_tlb_ops,
0611         .iommu_dev  = pfdev->dev,
0612     };
0613 
0614     mmu->pgtbl_ops = alloc_io_pgtable_ops(ARM_MALI_LPAE, &mmu->pgtbl_cfg,
0615                           mmu);
0616     if (!mmu->pgtbl_ops) {
0617         kfree(mmu);
0618         return ERR_PTR(-EINVAL);
0619     }
0620 
0621     kref_init(&mmu->refcount);
0622 
0623     return mmu;
0624 }
0625 
0626 static const char *access_type_name(struct panfrost_device *pfdev,
0627         u32 fault_status)
0628 {
0629     switch (fault_status & AS_FAULTSTATUS_ACCESS_TYPE_MASK) {
0630     case AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC:
0631         if (panfrost_has_hw_feature(pfdev, HW_FEATURE_AARCH64_MMU))
0632             return "ATOMIC";
0633         else
0634             return "UNKNOWN";
0635     case AS_FAULTSTATUS_ACCESS_TYPE_READ:
0636         return "READ";
0637     case AS_FAULTSTATUS_ACCESS_TYPE_WRITE:
0638         return "WRITE";
0639     case AS_FAULTSTATUS_ACCESS_TYPE_EX:
0640         return "EXECUTE";
0641     default:
0642         WARN_ON(1);
0643         return NULL;
0644     }
0645 }
0646 
0647 static irqreturn_t panfrost_mmu_irq_handler(int irq, void *data)
0648 {
0649     struct panfrost_device *pfdev = data;
0650 
0651     if (!mmu_read(pfdev, MMU_INT_STAT))
0652         return IRQ_NONE;
0653 
0654     mmu_write(pfdev, MMU_INT_MASK, 0);
0655     return IRQ_WAKE_THREAD;
0656 }
0657 
0658 static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data)
0659 {
0660     struct panfrost_device *pfdev = data;
0661     u32 status = mmu_read(pfdev, MMU_INT_RAWSTAT);
0662     int ret;
0663 
0664     while (status) {
0665         u32 as = ffs(status | (status >> 16)) - 1;
0666         u32 mask = BIT(as) | BIT(as + 16);
0667         u64 addr;
0668         u32 fault_status;
0669         u32 exception_type;
0670         u32 access_type;
0671         u32 source_id;
0672 
0673         fault_status = mmu_read(pfdev, AS_FAULTSTATUS(as));
0674         addr = mmu_read(pfdev, AS_FAULTADDRESS_LO(as));
0675         addr |= (u64)mmu_read(pfdev, AS_FAULTADDRESS_HI(as)) << 32;
0676 
0677         /* decode the fault status */
0678         exception_type = fault_status & 0xFF;
0679         access_type = (fault_status >> 8) & 0x3;
0680         source_id = (fault_status >> 16);
0681 
0682         mmu_write(pfdev, MMU_INT_CLEAR, mask);
0683 
0684         /* Page fault only */
0685         ret = -1;
0686         if ((status & mask) == BIT(as) && (exception_type & 0xF8) == 0xC0)
0687             ret = panfrost_mmu_map_fault_addr(pfdev, as, addr);
0688 
0689         if (ret) {
0690             /* terminal fault, print info about the fault */
0691             dev_err(pfdev->dev,
0692                 "Unhandled Page fault in AS%d at VA 0x%016llX\n"
0693                 "Reason: %s\n"
0694                 "raw fault status: 0x%X\n"
0695                 "decoded fault status: %s\n"
0696                 "exception type 0x%X: %s\n"
0697                 "access type 0x%X: %s\n"
0698                 "source id 0x%X\n",
0699                 as, addr,
0700                 "TODO",
0701                 fault_status,
0702                 (fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"),
0703                 exception_type, panfrost_exception_name(exception_type),
0704                 access_type, access_type_name(pfdev, fault_status),
0705                 source_id);
0706 
0707             spin_lock(&pfdev->as_lock);
0708             /* Ignore MMU interrupts on this AS until it's been
0709              * re-enabled.
0710              */
0711             pfdev->as_faulty_mask |= mask;
0712 
0713             /* Disable the MMU to kill jobs on this AS. */
0714             panfrost_mmu_disable(pfdev, as);
0715             spin_unlock(&pfdev->as_lock);
0716         }
0717 
0718         status &= ~mask;
0719 
0720         /* If we received new MMU interrupts, process them before returning. */
0721         if (!status)
0722             status = mmu_read(pfdev, MMU_INT_RAWSTAT) & ~pfdev->as_faulty_mask;
0723     }
0724 
0725     spin_lock(&pfdev->as_lock);
0726     mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask);
0727     spin_unlock(&pfdev->as_lock);
0728 
0729     return IRQ_HANDLED;
0730 };
0731 
0732 int panfrost_mmu_init(struct panfrost_device *pfdev)
0733 {
0734     int err, irq;
0735 
0736     irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "mmu");
0737     if (irq <= 0)
0738         return -ENODEV;
0739 
0740     err = devm_request_threaded_irq(pfdev->dev, irq,
0741                     panfrost_mmu_irq_handler,
0742                     panfrost_mmu_irq_handler_thread,
0743                     IRQF_SHARED, KBUILD_MODNAME "-mmu",
0744                     pfdev);
0745 
0746     if (err) {
0747         dev_err(pfdev->dev, "failed to request mmu irq");
0748         return err;
0749     }
0750 
0751     return 0;
0752 }
0753 
0754 void panfrost_mmu_fini(struct panfrost_device *pfdev)
0755 {
0756     mmu_write(pfdev, MMU_INT_MASK, 0);
0757 }
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