drm/panfrost/panfrost_issues.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. */
0003 /* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */
0004 #ifndef __PANFROST_ISSUES_H__
0005 #define __PANFROST_ISSUES_H__
0006
0007 #include <linux/bitops.h>
0008
0009 #include "panfrost_device.h"
0010
0011 /*
0012  * This is not a complete list of issues, but only the ones the driver needs
0013  * to care about.
0014  */
0015 enum panfrost_hw_issue {
0016     /* Need way to guarantee that all previously-translated memory accesses
0017      * are committed */
0018     HW_ISSUE_6367,
0019
0020     /* On job complete with non-done the cache is not flushed */
0021     HW_ISSUE_6787,
0022
0023     /* Write of PRFCNT_CONFIG_MODE_MANUAL to PRFCNT_CONFIG causes a
0024      * instrumentation dump if PRFCNT_TILER_EN is enabled */
0025     HW_ISSUE_8186,
0026
0027     /* TIB: Reports faults from a vtile which has not yet been allocated */
0028     HW_ISSUE_8245,
0029
0030     /* uTLB deadlock could occur when writing to an invalid page at the
0031      * same time as access to a valid page in the same uTLB cache line ( ==
0032      * 4 PTEs == 16K block of mapping) */
0033     HW_ISSUE_8316,
0034
0035     /* HT: TERMINATE for RUN command ignored if previous LOAD_DESCRIPTOR is
0036      * still executing */
0037     HW_ISSUE_8394,
0038
0039     /* CSE: Sends a TERMINATED response for a task that should not be
0040      * terminated */
0041     HW_ISSUE_8401,
0042
0043     /* Repeatedly Soft-stopping a job chain consisting of (Vertex Shader,
0044      * Cache Flush, Tiler) jobs causes DATA_INVALID_FAULT on tiler job. */
0045     HW_ISSUE_8408,
0046
0047     /* Disable the Pause Buffer in the LS pipe. */
0048     HW_ISSUE_8443,
0049
0050     /* Change in RMUs in use causes problems related with the core's SDC */
0051     HW_ISSUE_8987,
0052
0053     /* Compute endpoint has a 4-deep queue of tasks, meaning a soft stop
0054      * won't complete until all 4 tasks have completed */
0055     HW_ISSUE_9435,
0056
0057     /* HT: Tiler returns TERMINATED for non-terminated command */
0058     HW_ISSUE_9510,
0059
0060     /* Occasionally the GPU will issue multiple page faults for the same
0061      * address before the MMU page table has been read by the GPU */
0062     HW_ISSUE_9630,
0063
0064     /* RA DCD load request to SDC returns invalid load ignore causing
0065      * colour buffer mismatch */
0066     HW_ISSUE_10327,
0067
0068     /* MMU TLB invalidation hazards */
0069     HW_ISSUE_10649,
0070
0071     /* Missing cache flush in multi core-group configuration */
0072     HW_ISSUE_10676,
0073
0074     /* Chicken bit on T72X for a hardware workaround in compiler */
0075     HW_ISSUE_10797,
0076
0077     /* Soft-stopping fragment jobs might fail with TILE_RANGE_FAULT */
0078     HW_ISSUE_10817,
0079
0080     /* Intermittent missing interrupt on job completion */
0081     HW_ISSUE_10883,
0082
0083     /* Soft-stopping fragment jobs might fail with TILE_RANGE_ERROR
0084      * (similar to issue 10817) and can use #10817 workaround */
0085     HW_ISSUE_10959,
0086
0087     /* Soft-stopped fragment shader job can restart with out-of-bound
0088      * restart index */
0089     HW_ISSUE_10969,
0090
0091     /* Race condition can cause tile list corruption */
0092     HW_ISSUE_11020,
0093
0094     /* Write buffer can cause tile list corruption */
0095     HW_ISSUE_11024,
0096
0097     /* Pause buffer can cause a fragment job hang */
0098     HW_ISSUE_11035,
0099
0100     /* Dynamic Core Scaling not supported due to errata */
0101     HW_ISSUE_11056,
0102
0103     /* Clear encoder state for a hard stopped fragment job which is AFBC
0104      * encoded by soft resetting the GPU. Only for T76X r0p0, r0p1 and
0105      * r0p1_50rel0 */
0106     HW_ISSUE_T76X_3542,
0107
0108     /* Keep tiler module clock on to prevent GPU stall */
0109     HW_ISSUE_T76X_3953,
0110
0111     /* Must ensure L2 is not transitioning when we reset. Workaround with a
0112      * busy wait until L2 completes transition; ensure there is a maximum
0113      * loop count as she may never complete her transition. (On chips
0114      * without this errata, it's totally okay if L2 transitions.) */
0115     HW_ISSUE_TMIX_8463,
0116
0117     /* Don't set SC_LS_ATTR_CHECK_DISABLE/SC_LS_ALLOW_ATTR_TYPES */
0118     GPUCORE_1619,
0119
0120     /* When a hard-stop follows close after a soft-stop, the completion
0121      * code for the terminated job may be incorrectly set to STOPPED */
0122     HW_ISSUE_TMIX_8438,
0123
0124     /* "Protected mode" is buggy on Mali-G31 some Bifrost chips, so the
0125      * kernel must fiddle with L2 caches to prevent data leakage */
0126     HW_ISSUE_TGOX_R1_1234,
0127
0128     /* Must set SC_VAR_ALGORITHM */
0129     HW_ISSUE_TTRX_2968_TTRX_3162,
0130
0131     /* Bus fault from occlusion query write may cause future fragment jobs
0132      * to hang */
0133     HW_ISSUE_TTRX_3076,
0134
0135     /* Must issue a dummy job before starting real work to prevent hangs */
0136     HW_ISSUE_TTRX_3485,
0137
0138     HW_ISSUE_END
0139 };
0140
0141 #define hw_issues_all (\
0142     BIT_ULL(HW_ISSUE_9435))
0143
0144 #define hw_issues_t600 (\
0145     BIT_ULL(HW_ISSUE_6367) | \
0146     BIT_ULL(HW_ISSUE_6787) | \
0147     BIT_ULL(HW_ISSUE_8408) | \
0148     BIT_ULL(HW_ISSUE_9510) | \
0149     BIT_ULL(HW_ISSUE_10649) | \
0150     BIT_ULL(HW_ISSUE_10676) | \
0151     BIT_ULL(HW_ISSUE_10883) | \
0152     BIT_ULL(HW_ISSUE_11020) | \
0153     BIT_ULL(HW_ISSUE_11035) | \
0154     BIT_ULL(HW_ISSUE_11056) | \
0155     BIT_ULL(HW_ISSUE_TMIX_8438))
0156
0157 #define hw_issues_t600_r0p0_15dev0 (\
0158     BIT_ULL(HW_ISSUE_8186) | \
0159     BIT_ULL(HW_ISSUE_8245) | \
0160     BIT_ULL(HW_ISSUE_8316) | \
0161     BIT_ULL(HW_ISSUE_8394) | \
0162     BIT_ULL(HW_ISSUE_8401) | \
0163     BIT_ULL(HW_ISSUE_8443) | \
0164     BIT_ULL(HW_ISSUE_8987) | \
0165     BIT_ULL(HW_ISSUE_9630) | \
0166     BIT_ULL(HW_ISSUE_10969) | \
0167     BIT_ULL(GPUCORE_1619))
0168
0169 #define hw_issues_t620 (\
0170     BIT_ULL(HW_ISSUE_10649) | \
0171     BIT_ULL(HW_ISSUE_10883) | \
0172     BIT_ULL(HW_ISSUE_10959) | \
0173     BIT_ULL(HW_ISSUE_11056) | \
0174     BIT_ULL(HW_ISSUE_TMIX_8438))
0175
0176 #define hw_issues_t620_r0p1 (\
0177     BIT_ULL(HW_ISSUE_10327) | \
0178     BIT_ULL(HW_ISSUE_10676) | \
0179     BIT_ULL(HW_ISSUE_10817) | \
0180     BIT_ULL(HW_ISSUE_11020) | \
0181     BIT_ULL(HW_ISSUE_11024) | \
0182     BIT_ULL(HW_ISSUE_11035))
0183
0184 #define hw_issues_t620_r1p0 (\
0185     BIT_ULL(HW_ISSUE_11020) | \
0186     BIT_ULL(HW_ISSUE_11024))
0187
0188 #define hw_issues_t720 (\
0189     BIT_ULL(HW_ISSUE_10649) | \
0190     BIT_ULL(HW_ISSUE_10797) | \
0191     BIT_ULL(HW_ISSUE_10883) | \
0192     BIT_ULL(HW_ISSUE_11056) | \
0193     BIT_ULL(HW_ISSUE_TMIX_8438))
0194
0195 #define hw_issues_t760 (\
0196     BIT_ULL(HW_ISSUE_10883) | \
0197     BIT_ULL(HW_ISSUE_T76X_3953) | \
0198     BIT_ULL(HW_ISSUE_TMIX_8438))
0199
0200 #define hw_issues_t760_r0p0 (\
0201     BIT_ULL(HW_ISSUE_11020) | \
0202     BIT_ULL(HW_ISSUE_11024) | \
0203     BIT_ULL(HW_ISSUE_T76X_3542))
0204
0205 #define hw_issues_t760_r0p1 (\
0206     BIT_ULL(HW_ISSUE_11020) | \
0207     BIT_ULL(HW_ISSUE_11024) | \
0208     BIT_ULL(HW_ISSUE_T76X_3542))
0209
0210 #define hw_issues_t760_r0p1_50rel0 (\
0211     BIT_ULL(HW_ISSUE_T76X_3542))
0212
0213 #define hw_issues_t760_r0p2 (\
0214     BIT_ULL(HW_ISSUE_11020) | \
0215     BIT_ULL(HW_ISSUE_11024) | \
0216     BIT_ULL(HW_ISSUE_T76X_3542))
0217
0218 #define hw_issues_t760_r0p3 (\
0219     BIT_ULL(HW_ISSUE_T76X_3542))
0220
0221 #define hw_issues_t820 (\
0222     BIT_ULL(HW_ISSUE_10883) | \
0223     BIT_ULL(HW_ISSUE_T76X_3953) | \
0224     BIT_ULL(HW_ISSUE_TMIX_8438))
0225
0226 #define hw_issues_t830 (\
0227     BIT_ULL(HW_ISSUE_10883) | \
0228     BIT_ULL(HW_ISSUE_T76X_3953) | \
0229     BIT_ULL(HW_ISSUE_TMIX_8438))
0230
0231 #define hw_issues_t860 (\
0232     BIT_ULL(HW_ISSUE_10883) | \
0233     BIT_ULL(HW_ISSUE_T76X_3953) | \
0234     BIT_ULL(HW_ISSUE_TMIX_8438))
0235
0236 #define hw_issues_t880 (\
0237     BIT_ULL(HW_ISSUE_10883) | \
0238     BIT_ULL(HW_ISSUE_T76X_3953) | \
0239     BIT_ULL(HW_ISSUE_TMIX_8438))
0240
0241 #define hw_issues_g31 0
0242
0243 #define hw_issues_g31_r1p0 (\
0244     BIT_ULL(HW_ISSUE_TGOX_R1_1234))
0245
0246 #define hw_issues_g51 0
0247
0248 #define hw_issues_g52 0
0249
0250 #define hw_issues_g71 (\
0251     BIT_ULL(HW_ISSUE_TMIX_8463) | \
0252     BIT_ULL(HW_ISSUE_TMIX_8438))
0253
0254 #define hw_issues_g71_r0p0_05dev0 (\
0255     BIT_ULL(HW_ISSUE_T76X_3953))
0256
0257 #define hw_issues_g72 0
0258
0259 #define hw_issues_g76 0
0260
0261 #define hw_issues_g57 (\
0262     BIT_ULL(HW_ISSUE_TTRX_2968_TTRX_3162) | \
0263     BIT_ULL(HW_ISSUE_TTRX_3076))
0264
0265 #define hw_issues_g57_r0p0 (\
0266     BIT_ULL(HW_ISSUE_TTRX_3485))
0267
0268 static inline bool panfrost_has_hw_issue(const struct panfrost_device *pfdev,
0269                      enum panfrost_hw_issue issue)
0270 {
0271     return test_bit(issue, pfdev->features.hw_issues);
0272 }
0273
0274 #endif /* __PANFROST_ISSUES_H__ */