drm/panel/panel-tpo-td028ttec1.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Toppoly TD028TTEC1 Panel Driver
0004  *
0005  * Copyright (C) 2019 Texas Instruments Incorporated
0006  *
0007  * Based on the omapdrm-specific panel-tpo-td028ttec1 driver
0008  *
0009  * Copyright (C) 2008 Nokia Corporation
0010  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
0011  *
0012  * Neo 1973 code (jbt6k74.c):
0013  * Copyright (C) 2006-2007 OpenMoko, Inc.
0014  * Author: Harald Welte <laforge@openmoko.org>
0015  *
0016  * Ported and adapted from Neo 1973 U-Boot by:
0017  * H. Nikolaus Schaller <hns@goldelico.com>
0018  */
0019
0020 #include <linux/delay.h>
0021 #include <linux/module.h>
0022 #include <linux/spi/spi.h>
0023
0024 #include <drm/drm_connector.h>
0025 #include <drm/drm_modes.h>
0026 #include <drm/drm_panel.h>
0027
0028 #define JBT_COMMAND         0x000
0029 #define JBT_DATA            0x100
0030
0031 #define JBT_REG_SLEEP_IN        0x10
0032 #define JBT_REG_SLEEP_OUT       0x11
0033
0034 #define JBT_REG_DISPLAY_OFF     0x28
0035 #define JBT_REG_DISPLAY_ON      0x29
0036
0037 #define JBT_REG_RGB_FORMAT      0x3a
0038 #define JBT_REG_QUAD_RATE       0x3b
0039
0040 #define JBT_REG_POWER_ON_OFF        0xb0
0041 #define JBT_REG_BOOSTER_OP      0xb1
0042 #define JBT_REG_BOOSTER_MODE        0xb2
0043 #define JBT_REG_BOOSTER_FREQ        0xb3
0044 #define JBT_REG_OPAMP_SYSCLK        0xb4
0045 #define JBT_REG_VSC_VOLTAGE     0xb5
0046 #define JBT_REG_VCOM_VOLTAGE        0xb6
0047 #define JBT_REG_EXT_DISPL       0xb7
0048 #define JBT_REG_OUTPUT_CONTROL      0xb8
0049 #define JBT_REG_DCCLK_DCEV      0xb9
0050 #define JBT_REG_DISPLAY_MODE1       0xba
0051 #define JBT_REG_DISPLAY_MODE2       0xbb
0052 #define JBT_REG_DISPLAY_MODE        0xbc
0053 #define JBT_REG_ASW_SLEW        0xbd
0054 #define JBT_REG_DUMMY_DISPLAY       0xbe
0055 #define JBT_REG_DRIVE_SYSTEM        0xbf
0056
0057 #define JBT_REG_SLEEP_OUT_FR_A      0xc0
0058 #define JBT_REG_SLEEP_OUT_FR_B      0xc1
0059 #define JBT_REG_SLEEP_OUT_FR_C      0xc2
0060 #define JBT_REG_SLEEP_IN_LCCNT_D    0xc3
0061 #define JBT_REG_SLEEP_IN_LCCNT_E    0xc4
0062 #define JBT_REG_SLEEP_IN_LCCNT_F    0xc5
0063 #define JBT_REG_SLEEP_IN_LCCNT_G    0xc6
0064
0065 #define JBT_REG_GAMMA1_FINE_1       0xc7
0066 #define JBT_REG_GAMMA1_FINE_2       0xc8
0067 #define JBT_REG_GAMMA1_INCLINATION  0xc9
0068 #define JBT_REG_GAMMA1_BLUE_OFFSET  0xca
0069
0070 #define JBT_REG_BLANK_CONTROL       0xcf
0071 #define JBT_REG_BLANK_TH_TV     0xd0
0072 #define JBT_REG_CKV_ON_OFF      0xd1
0073 #define JBT_REG_CKV_1_2         0xd2
0074 #define JBT_REG_OEV_TIMING      0xd3
0075 #define JBT_REG_ASW_TIMING_1        0xd4
0076 #define JBT_REG_ASW_TIMING_2        0xd5
0077
0078 #define JBT_REG_HCLOCK_VGA      0xec
0079 #define JBT_REG_HCLOCK_QVGA     0xed
0080
0081 struct td028ttec1_panel {
0082     struct drm_panel panel;
0083
0084     struct spi_device *spi;
0085 };
0086
0087 #define to_td028ttec1_device(p) container_of(p, struct td028ttec1_panel, panel)
0088
0089 /*
0090  * noinline_for_stack so we don't get multiple copies of tx_buf
0091  * on the stack in case of gcc-plugin-structleak
0092  */
0093 static int noinline_for_stack
0094 jbt_ret_write_0(struct td028ttec1_panel *lcd, u8 reg, int *err)
0095 {
0096     struct spi_device *spi = lcd->spi;
0097     u16 tx_buf = JBT_COMMAND | reg;
0098     int ret;
0099
0100     if (err && *err)
0101         return *err;
0102
0103     ret = spi_write(spi, (u8 *)&tx_buf, sizeof(tx_buf));
0104     if (ret < 0) {
0105         dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
0106         if (err)
0107             *err = ret;
0108     }
0109
0110     return ret;
0111 }
0112
0113 static int noinline_for_stack
0114 jbt_reg_write_1(struct td028ttec1_panel *lcd,
0115         u8 reg, u8 data, int *err)
0116 {
0117     struct spi_device *spi = lcd->spi;
0118     u16 tx_buf[2];
0119     int ret;
0120
0121     if (err && *err)
0122         return *err;
0123
0124     tx_buf[0] = JBT_COMMAND | reg;
0125     tx_buf[1] = JBT_DATA | data;
0126
0127     ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
0128     if (ret < 0) {
0129         dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
0130         if (err)
0131             *err = ret;
0132     }
0133
0134     return ret;
0135 }
0136
0137 static int noinline_for_stack
0138 jbt_reg_write_2(struct td028ttec1_panel *lcd,
0139         u8 reg, u16 data, int *err)
0140 {
0141     struct spi_device *spi = lcd->spi;
0142     u16 tx_buf[3];
0143     int ret;
0144
0145     if (err && *err)
0146         return *err;
0147
0148     tx_buf[0] = JBT_COMMAND | reg;
0149     tx_buf[1] = JBT_DATA | (data >> 8);
0150     tx_buf[2] = JBT_DATA | (data & 0xff);
0151
0152     ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
0153     if (ret < 0) {
0154         dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
0155         if (err)
0156             *err = ret;
0157     }
0158
0159     return ret;
0160 }
0161
0162 static int td028ttec1_prepare(struct drm_panel *panel)
0163 {
0164     struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
0165     unsigned int i;
0166     int ret = 0;
0167
0168     /* Three times command zero */
0169     for (i = 0; i < 3; ++i) {
0170         jbt_ret_write_0(lcd, 0x00, &ret);
0171         usleep_range(1000, 2000);
0172     }
0173
0174     /* deep standby out */
0175     jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x17, &ret);
0176
0177     /* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
0178     jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE, 0x80, &ret);
0179
0180     /* Quad mode off */
0181     jbt_reg_write_1(lcd, JBT_REG_QUAD_RATE, 0x00, &ret);
0182
0183     /* AVDD on, XVDD on */
0184     jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x16, &ret);
0185
0186     /* Output control */
0187     jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0xfff9, &ret);
0188
0189     /* Sleep mode off */
0190     jbt_ret_write_0(lcd, JBT_REG_SLEEP_OUT, &ret);
0191
0192     /* at this point we have like 50% grey */
0193
0194     /* initialize register set */
0195     jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE1, 0x01, &ret);
0196     jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE2, 0x00, &ret);
0197     jbt_reg_write_1(lcd, JBT_REG_RGB_FORMAT, 0x60, &ret);
0198     jbt_reg_write_1(lcd, JBT_REG_DRIVE_SYSTEM, 0x10, &ret);
0199     jbt_reg_write_1(lcd, JBT_REG_BOOSTER_OP, 0x56, &ret);
0200     jbt_reg_write_1(lcd, JBT_REG_BOOSTER_MODE, 0x33, &ret);
0201     jbt_reg_write_1(lcd, JBT_REG_BOOSTER_FREQ, 0x11, &ret);
0202     jbt_reg_write_1(lcd, JBT_REG_BOOSTER_FREQ, 0x11, &ret);
0203     jbt_reg_write_1(lcd, JBT_REG_OPAMP_SYSCLK, 0x02, &ret);
0204     jbt_reg_write_1(lcd, JBT_REG_VSC_VOLTAGE, 0x2b, &ret);
0205     jbt_reg_write_1(lcd, JBT_REG_VCOM_VOLTAGE, 0x40, &ret);
0206     jbt_reg_write_1(lcd, JBT_REG_EXT_DISPL, 0x03, &ret);
0207     jbt_reg_write_1(lcd, JBT_REG_DCCLK_DCEV, 0x04, &ret);
0208     /*
0209      * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
0210      * to avoid red / blue flicker
0211      */
0212     jbt_reg_write_1(lcd, JBT_REG_ASW_SLEW, 0x04, &ret);
0213     jbt_reg_write_1(lcd, JBT_REG_DUMMY_DISPLAY, 0x00, &ret);
0214
0215     jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_A, 0x11, &ret);
0216     jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_B, 0x11, &ret);
0217     jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_C, 0x11, &ret);
0218     jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040, &ret);
0219     jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0, &ret);
0220     jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020, &ret);
0221     jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0, &ret);
0222
0223     jbt_reg_write_2(lcd, JBT_REG_GAMMA1_FINE_1, 0x5533, &ret);
0224     jbt_reg_write_1(lcd, JBT_REG_GAMMA1_FINE_2, 0x00, &ret);
0225     jbt_reg_write_1(lcd, JBT_REG_GAMMA1_INCLINATION, 0x00, &ret);
0226     jbt_reg_write_1(lcd, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00, &ret);
0227
0228     jbt_reg_write_2(lcd, JBT_REG_HCLOCK_VGA, 0x1f0, &ret);
0229     jbt_reg_write_1(lcd, JBT_REG_BLANK_CONTROL, 0x02, &ret);
0230     jbt_reg_write_2(lcd, JBT_REG_BLANK_TH_TV, 0x0804, &ret);
0231
0232     jbt_reg_write_1(lcd, JBT_REG_CKV_ON_OFF, 0x01, &ret);
0233     jbt_reg_write_2(lcd, JBT_REG_CKV_1_2, 0x0000, &ret);
0234
0235     jbt_reg_write_2(lcd, JBT_REG_OEV_TIMING, 0x0d0e, &ret);
0236     jbt_reg_write_2(lcd, JBT_REG_ASW_TIMING_1, 0x11a4, &ret);
0237     jbt_reg_write_1(lcd, JBT_REG_ASW_TIMING_2, 0x0e, &ret);
0238
0239     return ret;
0240 }
0241
0242 static int td028ttec1_enable(struct drm_panel *panel)
0243 {
0244     struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
0245
0246     return jbt_ret_write_0(lcd, JBT_REG_DISPLAY_ON, NULL);
0247 }
0248
0249 static int td028ttec1_disable(struct drm_panel *panel)
0250 {
0251     struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
0252
0253     jbt_ret_write_0(lcd, JBT_REG_DISPLAY_OFF, NULL);
0254
0255     return 0;
0256 }
0257
0258 static int td028ttec1_unprepare(struct drm_panel *panel)
0259 {
0260     struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
0261
0262     jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0x8002, NULL);
0263     jbt_ret_write_0(lcd, JBT_REG_SLEEP_IN, NULL);
0264     jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x00, NULL);
0265
0266     return 0;
0267 }
0268
0269 static const struct drm_display_mode td028ttec1_mode = {
0270     .clock = 22153,
0271     .hdisplay = 480,
0272     .hsync_start = 480 + 24,
0273     .hsync_end = 480 + 24 + 8,
0274     .htotal = 480 + 24 + 8 + 8,
0275     .vdisplay = 640,
0276     .vsync_start = 640 + 4,
0277     .vsync_end = 640 + 4 + 2,
0278     .vtotal = 640 + 4 + 2 + 2,
0279     .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
0280     .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
0281     .width_mm = 43,
0282     .height_mm = 58,
0283 };
0284
0285 static int td028ttec1_get_modes(struct drm_panel *panel,
0286                 struct drm_connector *connector)
0287 {
0288     struct drm_display_mode *mode;
0289
0290     mode = drm_mode_duplicate(connector->dev, &td028ttec1_mode);
0291     if (!mode)
0292         return -ENOMEM;
0293
0294     drm_mode_set_name(mode);
0295     drm_mode_probed_add(connector, mode);
0296
0297     connector->display_info.width_mm = td028ttec1_mode.width_mm;
0298     connector->display_info.height_mm = td028ttec1_mode.height_mm;
0299     /*
0300      * FIXME: According to the datasheet sync signals are sampled on the
0301      * rising edge of the clock, but the code running on the OpenMoko Neo
0302      * FreeRunner and Neo 1973 indicates sampling on the falling edge. This
0303      * should be tested on a real device.
0304      */
0305     connector->display_info.bus_flags = DRM_BUS_FLAG_DE_HIGH
0306                       | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
0307                       | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE;
0308
0309     return 1;
0310 }
0311
0312 static const struct drm_panel_funcs td028ttec1_funcs = {
0313     .prepare = td028ttec1_prepare,
0314     .enable = td028ttec1_enable,
0315     .disable = td028ttec1_disable,
0316     .unprepare = td028ttec1_unprepare,
0317     .get_modes = td028ttec1_get_modes,
0318 };
0319
0320 static int td028ttec1_probe(struct spi_device *spi)
0321 {
0322     struct td028ttec1_panel *lcd;
0323     int ret;
0324
0325     lcd = devm_kzalloc(&spi->dev, sizeof(*lcd), GFP_KERNEL);
0326     if (!lcd)
0327         return -ENOMEM;
0328
0329     spi_set_drvdata(spi, lcd);
0330     lcd->spi = spi;
0331
0332     spi->mode = SPI_MODE_3;
0333     spi->bits_per_word = 9;
0334
0335     ret = spi_setup(spi);
0336     if (ret < 0) {
0337         dev_err(&spi->dev, "failed to setup SPI: %d\n", ret);
0338         return ret;
0339     }
0340
0341     drm_panel_init(&lcd->panel, &lcd->spi->dev, &td028ttec1_funcs,
0342                DRM_MODE_CONNECTOR_DPI);
0343
0344     ret = drm_panel_of_backlight(&lcd->panel);
0345     if (ret)
0346         return ret;
0347
0348     drm_panel_add(&lcd->panel);
0349
0350     return 0;
0351 }
0352
0353 static void td028ttec1_remove(struct spi_device *spi)
0354 {
0355     struct td028ttec1_panel *lcd = spi_get_drvdata(spi);
0356
0357     drm_panel_remove(&lcd->panel);
0358     drm_panel_disable(&lcd->panel);
0359     drm_panel_unprepare(&lcd->panel);
0360 }
0361
0362 static const struct of_device_id td028ttec1_of_match[] = {
0363     { .compatible = "tpo,td028ttec1", },
0364     /* DT backward compatibility. */
0365     { .compatible = "toppoly,td028ttec1", },
0366     { /* sentinel */ },
0367 };
0368
0369 MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
0370
0371 static const struct spi_device_id td028ttec1_ids[] = {
0372     { "td028ttec1", 0 },
0373     { /* sentinel */ }
0374 };
0375
0376 MODULE_DEVICE_TABLE(spi, td028ttec1_ids);
0377
0378 static struct spi_driver td028ttec1_driver = {
0379     .probe      = td028ttec1_probe,
0380     .remove     = td028ttec1_remove,
0381     .id_table   = td028ttec1_ids,
0382     .driver     = {
0383         .name   = "panel-tpo-td028ttec1",
0384         .of_match_table = td028ttec1_of_match,
0385     },
0386 };
0387
0388 module_spi_driver(td028ttec1_driver);
0389
0390 MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
0391 MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
0392 MODULE_LICENSE("GPL");