drm/panel/panel-sitronix-st7701.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (C) 2019, Amarula Solutions.
0004  * Author: Jagan Teki <jagan@amarulasolutions.com>
0005  */
0006
0007 #include <drm/drm_mipi_dsi.h>
0008 #include <drm/drm_modes.h>
0009 #include <drm/drm_panel.h>
0010
0011 #include <linux/gpio/consumer.h>
0012 #include <linux/delay.h>
0013 #include <linux/module.h>
0014 #include <linux/of_device.h>
0015 #include <linux/regulator/consumer.h>
0016
0017 #include <video/mipi_display.h>
0018
0019 /* Command2 BKx selection command */
0020 #define DSI_CMD2BKX_SEL         0xFF
0021
0022 /* Command2, BK0 commands */
0023 #define DSI_CMD2_BK0_PVGAMCTRL      0xB0 /* Positive Voltage Gamma Control */
0024 #define DSI_CMD2_BK0_NVGAMCTRL      0xB1 /* Negative Voltage Gamma Control */
0025 #define DSI_CMD2_BK0_LNESET     0xC0 /* Display Line setting */
0026 #define DSI_CMD2_BK0_PORCTRL        0xC1 /* Porch control */
0027 #define DSI_CMD2_BK0_INVSEL     0xC2 /* Inversion selection, Frame Rate Control */
0028
0029 /* Command2, BK1 commands */
0030 #define DSI_CMD2_BK1_VRHS       0xB0 /* Vop amplitude setting */
0031 #define DSI_CMD2_BK1_VCOM       0xB1 /* VCOM amplitude setting */
0032 #define DSI_CMD2_BK1_VGHSS      0xB2 /* VGH Voltage setting */
0033 #define DSI_CMD2_BK1_TESTCMD        0xB3 /* TEST Command Setting */
0034 #define DSI_CMD2_BK1_VGLS       0xB5 /* VGL Voltage setting */
0035 #define DSI_CMD2_BK1_PWCTLR1        0xB7 /* Power Control 1 */
0036 #define DSI_CMD2_BK1_PWCTLR2        0xB8 /* Power Control 2 */
0037 #define DSI_CMD2_BK1_SPD1       0xC1 /* Source pre_drive timing set1 */
0038 #define DSI_CMD2_BK1_SPD2       0xC2 /* Source EQ2 Setting */
0039 #define DSI_CMD2_BK1_MIPISET1       0xD0 /* MIPI Setting 1 */
0040
0041 /*
0042  * Command2 with BK function selection.
0043  *
0044  * BIT[4, 0]: [CN2, BKXSEL]
0045  * 10 = CMD2BK0, Command2 BK0
0046  * 11 = CMD2BK1, Command2 BK1
0047  * 00 = Command2 disable
0048  */
0049 #define DSI_CMD2BK1_SEL         0x11
0050 #define DSI_CMD2BK0_SEL         0x10
0051 #define DSI_CMD2BKX_SEL_NONE        0x00
0052
0053 /* Command2, BK0 bytes */
0054 #define DSI_LINESET_LINE        0x69
0055 #define DSI_LINESET_LDE_EN      BIT(7)
0056 #define DSI_LINESET_LINEDELTA       GENMASK(1, 0)
0057 #define DSI_CMD2_BK0_LNESET_B1      DSI_LINESET_LINEDELTA
0058 #define DSI_CMD2_BK0_LNESET_B0      (DSI_LINESET_LDE_EN | DSI_LINESET_LINE)
0059 #define DSI_INVSEL_DEFAULT      GENMASK(5, 4)
0060 #define DSI_INVSEL_NLINV        GENMASK(2, 0)
0061 #define DSI_INVSEL_RTNI         GENMASK(2, 1)
0062 #define DSI_CMD2_BK0_INVSEL_B1      DSI_INVSEL_RTNI
0063 #define DSI_CMD2_BK0_INVSEL_B0      (DSI_INVSEL_DEFAULT | DSI_INVSEL_NLINV)
0064 #define DSI_CMD2_BK0_PORCTRL_B0(m)  ((m)->vtotal - (m)->vsync_end)
0065 #define DSI_CMD2_BK0_PORCTRL_B1(m)  ((m)->vsync_start - (m)->vdisplay)
0066
0067 /* Command2, BK1 bytes */
0068 #define DSI_CMD2_BK1_VRHA_SET       0x45
0069 #define DSI_CMD2_BK1_VCOM_SET       0x13
0070 #define DSI_CMD2_BK1_VGHSS_SET      GENMASK(2, 0)
0071 #define DSI_CMD2_BK1_TESTCMD_VAL    BIT(7)
0072 #define DSI_VGLS_DEFAULT        BIT(6)
0073 #define DSI_VGLS_SEL            GENMASK(2, 0)
0074 #define DSI_CMD2_BK1_VGLS_SET       (DSI_VGLS_DEFAULT | DSI_VGLS_SEL)
0075 #define DSI_PWCTLR1_AP          BIT(7) /* Gamma OP bias, max */
0076 #define DSI_PWCTLR1_APIS        BIT(2) /* Source OP input bias, min */
0077 #define DSI_PWCTLR1_APOS        BIT(0) /* Source OP output bias, min */
0078 #define DSI_CMD2_BK1_PWCTLR1_SET    (DSI_PWCTLR1_AP | DSI_PWCTLR1_APIS | \
0079                     DSI_PWCTLR1_APOS)
0080 #define DSI_PWCTLR2_AVDD        BIT(5) /* AVDD 6.6v */
0081 #define DSI_PWCTLR2_AVCL        0x0    /* AVCL -4.4v */
0082 #define DSI_CMD2_BK1_PWCTLR2_SET    (DSI_PWCTLR2_AVDD | DSI_PWCTLR2_AVCL)
0083 #define DSI_SPD1_T2D            BIT(3)
0084 #define DSI_CMD2_BK1_SPD1_SET       (GENMASK(6, 4) | DSI_SPD1_T2D)
0085 #define DSI_CMD2_BK1_SPD2_SET       DSI_CMD2_BK1_SPD1_SET
0086 #define DSI_MIPISET1_EOT_EN     BIT(3)
0087 #define DSI_CMD2_BK1_MIPISET1_SET   (BIT(7) | DSI_MIPISET1_EOT_EN)
0088
0089 struct st7701_panel_desc {
0090     const struct drm_display_mode *mode;
0091     unsigned int lanes;
0092     unsigned long flags;
0093     enum mipi_dsi_pixel_format format;
0094     const char *const *supply_names;
0095     unsigned int num_supplies;
0096     unsigned int panel_sleep_delay;
0097 };
0098
0099 struct st7701 {
0100     struct drm_panel panel;
0101     struct mipi_dsi_device *dsi;
0102     const struct st7701_panel_desc *desc;
0103
0104     struct regulator_bulk_data *supplies;
0105     struct gpio_desc *reset;
0106     unsigned int sleep_delay;
0107 };
0108
0109 static inline struct st7701 *panel_to_st7701(struct drm_panel *panel)
0110 {
0111     return container_of(panel, struct st7701, panel);
0112 }
0113
0114 static inline int st7701_dsi_write(struct st7701 *st7701, const void *seq,
0115                    size_t len)
0116 {
0117     return mipi_dsi_dcs_write_buffer(st7701->dsi, seq, len);
0118 }
0119
0120 #define ST7701_DSI(st7701, seq...)              \
0121     {                           \
0122         const u8 d[] = { seq };             \
0123         st7701_dsi_write(st7701, d, ARRAY_SIZE(d)); \
0124     }
0125
0126 static void st7701_init_sequence(struct st7701 *st7701)
0127 {
0128     const struct drm_display_mode *mode = st7701->desc->mode;
0129
0130     ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00);
0131
0132     /* We need to wait 5ms before sending new commands */
0133     msleep(5);
0134
0135     ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
0136
0137     msleep(st7701->sleep_delay);
0138
0139     /* Command2, BK0 */
0140     ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
0141            0x77, 0x01, 0x00, 0x00, DSI_CMD2BK0_SEL);
0142     ST7701_DSI(st7701, DSI_CMD2_BK0_PVGAMCTRL, 0x00, 0x0E, 0x15, 0x0F,
0143            0x11, 0x08, 0x08, 0x08, 0x08, 0x23, 0x04, 0x13, 0x12,
0144            0x2B, 0x34, 0x1F);
0145     ST7701_DSI(st7701, DSI_CMD2_BK0_NVGAMCTRL, 0x00, 0x0E, 0x95, 0x0F,
0146            0x13, 0x07, 0x09, 0x08, 0x08, 0x22, 0x04, 0x10, 0x0E,
0147            0x2C, 0x34, 0x1F);
0148     ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET,
0149            DSI_CMD2_BK0_LNESET_B0, DSI_CMD2_BK0_LNESET_B1);
0150     ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL,
0151            DSI_CMD2_BK0_PORCTRL_B0(mode),
0152            DSI_CMD2_BK0_PORCTRL_B1(mode));
0153     ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL,
0154            DSI_CMD2_BK0_INVSEL_B0, DSI_CMD2_BK0_INVSEL_B1);
0155
0156     /* Command2, BK1 */
0157     ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
0158             0x77, 0x01, 0x00, 0x00, DSI_CMD2BK1_SEL);
0159     ST7701_DSI(st7701, DSI_CMD2_BK1_VRHS, DSI_CMD2_BK1_VRHA_SET);
0160     ST7701_DSI(st7701, DSI_CMD2_BK1_VCOM, DSI_CMD2_BK1_VCOM_SET);
0161     ST7701_DSI(st7701, DSI_CMD2_BK1_VGHSS, DSI_CMD2_BK1_VGHSS_SET);
0162     ST7701_DSI(st7701, DSI_CMD2_BK1_TESTCMD, DSI_CMD2_BK1_TESTCMD_VAL);
0163     ST7701_DSI(st7701, DSI_CMD2_BK1_VGLS, DSI_CMD2_BK1_VGLS_SET);
0164     ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR1, DSI_CMD2_BK1_PWCTLR1_SET);
0165     ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR2, DSI_CMD2_BK1_PWCTLR2_SET);
0166     ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1, DSI_CMD2_BK1_SPD1_SET);
0167     ST7701_DSI(st7701, DSI_CMD2_BK1_SPD2, DSI_CMD2_BK1_SPD2_SET);
0168     ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1, DSI_CMD2_BK1_MIPISET1_SET);
0169
0170     /**
0171      * ST7701_SPEC_V1.2 is unable to provide enough information above this
0172      * specific command sequence, so grab the same from vendor BSP driver.
0173      */
0174     ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
0175     ST7701_DSI(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E,
0176            0x00, 0x00, 0x44, 0x44);
0177     ST7701_DSI(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66,
0178            0x00, 0x65, 0x00, 0x67, 0x00, 0x00);
0179     ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);
0180     ST7701_DSI(st7701, 0xE4, 0x44, 0x44);
0181     ST7701_DSI(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C,
0182            0xA0, 0x10, 0x78, 0x3C, 0xA0, 0x12, 0x78, 0x3C, 0xA0);
0183     ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);
0184     ST7701_DSI(st7701, 0xE7, 0x44, 0x44);
0185     ST7701_DSI(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C,
0186            0xA0, 0x11, 0x78, 0x3C, 0xA0, 0x13, 0x78, 0x3C, 0xA0);
0187     ST7701_DSI(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00);
0188     ST7701_DSI(st7701, 0xEC, 0x00, 0x00);
0189     ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF,
0190            0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF);
0191
0192     /* disable Command2 */
0193     ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
0194            0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE);
0195 }
0196
0197 static int st7701_prepare(struct drm_panel *panel)
0198 {
0199     struct st7701 *st7701 = panel_to_st7701(panel);
0200     int ret;
0201
0202     gpiod_set_value(st7701->reset, 0);
0203
0204     ret = regulator_bulk_enable(st7701->desc->num_supplies,
0205                     st7701->supplies);
0206     if (ret < 0)
0207         return ret;
0208     msleep(20);
0209
0210     gpiod_set_value(st7701->reset, 1);
0211     msleep(150);
0212
0213     st7701_init_sequence(st7701);
0214
0215     return 0;
0216 }
0217
0218 static int st7701_enable(struct drm_panel *panel)
0219 {
0220     struct st7701 *st7701 = panel_to_st7701(panel);
0221
0222     ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00);
0223
0224     return 0;
0225 }
0226
0227 static int st7701_disable(struct drm_panel *panel)
0228 {
0229     struct st7701 *st7701 = panel_to_st7701(panel);
0230
0231     ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00);
0232
0233     return 0;
0234 }
0235
0236 static int st7701_unprepare(struct drm_panel *panel)
0237 {
0238     struct st7701 *st7701 = panel_to_st7701(panel);
0239
0240     ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00);
0241
0242     msleep(st7701->sleep_delay);
0243
0244     gpiod_set_value(st7701->reset, 0);
0245
0246     /**
0247      * During the Resetting period, the display will be blanked
0248      * (The display is entering blanking sequence, which maximum
0249      * time is 120 ms, when Reset Starts in Sleep Out –mode. The
0250      * display remains the blank state in Sleep In –mode.) and
0251      * then return to Default condition for Hardware Reset.
0252      *
0253      * So we need wait sleep_delay time to make sure reset completed.
0254      */
0255     msleep(st7701->sleep_delay);
0256
0257     regulator_bulk_disable(st7701->desc->num_supplies, st7701->supplies);
0258
0259     return 0;
0260 }
0261
0262 static int st7701_get_modes(struct drm_panel *panel,
0263                 struct drm_connector *connector)
0264 {
0265     struct st7701 *st7701 = panel_to_st7701(panel);
0266     const struct drm_display_mode *desc_mode = st7701->desc->mode;
0267     struct drm_display_mode *mode;
0268
0269     mode = drm_mode_duplicate(connector->dev, desc_mode);
0270     if (!mode) {
0271         dev_err(&st7701->dsi->dev, "failed to add mode %ux%u@%u\n",
0272             desc_mode->hdisplay, desc_mode->vdisplay,
0273             drm_mode_vrefresh(desc_mode));
0274         return -ENOMEM;
0275     }
0276
0277     drm_mode_set_name(mode);
0278     drm_mode_probed_add(connector, mode);
0279
0280     connector->display_info.width_mm = desc_mode->width_mm;
0281     connector->display_info.height_mm = desc_mode->height_mm;
0282
0283     return 1;
0284 }
0285
0286 static const struct drm_panel_funcs st7701_funcs = {
0287     .disable    = st7701_disable,
0288     .unprepare  = st7701_unprepare,
0289     .prepare    = st7701_prepare,
0290     .enable     = st7701_enable,
0291     .get_modes  = st7701_get_modes,
0292 };
0293
0294 static const struct drm_display_mode ts8550b_mode = {
0295     .clock      = 27500,
0296
0297     .hdisplay   = 480,
0298     .hsync_start    = 480 + 38,
0299     .hsync_end  = 480 + 38 + 12,
0300     .htotal     = 480 + 38 + 12 + 12,
0301
0302     .vdisplay   = 854,
0303     .vsync_start    = 854 + 18,
0304     .vsync_end  = 854 + 18 + 8,
0305     .vtotal     = 854 + 18 + 8 + 4,
0306
0307     .width_mm   = 69,
0308     .height_mm  = 139,
0309
0310     .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
0311 };
0312
0313 static const char * const ts8550b_supply_names[] = {
0314     "VCC",
0315     "IOVCC",
0316 };
0317
0318 static const struct st7701_panel_desc ts8550b_desc = {
0319     .mode = &ts8550b_mode,
0320     .lanes = 2,
0321     .flags = MIPI_DSI_MODE_VIDEO,
0322     .format = MIPI_DSI_FMT_RGB888,
0323     .supply_names = ts8550b_supply_names,
0324     .num_supplies = ARRAY_SIZE(ts8550b_supply_names),
0325     .panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */
0326 };
0327
0328 static int st7701_dsi_probe(struct mipi_dsi_device *dsi)
0329 {
0330     const struct st7701_panel_desc *desc;
0331     struct st7701 *st7701;
0332     int ret, i;
0333
0334     st7701 = devm_kzalloc(&dsi->dev, sizeof(*st7701), GFP_KERNEL);
0335     if (!st7701)
0336         return -ENOMEM;
0337
0338     desc = of_device_get_match_data(&dsi->dev);
0339     dsi->mode_flags = desc->flags;
0340     dsi->format = desc->format;
0341     dsi->lanes = desc->lanes;
0342
0343     st7701->supplies = devm_kcalloc(&dsi->dev, desc->num_supplies,
0344                     sizeof(*st7701->supplies),
0345                     GFP_KERNEL);
0346     if (!st7701->supplies)
0347         return -ENOMEM;
0348
0349     for (i = 0; i < desc->num_supplies; i++)
0350         st7701->supplies[i].supply = desc->supply_names[i];
0351
0352     ret = devm_regulator_bulk_get(&dsi->dev, desc->num_supplies,
0353                       st7701->supplies);
0354     if (ret < 0)
0355         return ret;
0356
0357     st7701->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW);
0358     if (IS_ERR(st7701->reset)) {
0359         dev_err(&dsi->dev, "Couldn't get our reset GPIO\n");
0360         return PTR_ERR(st7701->reset);
0361     }
0362
0363     drm_panel_init(&st7701->panel, &dsi->dev, &st7701_funcs,
0364                DRM_MODE_CONNECTOR_DSI);
0365
0366     /**
0367      * Once sleep out has been issued, ST7701 IC required to wait 120ms
0368      * before initiating new commands.
0369      *
0370      * On top of that some panels might need an extra delay to wait, so
0371      * add panel specific delay for those cases. As now this panel specific
0372      * delay information is referenced from those panel BSP driver, example
0373      * ts8550b and there is no valid documentation for that.
0374      */
0375     st7701->sleep_delay = 120 + desc->panel_sleep_delay;
0376
0377     ret = drm_panel_of_backlight(&st7701->panel);
0378     if (ret)
0379         return ret;
0380
0381     drm_panel_add(&st7701->panel);
0382
0383     mipi_dsi_set_drvdata(dsi, st7701);
0384     st7701->dsi = dsi;
0385     st7701->desc = desc;
0386
0387     return mipi_dsi_attach(dsi);
0388 }
0389
0390 static int st7701_dsi_remove(struct mipi_dsi_device *dsi)
0391 {
0392     struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi);
0393
0394     mipi_dsi_detach(dsi);
0395     drm_panel_remove(&st7701->panel);
0396
0397     return 0;
0398 }
0399
0400 static const struct of_device_id st7701_of_match[] = {
0401     { .compatible = "techstar,ts8550b", .data = &ts8550b_desc },
0402     { }
0403 };
0404 MODULE_DEVICE_TABLE(of, st7701_of_match);
0405
0406 static struct mipi_dsi_driver st7701_dsi_driver = {
0407     .probe      = st7701_dsi_probe,
0408     .remove     = st7701_dsi_remove,
0409     .driver = {
0410         .name       = "st7701",
0411         .of_match_table = st7701_of_match,
0412     },
0413 };
0414 module_mipi_dsi_driver(st7701_dsi_driver);
0415
0416 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
0417 MODULE_DESCRIPTION("Sitronix ST7701 LCD Panel Driver");
0418 MODULE_LICENSE("GPL");