drm/panel/panel-innolux-ej030na.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Innolux/Chimei EJ030NA TFT LCD panel driver
0004  *
0005  * Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
0006  * Copyright (C) 2020, Christophe Branchereau <cbranchereau@gmail.com>
0007  */
0008
0009 #include <linux/delay.h>
0010 #include <linux/device.h>
0011 #include <linux/gpio/consumer.h>
0012 #include <linux/media-bus-format.h>
0013 #include <linux/module.h>
0014 #include <linux/of_device.h>
0015 #include <linux/regmap.h>
0016 #include <linux/regulator/consumer.h>
0017 #include <linux/spi/spi.h>
0018
0019 #include <drm/drm_modes.h>
0020 #include <drm/drm_panel.h>
0021
0022 struct ej030na_info {
0023     const struct drm_display_mode *display_modes;
0024     unsigned int num_modes;
0025     u16 width_mm, height_mm;
0026     u32 bus_format, bus_flags;
0027 };
0028
0029 struct ej030na {
0030     struct drm_panel panel;
0031     struct spi_device *spi;
0032     struct regmap *map;
0033
0034     const struct ej030na_info *panel_info;
0035
0036     struct regulator *supply;
0037     struct gpio_desc *reset_gpio;
0038 };
0039
0040 static inline struct ej030na *to_ej030na(struct drm_panel *panel)
0041 {
0042     return container_of(panel, struct ej030na, panel);
0043 }
0044
0045 static const struct reg_sequence ej030na_init_sequence[] = {
0046     { 0x05, 0x1e },
0047     { 0x05, 0x5c },
0048     { 0x02, 0x14 },
0049     { 0x03, 0x40 },
0050     { 0x04, 0x07 },
0051     { 0x06, 0x12 },
0052     { 0x07, 0xd2 },
0053     { 0x0c, 0x06 },
0054     { 0x0d, 0x40 },
0055     { 0x0e, 0x40 },
0056     { 0x0f, 0x40 },
0057     { 0x10, 0x40 },
0058     { 0x11, 0x40 },
0059     { 0x2f, 0x40 },
0060     { 0x5a, 0x02 },
0061
0062     { 0x30, 0x07 },
0063     { 0x31, 0x57 },
0064     { 0x32, 0x53 },
0065     { 0x33, 0x77 },
0066     { 0x34, 0xb8 },
0067     { 0x35, 0xbd },
0068     { 0x36, 0xb8 },
0069     { 0x37, 0xe7 },
0070     { 0x38, 0x04 },
0071     { 0x39, 0xff },
0072
0073     { 0x40, 0x0b },
0074     { 0x41, 0xb8 },
0075     { 0x42, 0xab },
0076     { 0x43, 0xb9 },
0077     { 0x44, 0x6a },
0078     { 0x45, 0x56 },
0079     { 0x46, 0x61 },
0080     { 0x47, 0x08 },
0081     { 0x48, 0x0f },
0082     { 0x49, 0x0f },
0083 };
0084
0085 static int ej030na_prepare(struct drm_panel *panel)
0086 {
0087     struct ej030na *priv = to_ej030na(panel);
0088     struct device *dev = &priv->spi->dev;
0089     int err;
0090
0091     err = regulator_enable(priv->supply);
0092     if (err) {
0093         dev_err(dev, "Failed to enable power supply: %d\n", err);
0094         return err;
0095     }
0096
0097     /* Reset the chip */
0098     gpiod_set_value_cansleep(priv->reset_gpio, 1);
0099     usleep_range(50, 150);
0100     gpiod_set_value_cansleep(priv->reset_gpio, 0);
0101     usleep_range(50, 150);
0102
0103     err = regmap_multi_reg_write(priv->map, ej030na_init_sequence,
0104                      ARRAY_SIZE(ej030na_init_sequence));
0105     if (err) {
0106         dev_err(dev, "Failed to init registers: %d\n", err);
0107         goto err_disable_regulator;
0108     }
0109
0110     return 0;
0111
0112 err_disable_regulator:
0113     regulator_disable(priv->supply);
0114     return err;
0115 }
0116
0117 static int ej030na_unprepare(struct drm_panel *panel)
0118 {
0119     struct ej030na *priv = to_ej030na(panel);
0120
0121     gpiod_set_value_cansleep(priv->reset_gpio, 1);
0122     regulator_disable(priv->supply);
0123
0124     return 0;
0125 }
0126
0127 static int ej030na_enable(struct drm_panel *panel)
0128 {
0129     struct ej030na *priv = to_ej030na(panel);
0130
0131     /* standby off */
0132     regmap_write(priv->map, 0x2b, 0x01);
0133
0134     if (panel->backlight) {
0135         /* Wait for the picture to be ready before enabling backlight */
0136         msleep(120);
0137     }
0138
0139     return 0;
0140 }
0141
0142 static int ej030na_disable(struct drm_panel *panel)
0143 {
0144     struct ej030na *priv = to_ej030na(panel);
0145
0146     /* standby on */
0147     regmap_write(priv->map, 0x2b, 0x00);
0148
0149     return 0;
0150 }
0151
0152 static int ej030na_get_modes(struct drm_panel *panel,
0153                  struct drm_connector *connector)
0154 {
0155     struct ej030na *priv = to_ej030na(panel);
0156     const struct ej030na_info *panel_info = priv->panel_info;
0157     struct drm_display_mode *mode;
0158     unsigned int i;
0159
0160     for (i = 0; i < panel_info->num_modes; i++) {
0161         mode = drm_mode_duplicate(connector->dev,
0162                       &panel_info->display_modes[i]);
0163         if (!mode)
0164             return -ENOMEM;
0165
0166         drm_mode_set_name(mode);
0167
0168         mode->type = DRM_MODE_TYPE_DRIVER;
0169         if (panel_info->num_modes == 1)
0170             mode->type |= DRM_MODE_TYPE_PREFERRED;
0171
0172         drm_mode_probed_add(connector, mode);
0173     }
0174
0175     connector->display_info.bpc = 8;
0176     connector->display_info.width_mm = panel_info->width_mm;
0177     connector->display_info.height_mm = panel_info->height_mm;
0178
0179     drm_display_info_set_bus_formats(&connector->display_info,
0180                      &panel_info->bus_format, 1);
0181     connector->display_info.bus_flags = panel_info->bus_flags;
0182
0183     return panel_info->num_modes;
0184 }
0185
0186 static const struct drm_panel_funcs ej030na_funcs = {
0187     .prepare    = ej030na_prepare,
0188     .unprepare  = ej030na_unprepare,
0189     .enable     = ej030na_enable,
0190     .disable    = ej030na_disable,
0191     .get_modes  = ej030na_get_modes,
0192 };
0193
0194 static const struct regmap_config ej030na_regmap_config = {
0195     .reg_bits = 8,
0196     .val_bits = 8,
0197     .max_register = 0x5a,
0198 };
0199
0200 static int ej030na_probe(struct spi_device *spi)
0201 {
0202     struct device *dev = &spi->dev;
0203     struct ej030na *priv;
0204     int err;
0205
0206     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0207     if (!priv)
0208         return -ENOMEM;
0209
0210     priv->spi = spi;
0211     spi_set_drvdata(spi, priv);
0212
0213     priv->map = devm_regmap_init_spi(spi, &ej030na_regmap_config);
0214     if (IS_ERR(priv->map)) {
0215         dev_err(dev, "Unable to init regmap\n");
0216         return PTR_ERR(priv->map);
0217     }
0218
0219     priv->panel_info = of_device_get_match_data(dev);
0220     if (!priv->panel_info)
0221         return -EINVAL;
0222
0223     priv->supply = devm_regulator_get(dev, "power");
0224     if (IS_ERR(priv->supply))
0225         return dev_err_probe(dev, PTR_ERR(priv->supply),
0226                      "Failed to get power supply\n");
0227
0228     priv->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
0229     if (IS_ERR(priv->reset_gpio))
0230         return dev_err_probe(dev, PTR_ERR(priv->reset_gpio),
0231                      "Failed to get reset GPIO\n");
0232
0233     drm_panel_init(&priv->panel, dev, &ej030na_funcs,
0234                DRM_MODE_CONNECTOR_DPI);
0235
0236     err = drm_panel_of_backlight(&priv->panel);
0237     if (err)
0238         return err;
0239
0240     drm_panel_add(&priv->panel);
0241
0242     return 0;
0243 }
0244
0245 static void ej030na_remove(struct spi_device *spi)
0246 {
0247     struct ej030na *priv = spi_get_drvdata(spi);
0248
0249     drm_panel_remove(&priv->panel);
0250     drm_panel_disable(&priv->panel);
0251     drm_panel_unprepare(&priv->panel);
0252 }
0253
0254 static const struct drm_display_mode ej030na_modes[] = {
0255     { /* 60 Hz */
0256         .clock = 14400,
0257         .hdisplay = 320,
0258         .hsync_start = 320 + 10,
0259         .hsync_end = 320 + 10 + 37,
0260         .htotal = 320 + 10 + 37 + 33,
0261         .vdisplay = 480,
0262         .vsync_start = 480 + 102,
0263         .vsync_end = 480 + 102 + 9 + 9,
0264         .vtotal = 480 + 102 + 9 + 9,
0265         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
0266     },
0267     { /* 50 Hz */
0268         .clock = 12000,
0269         .hdisplay = 320,
0270         .hsync_start = 320 + 10,
0271         .hsync_end = 320 + 10 + 37,
0272         .htotal = 320 + 10 + 37 + 33,
0273         .vdisplay = 480,
0274         .vsync_start = 480 + 102,
0275         .vsync_end = 480 + 102 + 9,
0276         .vtotal = 480 + 102 + 9 + 9,
0277         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
0278     },
0279 };
0280
0281 static const struct ej030na_info ej030na_info = {
0282     .display_modes = ej030na_modes,
0283     .num_modes = ARRAY_SIZE(ej030na_modes),
0284     .width_mm = 70,
0285     .height_mm = 51,
0286     .bus_format = MEDIA_BUS_FMT_RGB888_3X8_DELTA,
0287     .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | DRM_BUS_FLAG_DE_LOW,
0288 };
0289
0290 static const struct of_device_id ej030na_of_match[] = {
0291     { .compatible = "innolux,ej030na", .data = &ej030na_info },
0292     { /* sentinel */ }
0293 };
0294 MODULE_DEVICE_TABLE(of, ej030na_of_match);
0295
0296 static struct spi_driver ej030na_driver = {
0297     .driver = {
0298         .name = "panel-innolux-ej030na",
0299         .of_match_table = ej030na_of_match,
0300     },
0301     .probe = ej030na_probe,
0302     .remove = ej030na_remove,
0303 };
0304 module_spi_driver(ej030na_driver);
0305
0306 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
0307 MODULE_AUTHOR("Christophe Branchereau <cbranchereau@gmail.com>");
0308 MODULE_LICENSE("GPL v2");