drm/panel/panel-abt-y030xx067a.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Asia Better Technology Ltd. Y030XX067A IPS LCD panel driver
0004  *
0005  * Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
0006  * Copyright (C) 2020, Christophe Branchereau <cbranchereau@gmail.com>
0007  */
0008
0009 #include <linux/delay.h>
0010 #include <linux/device.h>
0011 #include <linux/gpio/consumer.h>
0012 #include <linux/media-bus-format.h>
0013 #include <linux/module.h>
0014 #include <linux/of_device.h>
0015 #include <linux/regmap.h>
0016 #include <linux/regulator/consumer.h>
0017 #include <linux/spi/spi.h>
0018
0019 #include <drm/drm_modes.h>
0020 #include <drm/drm_panel.h>
0021
0022 #define REG00_VBRT_CTRL(val)        (val)
0023
0024 #define REG01_COM_DC(val)       (val)
0025
0026 #define REG02_DA_CONTRAST(val)      (val)
0027 #define REG02_VESA_SEL(val)     ((val) << 5)
0028 #define REG02_COMDC_SW          BIT(7)
0029
0030 #define REG03_VPOSITION(val)        (val)
0031 #define REG03_BSMOUNT           BIT(5)
0032 #define REG03_COMTST            BIT(6)
0033 #define REG03_HPOSITION1        BIT(7)
0034
0035 #define REG04_HPOSITION1(val)       (val)
0036
0037 #define REG05_CLIP          BIT(0)
0038 #define REG05_NVM_VREFRESH      BIT(1)
0039 #define REG05_SLFR          BIT(2)
0040 #define REG05_SLBRCHARGE(val)       ((val) << 3)
0041 #define REG05_PRECHARGE_LEVEL(val)  ((val) << 6)
0042
0043 #define REG06_TEST5         BIT(0)
0044 #define REG06_SLDWN         BIT(1)
0045 #define REG06_SLRGT         BIT(2)
0046 #define REG06_TEST2         BIT(3)
0047 #define REG06_XPSAVE            BIT(4)
0048 #define REG06_GAMMA_SEL(val)        ((val) << 5)
0049 #define REG06_NT            BIT(7)
0050
0051 #define REG07_TEST1         BIT(0)
0052 #define REG07_HDVD_POL          BIT(1)
0053 #define REG07_CK_POL            BIT(2)
0054 #define REG07_TEST3         BIT(3)
0055 #define REG07_TEST4         BIT(4)
0056 #define REG07_480_LINEMASK      BIT(5)
0057 #define REG07_AMPTST(val)       ((val) << 6)
0058
0059 #define REG08_SLHRC(val)        (val)
0060 #define REG08_CLOCK_DIV(val)        ((val) << 2)
0061 #define REG08_PANEL(val)        ((val) << 5)
0062
0063 #define REG09_SUB_BRIGHT_R(val)     (val)
0064 #define REG09_NW_NB         BIT(6)
0065 #define REG09_IPCON         BIT(7)
0066
0067 #define REG0A_SUB_BRIGHT_B(val)     (val)
0068 #define REG0A_PAIR          BIT(6)
0069 #define REG0A_DE_SEL            BIT(7)
0070
0071 #define REG0B_MBK_POSITION(val)     (val)
0072 #define REG0B_HD_FREERUN        BIT(4)
0073 #define REG0B_VD_FREERUN        BIT(5)
0074 #define REG0B_YUV2BIN(val)      ((val) << 6)
0075
0076 #define REG0C_CONTRAST_R(val)       (val)
0077 #define REG0C_DOUBLEREAD        BIT(7)
0078
0079 #define REG0D_CONTRAST_G(val)       (val)
0080 #define REG0D_RGB_YUV           BIT(7)
0081
0082 #define REG0E_CONTRAST_B(val)       (val)
0083 #define REG0E_PIXELCOLORDRIVE       BIT(7)
0084
0085 #define REG0F_ASPECT            BIT(0)
0086 #define REG0F_OVERSCAN(val)     ((val) << 1)
0087 #define REG0F_FRAMEWIDTH(val)       ((val) << 3)
0088
0089 #define REG10_BRIGHT(val)       (val)
0090
0091 #define REG11_SIG_GAIN(val)     (val)
0092 #define REG11_SIGC_CNTL         BIT(6)
0093 #define REG11_SIGC_POL          BIT(7)
0094
0095 #define REG12_COLOR(val)        (val)
0096 #define REG12_PWCKSEL(val)      ((val) << 6)
0097
0098 #define REG13_4096LEVEL_CNTL(val)   (val)
0099 #define REG13_SL4096(val)       ((val) << 4)
0100 #define REG13_LIMITER_CONTROL       BIT(7)
0101
0102 #define REG14_PANEL_TEST(val)       (val)
0103
0104 #define REG15_NVM_LINK0         BIT(0)
0105 #define REG15_NVM_LINK1         BIT(1)
0106 #define REG15_NVM_LINK2         BIT(2)
0107 #define REG15_NVM_LINK3         BIT(3)
0108 #define REG15_NVM_LINK4         BIT(4)
0109 #define REG15_NVM_LINK5         BIT(5)
0110 #define REG15_NVM_LINK6         BIT(6)
0111 #define REG15_NVM_LINK7         BIT(7)
0112
0113 struct y030xx067a_info {
0114     const struct drm_display_mode *display_modes;
0115     unsigned int num_modes;
0116     u16 width_mm, height_mm;
0117     u32 bus_format, bus_flags;
0118 };
0119
0120 struct y030xx067a {
0121     struct drm_panel panel;
0122     struct spi_device *spi;
0123     struct regmap *map;
0124
0125     const struct y030xx067a_info *panel_info;
0126
0127     struct regulator *supply;
0128     struct gpio_desc *reset_gpio;
0129 };
0130
0131 static inline struct y030xx067a *to_y030xx067a(struct drm_panel *panel)
0132 {
0133     return container_of(panel, struct y030xx067a, panel);
0134 }
0135
0136 static const struct reg_sequence y030xx067a_init_sequence[] = {
0137     { 0x00, REG00_VBRT_CTRL(0x7f) },
0138     { 0x01, REG01_COM_DC(0x3c) },
0139     { 0x02, REG02_VESA_SEL(0x3) | REG02_DA_CONTRAST(0x1f) },
0140     { 0x03, REG03_VPOSITION(0x0a) },
0141     { 0x04, REG04_HPOSITION1(0xd2) },
0142     { 0x05, REG05_CLIP | REG05_NVM_VREFRESH | REG05_SLBRCHARGE(0x2) },
0143     { 0x06, REG06_NT },
0144     { 0x07, 0 },
0145     { 0x08, REG08_PANEL(0x1) | REG08_CLOCK_DIV(0x2) },
0146     { 0x09, REG09_SUB_BRIGHT_R(0x20) },
0147     { 0x0a, REG0A_SUB_BRIGHT_B(0x20) },
0148     { 0x0b, REG0B_HD_FREERUN | REG0B_VD_FREERUN },
0149     { 0x0c, REG0C_CONTRAST_R(0x00) },
0150     { 0x0d, REG0D_CONTRAST_G(0x00) },
0151     { 0x0e, REG0E_CONTRAST_B(0x10) },
0152     { 0x0f, 0 },
0153     { 0x10, REG10_BRIGHT(0x7f) },
0154     { 0x11, REG11_SIGC_CNTL | REG11_SIG_GAIN(0x3f) },
0155     { 0x12, REG12_COLOR(0x20) | REG12_PWCKSEL(0x1) },
0156     { 0x13, REG13_4096LEVEL_CNTL(0x8) },
0157     { 0x14, 0 },
0158     { 0x15, 0 },
0159 };
0160
0161 static int y030xx067a_prepare(struct drm_panel *panel)
0162 {
0163     struct y030xx067a *priv = to_y030xx067a(panel);
0164     struct device *dev = &priv->spi->dev;
0165     int err;
0166
0167     err = regulator_enable(priv->supply);
0168     if (err) {
0169         dev_err(dev, "Failed to enable power supply: %d\n", err);
0170         return err;
0171     }
0172
0173     /* Reset the chip */
0174     gpiod_set_value_cansleep(priv->reset_gpio, 1);
0175     usleep_range(1000, 20000);
0176     gpiod_set_value_cansleep(priv->reset_gpio, 0);
0177     usleep_range(1000, 20000);
0178
0179     err = regmap_multi_reg_write(priv->map, y030xx067a_init_sequence,
0180                      ARRAY_SIZE(y030xx067a_init_sequence));
0181     if (err) {
0182         dev_err(dev, "Failed to init registers: %d\n", err);
0183         goto err_disable_regulator;
0184     }
0185
0186     return 0;
0187
0188 err_disable_regulator:
0189     regulator_disable(priv->supply);
0190     return err;
0191 }
0192
0193 static int y030xx067a_unprepare(struct drm_panel *panel)
0194 {
0195     struct y030xx067a *priv = to_y030xx067a(panel);
0196
0197     gpiod_set_value_cansleep(priv->reset_gpio, 1);
0198     regulator_disable(priv->supply);
0199
0200     return 0;
0201 }
0202
0203 static int y030xx067a_enable(struct drm_panel *panel)
0204 {
0205     struct y030xx067a *priv = to_y030xx067a(panel);
0206
0207     regmap_set_bits(priv->map, 0x06, REG06_XPSAVE);
0208
0209     if (panel->backlight) {
0210         /* Wait for the picture to be ready before enabling backlight */
0211         msleep(120);
0212     }
0213
0214     return 0;
0215 }
0216
0217 static int y030xx067a_disable(struct drm_panel *panel)
0218 {
0219     struct y030xx067a *priv = to_y030xx067a(panel);
0220
0221     regmap_clear_bits(priv->map, 0x06, REG06_XPSAVE);
0222
0223     return 0;
0224 }
0225
0226 static int y030xx067a_get_modes(struct drm_panel *panel,
0227                 struct drm_connector *connector)
0228 {
0229     struct y030xx067a *priv = to_y030xx067a(panel);
0230     const struct y030xx067a_info *panel_info = priv->panel_info;
0231     struct drm_display_mode *mode;
0232     unsigned int i;
0233
0234     for (i = 0; i < panel_info->num_modes; i++) {
0235         mode = drm_mode_duplicate(connector->dev,
0236                       &panel_info->display_modes[i]);
0237         if (!mode)
0238             return -ENOMEM;
0239
0240         drm_mode_set_name(mode);
0241
0242         mode->type = DRM_MODE_TYPE_DRIVER;
0243         if (panel_info->num_modes == 1)
0244             mode->type |= DRM_MODE_TYPE_PREFERRED;
0245
0246         drm_mode_probed_add(connector, mode);
0247     }
0248
0249     connector->display_info.bpc = 8;
0250     connector->display_info.width_mm = panel_info->width_mm;
0251     connector->display_info.height_mm = panel_info->height_mm;
0252
0253     drm_display_info_set_bus_formats(&connector->display_info,
0254                      &panel_info->bus_format, 1);
0255     connector->display_info.bus_flags = panel_info->bus_flags;
0256
0257     return panel_info->num_modes;
0258 }
0259
0260 static const struct drm_panel_funcs y030xx067a_funcs = {
0261     .prepare    = y030xx067a_prepare,
0262     .unprepare  = y030xx067a_unprepare,
0263     .enable     = y030xx067a_enable,
0264     .disable    = y030xx067a_disable,
0265     .get_modes  = y030xx067a_get_modes,
0266 };
0267
0268 static const struct regmap_config y030xx067a_regmap_config = {
0269     .reg_bits = 8,
0270     .val_bits = 8,
0271     .max_register = 0x15,
0272     .cache_type = REGCACHE_FLAT,
0273 };
0274
0275 static int y030xx067a_probe(struct spi_device *spi)
0276 {
0277     struct device *dev = &spi->dev;
0278     struct y030xx067a *priv;
0279     int err;
0280
0281     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0282     if (!priv)
0283         return -ENOMEM;
0284
0285     priv->spi = spi;
0286     spi_set_drvdata(spi, priv);
0287
0288     priv->map = devm_regmap_init_spi(spi, &y030xx067a_regmap_config);
0289     if (IS_ERR(priv->map)) {
0290         dev_err(dev, "Unable to init regmap\n");
0291         return PTR_ERR(priv->map);
0292     }
0293
0294     priv->panel_info = of_device_get_match_data(dev);
0295     if (!priv->panel_info)
0296         return -EINVAL;
0297
0298     priv->supply = devm_regulator_get(dev, "power");
0299     if (IS_ERR(priv->supply))
0300         return dev_err_probe(dev, PTR_ERR(priv->supply),
0301                      "Failed to get power supply\n");
0302
0303     priv->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
0304     if (IS_ERR(priv->reset_gpio))
0305         return dev_err_probe(dev, PTR_ERR(priv->reset_gpio),
0306                      "Failed to get reset GPIO\n");
0307
0308     drm_panel_init(&priv->panel, dev, &y030xx067a_funcs,
0309                DRM_MODE_CONNECTOR_DPI);
0310
0311     err = drm_panel_of_backlight(&priv->panel);
0312     if (err)
0313         return err;
0314
0315     drm_panel_add(&priv->panel);
0316
0317     return 0;
0318 }
0319
0320 static void y030xx067a_remove(struct spi_device *spi)
0321 {
0322     struct y030xx067a *priv = spi_get_drvdata(spi);
0323
0324     drm_panel_remove(&priv->panel);
0325     drm_panel_disable(&priv->panel);
0326     drm_panel_unprepare(&priv->panel);
0327 }
0328
0329 static const struct drm_display_mode y030xx067a_modes[] = {
0330     { /* 60 Hz */
0331         .clock = 14400,
0332         .hdisplay = 320,
0333         .hsync_start = 320 + 10,
0334         .hsync_end = 320 + 10 + 37,
0335         .htotal = 320 + 10 + 37 + 33,
0336         .vdisplay = 480,
0337         .vsync_start = 480 + 84,
0338         .vsync_end = 480 + 84 + 20,
0339         .vtotal = 480 + 84 + 20 + 16,
0340         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
0341     },
0342     { /* 50 Hz */
0343         .clock = 12000,
0344         .hdisplay = 320,
0345         .hsync_start = 320 + 10,
0346         .hsync_end = 320 + 10 + 37,
0347         .htotal = 320 + 10 + 37 + 33,
0348         .vdisplay = 480,
0349         .vsync_start = 480 + 84,
0350         .vsync_end = 480 + 84 + 20,
0351         .vtotal = 480 + 84 + 20 + 16,
0352         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
0353     },
0354 };
0355
0356 static const struct y030xx067a_info y030xx067a_info = {
0357     .display_modes = y030xx067a_modes,
0358     .num_modes = ARRAY_SIZE(y030xx067a_modes),
0359     .width_mm = 69,
0360     .height_mm = 51,
0361     .bus_format = MEDIA_BUS_FMT_RGB888_3X8_DELTA,
0362     .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | DRM_BUS_FLAG_DE_LOW,
0363 };
0364
0365 static const struct of_device_id y030xx067a_of_match[] = {
0366     { .compatible = "abt,y030xx067a", .data = &y030xx067a_info },
0367     { /* sentinel */ }
0368 };
0369 MODULE_DEVICE_TABLE(of, y030xx067a_of_match);
0370
0371 static struct spi_driver y030xx067a_driver = {
0372     .driver = {
0373         .name = "abt-y030xx067a",
0374         .of_match_table = y030xx067a_of_match,
0375     },
0376     .probe = y030xx067a_probe,
0377     .remove = y030xx067a_remove,
0378 };
0379 module_spi_driver(y030xx067a_driver);
0380
0381 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
0382 MODULE_AUTHOR("Christophe Branchereau <cbranchereau@gmail.com>");
0383 MODULE_LICENSE("GPL v2");