drm/omapdrm/omap_dmm_priv.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
0004  * Author: Rob Clark <rob@ti.com>
0005  *         Andy Gross <andy.gross@ti.com>
0006  */
0007
0008 #ifndef OMAP_DMM_PRIV_H
0009 #define OMAP_DMM_PRIV_H
0010
0011 #define DMM_REVISION          0x000
0012 #define DMM_HWINFO            0x004
0013 #define DMM_LISA_HWINFO       0x008
0014 #define DMM_DMM_SYSCONFIG     0x010
0015 #define DMM_LISA_LOCK         0x01C
0016 #define DMM_LISA_MAP__0       0x040
0017 #define DMM_LISA_MAP__1       0x044
0018 #define DMM_TILER_HWINFO      0x208
0019 #define DMM_TILER_OR__0       0x220
0020 #define DMM_TILER_OR__1       0x224
0021 #define DMM_PAT_HWINFO        0x408
0022 #define DMM_PAT_GEOMETRY      0x40C
0023 #define DMM_PAT_CONFIG        0x410
0024 #define DMM_PAT_VIEW__0       0x420
0025 #define DMM_PAT_VIEW__1       0x424
0026 #define DMM_PAT_VIEW_MAP__0   0x440
0027 #define DMM_PAT_VIEW_MAP_BASE 0x460
0028 #define DMM_PAT_IRQ_EOI       0x478
0029 #define DMM_PAT_IRQSTATUS_RAW 0x480
0030 #define DMM_PAT_IRQSTATUS     0x490
0031 #define DMM_PAT_IRQENABLE_SET 0x4A0
0032 #define DMM_PAT_IRQENABLE_CLR 0x4B0
0033 #define DMM_PAT_STATUS__0     0x4C0
0034 #define DMM_PAT_STATUS__1     0x4C4
0035 #define DMM_PAT_STATUS__2     0x4C8
0036 #define DMM_PAT_STATUS__3     0x4CC
0037 #define DMM_PAT_DESCR__0      0x500
0038 #define DMM_PAT_DESCR__1      0x510
0039 #define DMM_PAT_DESCR__2      0x520
0040 #define DMM_PAT_DESCR__3      0x530
0041 #define DMM_PEG_HWINFO        0x608
0042 #define DMM_PEG_PRIO          0x620
0043 #define DMM_PEG_PRIO_PAT      0x640
0044
0045 #define DMM_IRQSTAT_DST         (1<<0)
0046 #define DMM_IRQSTAT_LST         (1<<1)
0047 #define DMM_IRQSTAT_ERR_INV_DSC     (1<<2)
0048 #define DMM_IRQSTAT_ERR_INV_DATA    (1<<3)
0049 #define DMM_IRQSTAT_ERR_UPD_AREA    (1<<4)
0050 #define DMM_IRQSTAT_ERR_UPD_CTRL    (1<<5)
0051 #define DMM_IRQSTAT_ERR_UPD_DATA    (1<<6)
0052 #define DMM_IRQSTAT_ERR_LUT_MISS    (1<<7)
0053
0054 #define DMM_IRQSTAT_ERR_MASK    (DMM_IRQSTAT_ERR_INV_DSC | \
0055                 DMM_IRQSTAT_ERR_INV_DATA | \
0056                 DMM_IRQSTAT_ERR_UPD_AREA | \
0057                 DMM_IRQSTAT_ERR_UPD_CTRL | \
0058                 DMM_IRQSTAT_ERR_UPD_DATA | \
0059                 DMM_IRQSTAT_ERR_LUT_MISS)
0060
0061 #define DMM_PATSTATUS_READY     (1<<0)
0062 #define DMM_PATSTATUS_VALID     (1<<1)
0063 #define DMM_PATSTATUS_RUN       (1<<2)
0064 #define DMM_PATSTATUS_DONE      (1<<3)
0065 #define DMM_PATSTATUS_LINKED        (1<<4)
0066 #define DMM_PATSTATUS_BYPASSED      (1<<7)
0067 #define DMM_PATSTATUS_ERR_INV_DESCR (1<<10)
0068 #define DMM_PATSTATUS_ERR_INV_DATA  (1<<11)
0069 #define DMM_PATSTATUS_ERR_UPD_AREA  (1<<12)
0070 #define DMM_PATSTATUS_ERR_UPD_CTRL  (1<<13)
0071 #define DMM_PATSTATUS_ERR_UPD_DATA  (1<<14)
0072 #define DMM_PATSTATUS_ERR_ACCESS    (1<<15)
0073
0074 /* note: don't treat DMM_PATSTATUS_ERR_ACCESS as an error */
0075 #define DMM_PATSTATUS_ERR   (DMM_PATSTATUS_ERR_INV_DESCR | \
0076                 DMM_PATSTATUS_ERR_INV_DATA | \
0077                 DMM_PATSTATUS_ERR_UPD_AREA | \
0078                 DMM_PATSTATUS_ERR_UPD_CTRL | \
0079                 DMM_PATSTATUS_ERR_UPD_DATA)
0080
0081
0082
0083 enum {
0084     PAT_STATUS,
0085     PAT_DESCR
0086 };
0087
0088 struct pat_ctrl {
0089     u32 start:4;
0090     u32 dir:4;
0091     u32 lut_id:8;
0092     u32 sync:12;
0093     u32 ini:4;
0094 };
0095
0096 struct pat {
0097     u32 next_pa;
0098     struct pat_area area;
0099     struct pat_ctrl ctrl;
0100     u32 data_pa;
0101 };
0102
0103 #define DMM_FIXED_RETRY_COUNT 1000
0104
0105 /* create refill buffer big enough to refill all slots, plus 3 descriptors..
0106  * 3 descriptors is probably the worst-case for # of 2d-slices in a 1d area,
0107  * but I guess you don't hit that worst case at the same time as full area
0108  * refill
0109  */
0110 #define DESCR_SIZE 128
0111 #define REFILL_BUFFER_SIZE ((4 * 128 * 256) + (3 * DESCR_SIZE))
0112
0113 /* For OMAP5, a fixed offset is added to all Y coordinates for 1D buffers.
0114  * This is used in programming to address the upper portion of the LUT
0115 */
0116 #define OMAP5_LUT_OFFSET       128
0117
0118 struct dmm;
0119
0120 struct dmm_txn {
0121     void *engine_handle;
0122     struct tcm *tcm;
0123
0124     u8 *current_va;
0125     dma_addr_t current_pa;
0126
0127     struct pat *last_pat;
0128 };
0129
0130 struct refill_engine {
0131     int id;
0132     struct dmm *dmm;
0133     struct tcm *tcm;
0134
0135     u8 *refill_va;
0136     dma_addr_t refill_pa;
0137
0138     /* only one trans per engine for now */
0139     struct dmm_txn txn;
0140
0141     bool async;
0142
0143     struct completion compl;
0144
0145     struct list_head idle_node;
0146 };
0147
0148 struct dmm_platform_data {
0149     u32 cpu_cache_flags;
0150 };
0151
0152 struct dmm {
0153     struct device *dev;
0154     dma_addr_t phys_base;
0155     void __iomem *base;
0156     int irq;
0157
0158     struct page *dummy_page;
0159     dma_addr_t dummy_pa;
0160
0161     void *refill_va;
0162     dma_addr_t refill_pa;
0163
0164     /* refill engines */
0165     wait_queue_head_t engine_queue;
0166     struct list_head idle_head;
0167     struct refill_engine *engines;
0168     int num_engines;
0169     atomic_t engine_counter;
0170
0171     /* container information */
0172     int container_width;
0173     int container_height;
0174     int lut_width;
0175     int lut_height;
0176     int num_lut;
0177
0178     /* array of LUT - TCM containers */
0179     struct tcm **tcm;
0180
0181     /* allocation list and lock */
0182     struct list_head alloc_head;
0183
0184     const struct dmm_platform_data *plat_data;
0185
0186     bool dmm_workaround;
0187     spinlock_t wa_lock;
0188     u32 *wa_dma_data;
0189     dma_addr_t wa_dma_handle;
0190     struct dma_chan *wa_dma_chan;
0191 };
0192
0193 #endif