drm/omapdrm/omap_crtc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
0004  * Author: Rob Clark <rob@ti.com>
0005  */
0006
0007 #include <linux/math64.h>
0008
0009 #include <drm/drm_atomic.h>
0010 #include <drm/drm_atomic_helper.h>
0011 #include <drm/drm_crtc.h>
0012 #include <drm/drm_mode.h>
0013 #include <drm/drm_plane_helper.h>
0014 #include <drm/drm_vblank.h>
0015
0016 #include "omap_drv.h"
0017
0018 #define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base)
0019
0020 struct omap_crtc_state {
0021     /* Must be first. */
0022     struct drm_crtc_state base;
0023     /* Shadow values for legacy userspace support. */
0024     unsigned int rotation;
0025     unsigned int zpos;
0026     bool manually_updated;
0027 };
0028
0029 #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
0030
0031 struct omap_crtc {
0032     struct drm_crtc base;
0033
0034     const char *name;
0035     struct omap_drm_pipeline *pipe;
0036     enum omap_channel channel;
0037
0038     struct videomode vm;
0039
0040     bool ignore_digit_sync_lost;
0041
0042     bool enabled;
0043     bool pending;
0044     wait_queue_head_t pending_wait;
0045     struct drm_pending_vblank_event *event;
0046     struct delayed_work update_work;
0047
0048     void (*framedone_handler)(void *);
0049     void *framedone_handler_data;
0050 };
0051
0052 /* -----------------------------------------------------------------------------
0053  * Helper Functions
0054  */
0055
0056 struct videomode *omap_crtc_timings(struct drm_crtc *crtc)
0057 {
0058     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0059     return &omap_crtc->vm;
0060 }
0061
0062 enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
0063 {
0064     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0065     return omap_crtc->channel;
0066 }
0067
0068 static bool omap_crtc_is_pending(struct drm_crtc *crtc)
0069 {
0070     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0071     unsigned long flags;
0072     bool pending;
0073
0074     spin_lock_irqsave(&crtc->dev->event_lock, flags);
0075     pending = omap_crtc->pending;
0076     spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
0077
0078     return pending;
0079 }
0080
0081 int omap_crtc_wait_pending(struct drm_crtc *crtc)
0082 {
0083     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0084
0085     /*
0086      * Timeout is set to a "sufficiently" high value, which should cover
0087      * a single frame refresh even on slower displays.
0088      */
0089     return wait_event_timeout(omap_crtc->pending_wait,
0090                   !omap_crtc_is_pending(crtc),
0091                   msecs_to_jiffies(250));
0092 }
0093
0094 /* -----------------------------------------------------------------------------
0095  * DSS Manager Functions
0096  */
0097
0098 /*
0099  * Manager-ops, callbacks from output when they need to configure
0100  * the upstream part of the video pipe.
0101  */
0102
0103 void omap_crtc_dss_start_update(struct omap_drm_private *priv,
0104                        enum omap_channel channel)
0105 {
0106     dispc_mgr_enable(priv->dispc, channel, true);
0107 }
0108
0109 /* Called only from the encoder enable/disable and suspend/resume handlers. */
0110 void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
0111 {
0112     struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
0113     struct drm_device *dev = crtc->dev;
0114     struct omap_drm_private *priv = dev->dev_private;
0115     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0116     enum omap_channel channel = omap_crtc->channel;
0117     struct omap_irq_wait *wait;
0118     u32 framedone_irq, vsync_irq;
0119     int ret;
0120
0121     if (WARN_ON(omap_crtc->enabled == enable))
0122         return;
0123
0124     if (omap_state->manually_updated) {
0125         omap_irq_enable_framedone(crtc, enable);
0126         omap_crtc->enabled = enable;
0127         return;
0128     }
0129
0130     if (omap_crtc->pipe->output->type == OMAP_DISPLAY_TYPE_HDMI) {
0131         dispc_mgr_enable(priv->dispc, channel, enable);
0132         omap_crtc->enabled = enable;
0133         return;
0134     }
0135
0136     if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
0137         /*
0138          * Digit output produces some sync lost interrupts during the
0139          * first frame when enabling, so we need to ignore those.
0140          */
0141         omap_crtc->ignore_digit_sync_lost = true;
0142     }
0143
0144     framedone_irq = dispc_mgr_get_framedone_irq(priv->dispc,
0145                                    channel);
0146     vsync_irq = dispc_mgr_get_vsync_irq(priv->dispc, channel);
0147
0148     if (enable) {
0149         wait = omap_irq_wait_init(dev, vsync_irq, 1);
0150     } else {
0151         /*
0152          * When we disable the digit output, we need to wait for
0153          * FRAMEDONE to know that DISPC has finished with the output.
0154          *
0155          * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
0156          * that case we need to use vsync interrupt, and wait for both
0157          * even and odd frames.
0158          */
0159
0160         if (framedone_irq)
0161             wait = omap_irq_wait_init(dev, framedone_irq, 1);
0162         else
0163             wait = omap_irq_wait_init(dev, vsync_irq, 2);
0164     }
0165
0166     dispc_mgr_enable(priv->dispc, channel, enable);
0167     omap_crtc->enabled = enable;
0168
0169     ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
0170     if (ret) {
0171         dev_err(dev->dev, "%s: timeout waiting for %s\n",
0172                 omap_crtc->name, enable ? "enable" : "disable");
0173     }
0174
0175     if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
0176         omap_crtc->ignore_digit_sync_lost = false;
0177         /* make sure the irq handler sees the value above */
0178         mb();
0179     }
0180 }
0181
0182
0183 int omap_crtc_dss_enable(struct omap_drm_private *priv, enum omap_channel channel)
0184 {
0185     struct drm_crtc *crtc = priv->channels[channel]->crtc;
0186     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0187
0188     dispc_mgr_set_timings(priv->dispc, omap_crtc->channel,
0189                      &omap_crtc->vm);
0190     omap_crtc_set_enabled(&omap_crtc->base, true);
0191
0192     return 0;
0193 }
0194
0195 void omap_crtc_dss_disable(struct omap_drm_private *priv, enum omap_channel channel)
0196 {
0197     struct drm_crtc *crtc = priv->channels[channel]->crtc;
0198     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0199
0200     omap_crtc_set_enabled(&omap_crtc->base, false);
0201 }
0202
0203 void omap_crtc_dss_set_timings(struct omap_drm_private *priv,
0204         enum omap_channel channel,
0205         const struct videomode *vm)
0206 {
0207     struct drm_crtc *crtc = priv->channels[channel]->crtc;
0208     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0209
0210     DBG("%s", omap_crtc->name);
0211     omap_crtc->vm = *vm;
0212 }
0213
0214 void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv,
0215         enum omap_channel channel,
0216         const struct dss_lcd_mgr_config *config)
0217 {
0218     struct drm_crtc *crtc = priv->channels[channel]->crtc;
0219     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0220
0221     DBG("%s", omap_crtc->name);
0222     dispc_mgr_set_lcd_config(priv->dispc, omap_crtc->channel,
0223                         config);
0224 }
0225
0226 int omap_crtc_dss_register_framedone(
0227         struct omap_drm_private *priv, enum omap_channel channel,
0228         void (*handler)(void *), void *data)
0229 {
0230     struct drm_crtc *crtc = priv->channels[channel]->crtc;
0231     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0232     struct drm_device *dev = omap_crtc->base.dev;
0233
0234     if (omap_crtc->framedone_handler)
0235         return -EBUSY;
0236
0237     dev_dbg(dev->dev, "register framedone %s", omap_crtc->name);
0238
0239     omap_crtc->framedone_handler = handler;
0240     omap_crtc->framedone_handler_data = data;
0241
0242     return 0;
0243 }
0244
0245 void omap_crtc_dss_unregister_framedone(
0246         struct omap_drm_private *priv, enum omap_channel channel,
0247         void (*handler)(void *), void *data)
0248 {
0249     struct drm_crtc *crtc = priv->channels[channel]->crtc;
0250     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0251     struct drm_device *dev = omap_crtc->base.dev;
0252
0253     dev_dbg(dev->dev, "unregister framedone %s", omap_crtc->name);
0254
0255     WARN_ON(omap_crtc->framedone_handler != handler);
0256     WARN_ON(omap_crtc->framedone_handler_data != data);
0257
0258     omap_crtc->framedone_handler = NULL;
0259     omap_crtc->framedone_handler_data = NULL;
0260 }
0261
0262 /* -----------------------------------------------------------------------------
0263  * Setup, Flush and Page Flip
0264  */
0265
0266 void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus)
0267 {
0268     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0269
0270     if (omap_crtc->ignore_digit_sync_lost) {
0271         irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
0272         if (!irqstatus)
0273             return;
0274     }
0275
0276     DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
0277 }
0278
0279 void omap_crtc_vblank_irq(struct drm_crtc *crtc)
0280 {
0281     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0282     struct drm_device *dev = omap_crtc->base.dev;
0283     struct omap_drm_private *priv = dev->dev_private;
0284     bool pending;
0285
0286     spin_lock(&crtc->dev->event_lock);
0287     /*
0288      * If the dispc is busy we're racing the flush operation. Try again on
0289      * the next vblank interrupt.
0290      */
0291     if (dispc_mgr_go_busy(priv->dispc, omap_crtc->channel)) {
0292         spin_unlock(&crtc->dev->event_lock);
0293         return;
0294     }
0295
0296     /* Send the vblank event if one has been requested. */
0297     if (omap_crtc->event) {
0298         drm_crtc_send_vblank_event(crtc, omap_crtc->event);
0299         omap_crtc->event = NULL;
0300     }
0301
0302     pending = omap_crtc->pending;
0303     omap_crtc->pending = false;
0304     spin_unlock(&crtc->dev->event_lock);
0305
0306     if (pending)
0307         drm_crtc_vblank_put(crtc);
0308
0309     /* Wake up omap_atomic_complete. */
0310     wake_up(&omap_crtc->pending_wait);
0311
0312     DBG("%s: apply done", omap_crtc->name);
0313 }
0314
0315 void omap_crtc_framedone_irq(struct drm_crtc *crtc, uint32_t irqstatus)
0316 {
0317     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0318
0319     if (!omap_crtc->framedone_handler)
0320         return;
0321
0322     omap_crtc->framedone_handler(omap_crtc->framedone_handler_data);
0323
0324     spin_lock(&crtc->dev->event_lock);
0325     /* Send the vblank event if one has been requested. */
0326     if (omap_crtc->event) {
0327         drm_crtc_send_vblank_event(crtc, omap_crtc->event);
0328         omap_crtc->event = NULL;
0329     }
0330     omap_crtc->pending = false;
0331     spin_unlock(&crtc->dev->event_lock);
0332
0333     /* Wake up omap_atomic_complete. */
0334     wake_up(&omap_crtc->pending_wait);
0335 }
0336
0337 void omap_crtc_flush(struct drm_crtc *crtc)
0338 {
0339     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0340     struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
0341
0342     if (!omap_state->manually_updated)
0343         return;
0344
0345     if (!delayed_work_pending(&omap_crtc->update_work))
0346         schedule_delayed_work(&omap_crtc->update_work, 0);
0347 }
0348
0349 static void omap_crtc_manual_display_update(struct work_struct *data)
0350 {
0351     struct omap_crtc *omap_crtc =
0352             container_of(data, struct omap_crtc, update_work.work);
0353     struct omap_dss_device *dssdev = omap_crtc->pipe->output;
0354     struct drm_device *dev = omap_crtc->base.dev;
0355     int ret;
0356
0357     if (!dssdev || !dssdev->dsi_ops || !dssdev->dsi_ops->update)
0358         return;
0359
0360     ret = dssdev->dsi_ops->update(dssdev);
0361     if (ret < 0) {
0362         spin_lock_irq(&dev->event_lock);
0363         omap_crtc->pending = false;
0364         spin_unlock_irq(&dev->event_lock);
0365         wake_up(&omap_crtc->pending_wait);
0366     }
0367 }
0368
0369 static s16 omap_crtc_s31_32_to_s2_8(s64 coef)
0370 {
0371     u64 sign_bit = 1ULL << 63;
0372     u64 cbits = (u64)coef;
0373
0374     s16 ret = clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x1ff);
0375
0376     if (cbits & sign_bit)
0377         ret = -ret;
0378
0379     return ret;
0380 }
0381
0382 static void omap_crtc_cpr_coefs_from_ctm(const struct drm_color_ctm *ctm,
0383                      struct omap_dss_cpr_coefs *cpr)
0384 {
0385     cpr->rr = omap_crtc_s31_32_to_s2_8(ctm->matrix[0]);
0386     cpr->rg = omap_crtc_s31_32_to_s2_8(ctm->matrix[1]);
0387     cpr->rb = omap_crtc_s31_32_to_s2_8(ctm->matrix[2]);
0388     cpr->gr = omap_crtc_s31_32_to_s2_8(ctm->matrix[3]);
0389     cpr->gg = omap_crtc_s31_32_to_s2_8(ctm->matrix[4]);
0390     cpr->gb = omap_crtc_s31_32_to_s2_8(ctm->matrix[5]);
0391     cpr->br = omap_crtc_s31_32_to_s2_8(ctm->matrix[6]);
0392     cpr->bg = omap_crtc_s31_32_to_s2_8(ctm->matrix[7]);
0393     cpr->bb = omap_crtc_s31_32_to_s2_8(ctm->matrix[8]);
0394 }
0395
0396 static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc)
0397 {
0398     struct omap_drm_private *priv = crtc->dev->dev_private;
0399     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0400     struct omap_overlay_manager_info info;
0401
0402     memset(&info, 0, sizeof(info));
0403
0404     info.default_color = 0x000000;
0405     info.trans_enabled = false;
0406     info.partial_alpha_enabled = false;
0407
0408     if (crtc->state->ctm) {
0409         struct drm_color_ctm *ctm = crtc->state->ctm->data;
0410
0411         info.cpr_enable = true;
0412         omap_crtc_cpr_coefs_from_ctm(ctm, &info.cpr_coefs);
0413     } else {
0414         info.cpr_enable = false;
0415     }
0416
0417     dispc_mgr_setup(priv->dispc, omap_crtc->channel, &info);
0418 }
0419
0420 /* -----------------------------------------------------------------------------
0421  * CRTC Functions
0422  */
0423
0424 static void omap_crtc_destroy(struct drm_crtc *crtc)
0425 {
0426     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0427
0428     DBG("%s", omap_crtc->name);
0429
0430     drm_crtc_cleanup(crtc);
0431
0432     kfree(omap_crtc);
0433 }
0434
0435 static void omap_crtc_arm_event(struct drm_crtc *crtc)
0436 {
0437     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0438
0439     WARN_ON(omap_crtc->pending);
0440     omap_crtc->pending = true;
0441
0442     if (crtc->state->event) {
0443         omap_crtc->event = crtc->state->event;
0444         crtc->state->event = NULL;
0445     }
0446 }
0447
0448 static void omap_crtc_atomic_enable(struct drm_crtc *crtc,
0449                     struct drm_atomic_state *state)
0450 {
0451     struct omap_drm_private *priv = crtc->dev->dev_private;
0452     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0453     struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
0454     int ret;
0455
0456     DBG("%s", omap_crtc->name);
0457
0458     dispc_runtime_get(priv->dispc);
0459
0460     /* manual updated display will not trigger vsync irq */
0461     if (omap_state->manually_updated)
0462         return;
0463
0464     drm_crtc_vblank_on(crtc);
0465
0466     ret = drm_crtc_vblank_get(crtc);
0467     WARN_ON(ret != 0);
0468
0469     spin_lock_irq(&crtc->dev->event_lock);
0470     omap_crtc_arm_event(crtc);
0471     spin_unlock_irq(&crtc->dev->event_lock);
0472 }
0473
0474 static void omap_crtc_atomic_disable(struct drm_crtc *crtc,
0475                      struct drm_atomic_state *state)
0476 {
0477     struct omap_drm_private *priv = crtc->dev->dev_private;
0478     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0479     struct drm_device *dev = crtc->dev;
0480
0481     DBG("%s", omap_crtc->name);
0482
0483     spin_lock_irq(&crtc->dev->event_lock);
0484     if (crtc->state->event) {
0485         drm_crtc_send_vblank_event(crtc, crtc->state->event);
0486         crtc->state->event = NULL;
0487     }
0488     spin_unlock_irq(&crtc->dev->event_lock);
0489
0490     cancel_delayed_work(&omap_crtc->update_work);
0491
0492     if (!omap_crtc_wait_pending(crtc))
0493         dev_warn(dev->dev, "manual display update did not finish!");
0494
0495     drm_crtc_vblank_off(crtc);
0496
0497     dispc_runtime_put(priv->dispc);
0498 }
0499
0500 static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc,
0501                     const struct drm_display_mode *mode)
0502 {
0503     struct omap_drm_private *priv = crtc->dev->dev_private;
0504     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0505     struct videomode vm = {0};
0506     int r;
0507
0508     drm_display_mode_to_videomode(mode, &vm);
0509
0510     /*
0511      * DSI might not call this, since the supplied mode is not a
0512      * valid DISPC mode. DSI will calculate and configure the
0513      * proper DISPC mode later.
0514      */
0515     if (omap_crtc->pipe->output->type != OMAP_DISPLAY_TYPE_DSI) {
0516         r = dispc_mgr_check_timings(priv->dispc,
0517                                omap_crtc->channel,
0518                                &vm);
0519         if (r)
0520             return r;
0521     }
0522
0523     /* Check for bandwidth limit */
0524     if (priv->max_bandwidth) {
0525         /*
0526          * Estimation for the bandwidth need of a given mode with one
0527          * full screen plane:
0528          * bandwidth = resolution * 32bpp * (pclk / (vtotal * htotal))
0529          *                  ^^ Refresh rate ^^
0530          *
0531          * The interlaced mode is taken into account by using the
0532          * pixelclock in the calculation.
0533          *
0534          * The equation is rearranged for 64bit arithmetic.
0535          */
0536         uint64_t bandwidth = mode->clock * 1000;
0537         unsigned int bpp = 4;
0538
0539         bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp;
0540         bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal);
0541
0542         /*
0543          * Reject modes which would need more bandwidth if used with one
0544          * full resolution plane (most common use case).
0545          */
0546         if (priv->max_bandwidth < bandwidth)
0547             return MODE_BAD;
0548     }
0549
0550     return MODE_OK;
0551 }
0552
0553 static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
0554 {
0555     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0556     struct drm_display_mode *mode = &crtc->state->adjusted_mode;
0557
0558     DBG("%s: set mode: " DRM_MODE_FMT,
0559         omap_crtc->name, DRM_MODE_ARG(mode));
0560
0561     drm_display_mode_to_videomode(mode, &omap_crtc->vm);
0562 }
0563
0564 static bool omap_crtc_is_manually_updated(struct drm_crtc *crtc)
0565 {
0566     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0567     struct omap_dss_device *dssdev = omap_crtc->pipe->output;
0568
0569     if (!dssdev || !dssdev->dsi_ops || !dssdev->dsi_ops->is_video_mode)
0570         return false;
0571
0572     if (dssdev->dsi_ops->is_video_mode(dssdev))
0573         return false;
0574
0575     DBG("detected manually updated display!");
0576     return true;
0577 }
0578
0579 static int omap_crtc_atomic_check(struct drm_crtc *crtc,
0580                 struct drm_atomic_state *state)
0581 {
0582     struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
0583                                       crtc);
0584     struct drm_plane_state *pri_state;
0585
0586     if (crtc_state->color_mgmt_changed && crtc_state->degamma_lut) {
0587         unsigned int length = crtc_state->degamma_lut->length /
0588             sizeof(struct drm_color_lut);
0589
0590         if (length < 2)
0591             return -EINVAL;
0592     }
0593
0594     pri_state = drm_atomic_get_new_plane_state(state,
0595                            crtc->primary);
0596     if (pri_state) {
0597         struct omap_crtc_state *omap_crtc_state =
0598             to_omap_crtc_state(crtc_state);
0599
0600         /* Mirror new values for zpos and rotation in omap_crtc_state */
0601         omap_crtc_state->zpos = pri_state->zpos;
0602         omap_crtc_state->rotation = pri_state->rotation;
0603
0604         /* Check if this CRTC is for a manually updated display */
0605         omap_crtc_state->manually_updated = omap_crtc_is_manually_updated(crtc);
0606     }
0607
0608     return 0;
0609 }
0610
0611 static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
0612                    struct drm_atomic_state *state)
0613 {
0614 }
0615
0616 static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
0617                    struct drm_atomic_state *state)
0618 {
0619     struct omap_drm_private *priv = crtc->dev->dev_private;
0620     struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
0621     struct omap_crtc_state *omap_crtc_state = to_omap_crtc_state(crtc->state);
0622     int ret;
0623
0624     if (crtc->state->color_mgmt_changed) {
0625         struct drm_color_lut *lut = NULL;
0626         unsigned int length = 0;
0627
0628         if (crtc->state->degamma_lut) {
0629             lut = (struct drm_color_lut *)
0630                 crtc->state->degamma_lut->data;
0631             length = crtc->state->degamma_lut->length /
0632                 sizeof(*lut);
0633         }
0634         dispc_mgr_set_gamma(priv->dispc, omap_crtc->channel,
0635                            lut, length);
0636     }
0637
0638     omap_crtc_write_crtc_properties(crtc);
0639
0640     /* Only flush the CRTC if it is currently enabled. */
0641     if (!omap_crtc->enabled)
0642         return;
0643
0644     DBG("%s: GO", omap_crtc->name);
0645
0646     if (omap_crtc_state->manually_updated) {
0647         /* send new image for page flips and modeset changes */
0648         spin_lock_irq(&crtc->dev->event_lock);
0649         omap_crtc_flush(crtc);
0650         omap_crtc_arm_event(crtc);
0651         spin_unlock_irq(&crtc->dev->event_lock);
0652         return;
0653     }
0654
0655     ret = drm_crtc_vblank_get(crtc);
0656     WARN_ON(ret != 0);
0657
0658     spin_lock_irq(&crtc->dev->event_lock);
0659     dispc_mgr_go(priv->dispc, omap_crtc->channel);
0660     omap_crtc_arm_event(crtc);
0661     spin_unlock_irq(&crtc->dev->event_lock);
0662 }
0663
0664 static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
0665                      struct drm_crtc_state *state,
0666                      struct drm_property *property,
0667                      u64 val)
0668 {
0669     struct omap_drm_private *priv = crtc->dev->dev_private;
0670     struct drm_plane_state *plane_state;
0671
0672     /*
0673      * Delegate property set to the primary plane. Get the plane state and
0674      * set the property directly, the shadow copy will be assigned in the
0675      * omap_crtc_atomic_check callback. This way updates to plane state will
0676      * always be mirrored in the crtc state correctly.
0677      */
0678     plane_state = drm_atomic_get_plane_state(state->state, crtc->primary);
0679     if (IS_ERR(plane_state))
0680         return PTR_ERR(plane_state);
0681
0682     if (property == crtc->primary->rotation_property)
0683         plane_state->rotation = val;
0684     else if (property == priv->zorder_prop)
0685         plane_state->zpos = val;
0686     else
0687         return -EINVAL;
0688
0689     return 0;
0690 }
0691
0692 static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
0693                      const struct drm_crtc_state *state,
0694                      struct drm_property *property,
0695                      u64 *val)
0696 {
0697     struct omap_drm_private *priv = crtc->dev->dev_private;
0698     struct omap_crtc_state *omap_state = to_omap_crtc_state(state);
0699
0700     if (property == crtc->primary->rotation_property)
0701         *val = omap_state->rotation;
0702     else if (property == priv->zorder_prop)
0703         *val = omap_state->zpos;
0704     else
0705         return -EINVAL;
0706
0707     return 0;
0708 }
0709
0710 static void omap_crtc_reset(struct drm_crtc *crtc)
0711 {
0712     struct omap_crtc_state *state;
0713
0714     if (crtc->state)
0715         __drm_atomic_helper_crtc_destroy_state(crtc->state);
0716
0717     kfree(crtc->state);
0718
0719     state = kzalloc(sizeof(*state), GFP_KERNEL);
0720     if (state)
0721         __drm_atomic_helper_crtc_reset(crtc, &state->base);
0722 }
0723
0724 static struct drm_crtc_state *
0725 omap_crtc_duplicate_state(struct drm_crtc *crtc)
0726 {
0727     struct omap_crtc_state *state, *current_state;
0728
0729     if (WARN_ON(!crtc->state))
0730         return NULL;
0731
0732     current_state = to_omap_crtc_state(crtc->state);
0733
0734     state = kmalloc(sizeof(*state), GFP_KERNEL);
0735     if (!state)
0736         return NULL;
0737
0738     __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
0739
0740     state->zpos = current_state->zpos;
0741     state->rotation = current_state->rotation;
0742     state->manually_updated = current_state->manually_updated;
0743
0744     return &state->base;
0745 }
0746
0747 static const struct drm_crtc_funcs omap_crtc_funcs = {
0748     .reset = omap_crtc_reset,
0749     .set_config = drm_atomic_helper_set_config,
0750     .destroy = omap_crtc_destroy,
0751     .page_flip = drm_atomic_helper_page_flip,
0752     .atomic_duplicate_state = omap_crtc_duplicate_state,
0753     .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
0754     .atomic_set_property = omap_crtc_atomic_set_property,
0755     .atomic_get_property = omap_crtc_atomic_get_property,
0756     .enable_vblank = omap_irq_enable_vblank,
0757     .disable_vblank = omap_irq_disable_vblank,
0758 };
0759
0760 static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
0761     .mode_set_nofb = omap_crtc_mode_set_nofb,
0762     .atomic_check = omap_crtc_atomic_check,
0763     .atomic_begin = omap_crtc_atomic_begin,
0764     .atomic_flush = omap_crtc_atomic_flush,
0765     .atomic_enable = omap_crtc_atomic_enable,
0766     .atomic_disable = omap_crtc_atomic_disable,
0767     .mode_valid = omap_crtc_mode_valid,
0768 };
0769
0770 /* -----------------------------------------------------------------------------
0771  * Init and Cleanup
0772  */
0773
0774 static const char *channel_names[] = {
0775     [OMAP_DSS_CHANNEL_LCD] = "lcd",
0776     [OMAP_DSS_CHANNEL_DIGIT] = "tv",
0777     [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
0778     [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
0779 };
0780
0781 /* initialize crtc */
0782 struct drm_crtc *omap_crtc_init(struct drm_device *dev,
0783                 struct omap_drm_pipeline *pipe,
0784                 struct drm_plane *plane)
0785 {
0786     struct omap_drm_private *priv = dev->dev_private;
0787     struct drm_crtc *crtc = NULL;
0788     struct omap_crtc *omap_crtc;
0789     enum omap_channel channel;
0790     int ret;
0791
0792     channel = pipe->output->dispc_channel;
0793
0794     DBG("%s", channel_names[channel]);
0795
0796     omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
0797     if (!omap_crtc)
0798         return ERR_PTR(-ENOMEM);
0799
0800     crtc = &omap_crtc->base;
0801
0802     init_waitqueue_head(&omap_crtc->pending_wait);
0803
0804     omap_crtc->pipe = pipe;
0805     omap_crtc->channel = channel;
0806     omap_crtc->name = channel_names[channel];
0807
0808     /*
0809      * We want to refresh manually updated displays from dirty callback,
0810      * which is called quite often (e.g. for each drawn line). This will
0811      * be used to do the display update asynchronously to avoid blocking
0812      * the rendering process and merges multiple dirty calls into one
0813      * update if they arrive very fast. We also call this function for
0814      * atomic display updates (e.g. for page flips), which means we do
0815      * not need extra locking. Atomic updates should be synchronous, but
0816      * need to wait for the framedone interrupt anyways.
0817      */
0818     INIT_DELAYED_WORK(&omap_crtc->update_work,
0819               omap_crtc_manual_display_update);
0820
0821     ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
0822                     &omap_crtc_funcs, NULL);
0823     if (ret < 0) {
0824         dev_err(dev->dev, "%s(): could not init crtc for: %s\n",
0825             __func__, pipe->output->name);
0826         kfree(omap_crtc);
0827         return ERR_PTR(ret);
0828     }
0829
0830     drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
0831
0832     /* The dispc API adapts to what ever size, but the HW supports
0833      * 256 element gamma table for LCDs and 1024 element table for
0834      * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma
0835      * tables so lets use that. Size of HW gamma table can be
0836      * extracted with dispc_mgr_gamma_size(). If it returns 0
0837      * gamma table is not supported.
0838      */
0839     if (dispc_mgr_gamma_size(priv->dispc, channel)) {
0840         unsigned int gamma_lut_size = 256;
0841
0842         drm_crtc_enable_color_mgmt(crtc, gamma_lut_size, true, 0);
0843         drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
0844     }
0845
0846     omap_plane_install_properties(crtc->primary, &crtc->base);
0847
0848     return crtc;
0849 }