omapdrm/dss/video-pll.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
0004  */
0005
0006 #include <linux/clk.h>
0007 #include <linux/delay.h>
0008 #include <linux/err.h>
0009 #include <linux/io.h>
0010 #include <linux/kernel.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/sched.h>
0013
0014 #include "omapdss.h"
0015 #include "dss.h"
0016
0017 struct dss_video_pll {
0018     struct dss_pll pll;
0019
0020     struct device *dev;
0021
0022     void __iomem *clkctrl_base;
0023 };
0024
0025 #define REG_MOD(reg, val, start, end) \
0026     writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg)
0027
0028 static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll)
0029 {
0030     REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */
0031 }
0032
0033 static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll)
0034 {
0035     REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */
0036 }
0037
0038 static void dss_dpll_power_enable(struct dss_video_pll *vpll)
0039 {
0040     REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */
0041
0042     /*
0043      * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0,
0044      * so we have to use fixed delay here.
0045      */
0046     msleep(1);
0047 }
0048
0049 static void dss_dpll_power_disable(struct dss_video_pll *vpll)
0050 {
0051     REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */
0052 }
0053
0054 static int dss_video_pll_enable(struct dss_pll *pll)
0055 {
0056     struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
0057     int r;
0058
0059     r = dss_runtime_get(pll->dss);
0060     if (r)
0061         return r;
0062
0063     dss_ctrl_pll_enable(pll, true);
0064
0065     dss_dpll_enable_scp_clk(vpll);
0066
0067     r = dss_pll_wait_reset_done(pll);
0068     if (r)
0069         goto err_reset;
0070
0071     dss_dpll_power_enable(vpll);
0072
0073     return 0;
0074
0075 err_reset:
0076     dss_dpll_disable_scp_clk(vpll);
0077     dss_ctrl_pll_enable(pll, false);
0078     dss_runtime_put(pll->dss);
0079
0080     return r;
0081 }
0082
0083 static void dss_video_pll_disable(struct dss_pll *pll)
0084 {
0085     struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
0086
0087     dss_dpll_power_disable(vpll);
0088
0089     dss_dpll_disable_scp_clk(vpll);
0090
0091     dss_ctrl_pll_enable(pll, false);
0092
0093     dss_runtime_put(pll->dss);
0094 }
0095
0096 static const struct dss_pll_ops dss_pll_ops = {
0097     .enable = dss_video_pll_enable,
0098     .disable = dss_video_pll_disable,
0099     .set_config = dss_pll_write_config_type_a,
0100 };
0101
0102 static const struct dss_pll_hw dss_dra7_video_pll_hw = {
0103     .type = DSS_PLL_TYPE_A,
0104
0105     .n_max = (1 << 8) - 1,
0106     .m_max = (1 << 12) - 1,
0107     .mX_max = (1 << 5) - 1,
0108     .fint_min = 500000,
0109     .fint_max = 2500000,
0110     .clkdco_max = 1800000000,
0111
0112     .n_msb = 8,
0113     .n_lsb = 1,
0114     .m_msb = 20,
0115     .m_lsb = 9,
0116
0117     .mX_msb[0] = 25,
0118     .mX_lsb[0] = 21,
0119     .mX_msb[1] = 30,
0120     .mX_lsb[1] = 26,
0121     .mX_msb[2] = 4,
0122     .mX_lsb[2] = 0,
0123     .mX_msb[3] = 9,
0124     .mX_lsb[3] = 5,
0125
0126     .has_refsel = true,
0127
0128     .errata_i886 = true,
0129     .errata_i932 = true,
0130 };
0131
0132 struct dss_pll *dss_video_pll_init(struct dss_device *dss,
0133                    struct platform_device *pdev, int id,
0134                    struct regulator *regulator)
0135 {
0136     const char * const reg_name[] = { "pll1", "pll2" };
0137     const char * const clkctrl_name[] = { "pll1_clkctrl", "pll2_clkctrl" };
0138     const char * const clkin_name[] = { "video1_clk", "video2_clk" };
0139
0140     struct dss_video_pll *vpll;
0141     void __iomem *pll_base, *clkctrl_base;
0142     struct clk *clk;
0143     struct dss_pll *pll;
0144     int r;
0145
0146     /* PLL CONTROL */
0147
0148     pll_base = devm_platform_ioremap_resource_byname(pdev, reg_name[id]);
0149     if (IS_ERR(pll_base))
0150         return ERR_CAST(pll_base);
0151
0152     /* CLOCK CONTROL */
0153
0154     clkctrl_base = devm_platform_ioremap_resource_byname(pdev, clkctrl_name[id]);
0155     if (IS_ERR(clkctrl_base))
0156         return ERR_CAST(clkctrl_base);
0157
0158     /* CLKIN */
0159
0160     clk = devm_clk_get(&pdev->dev, clkin_name[id]);
0161     if (IS_ERR(clk)) {
0162         DSSERR("can't get video pll clkin\n");
0163         return ERR_CAST(clk);
0164     }
0165
0166     vpll = devm_kzalloc(&pdev->dev, sizeof(*vpll), GFP_KERNEL);
0167     if (!vpll)
0168         return ERR_PTR(-ENOMEM);
0169
0170     vpll->dev = &pdev->dev;
0171     vpll->clkctrl_base = clkctrl_base;
0172
0173     pll = &vpll->pll;
0174
0175     pll->name = id == 0 ? "video0" : "video1";
0176     pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2;
0177     pll->clkin = clk;
0178     pll->regulator = regulator;
0179     pll->base = pll_base;
0180     pll->hw = &dss_dra7_video_pll_hw;
0181     pll->ops = &dss_pll_ops;
0182
0183     r = dss_pll_register(dss, pll);
0184     if (r)
0185         return ERR_PTR(r);
0186
0187     return pll;
0188 }
0189
0190 void dss_video_pll_uninit(struct dss_pll *pll)
0191 {
0192     dss_pll_unregister(pll);
0193 }