omapdrm/dss/omapdss.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
0004  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
0005  */
0006
0007 #ifndef __OMAP_DRM_DSS_H
0008 #define __OMAP_DRM_DSS_H
0009
0010 #include <drm/drm_color_mgmt.h>
0011 #include <drm/drm_crtc.h>
0012 #include <drm/drm_mode.h>
0013 #include <linux/device.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/list.h>
0016 #include <linux/platform_data/omapdss.h>
0017 #include <video/videomode.h>
0018
0019 #define DISPC_IRQ_FRAMEDONE     (1 << 0)
0020 #define DISPC_IRQ_VSYNC         (1 << 1)
0021 #define DISPC_IRQ_EVSYNC_EVEN       (1 << 2)
0022 #define DISPC_IRQ_EVSYNC_ODD        (1 << 3)
0023 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
0024 #define DISPC_IRQ_PROG_LINE_NUM     (1 << 5)
0025 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
0026 #define DISPC_IRQ_GFX_END_WIN       (1 << 7)
0027 #define DISPC_IRQ_PAL_GAMMA_MASK    (1 << 8)
0028 #define DISPC_IRQ_OCP_ERR       (1 << 9)
0029 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
0030 #define DISPC_IRQ_VID1_END_WIN      (1 << 11)
0031 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
0032 #define DISPC_IRQ_VID2_END_WIN      (1 << 13)
0033 #define DISPC_IRQ_SYNC_LOST     (1 << 14)
0034 #define DISPC_IRQ_SYNC_LOST_DIGIT   (1 << 15)
0035 #define DISPC_IRQ_WAKEUP        (1 << 16)
0036 #define DISPC_IRQ_SYNC_LOST2        (1 << 17)
0037 #define DISPC_IRQ_VSYNC2        (1 << 18)
0038 #define DISPC_IRQ_VID3_END_WIN      (1 << 19)
0039 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW   (1 << 20)
0040 #define DISPC_IRQ_ACBIAS_COUNT_STAT2    (1 << 21)
0041 #define DISPC_IRQ_FRAMEDONE2        (1 << 22)
0042 #define DISPC_IRQ_FRAMEDONEWB       (1 << 23)
0043 #define DISPC_IRQ_FRAMEDONETV       (1 << 24)
0044 #define DISPC_IRQ_WBBUFFEROVERFLOW  (1 << 25)
0045 #define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26)
0046 #define DISPC_IRQ_SYNC_LOST3        (1 << 27)
0047 #define DISPC_IRQ_VSYNC3        (1 << 28)
0048 #define DISPC_IRQ_ACBIAS_COUNT_STAT3    (1 << 29)
0049 #define DISPC_IRQ_FRAMEDONE3        (1 << 30)
0050
0051 struct dispc_device;
0052 struct drm_connector;
0053 struct dss_device;
0054 struct dss_lcd_mgr_config;
0055 struct hdmi_avi_infoframe;
0056 struct omap_drm_private;
0057 struct omap_dss_device;
0058 struct snd_aes_iec958;
0059 struct snd_cea_861_aud_if;
0060
0061 enum omap_display_type {
0062     OMAP_DISPLAY_TYPE_NONE      = 0,
0063     OMAP_DISPLAY_TYPE_DPI       = 1 << 0,
0064     OMAP_DISPLAY_TYPE_DBI       = 1 << 1,
0065     OMAP_DISPLAY_TYPE_SDI       = 1 << 2,
0066     OMAP_DISPLAY_TYPE_DSI       = 1 << 3,
0067     OMAP_DISPLAY_TYPE_VENC      = 1 << 4,
0068     OMAP_DISPLAY_TYPE_HDMI      = 1 << 5,
0069     OMAP_DISPLAY_TYPE_DVI       = 1 << 6,
0070 };
0071
0072 enum omap_plane_id {
0073     OMAP_DSS_GFX    = 0,
0074     OMAP_DSS_VIDEO1 = 1,
0075     OMAP_DSS_VIDEO2 = 2,
0076     OMAP_DSS_VIDEO3 = 3,
0077     OMAP_DSS_WB = 4,
0078 };
0079
0080 enum omap_channel {
0081     OMAP_DSS_CHANNEL_LCD    = 0,
0082     OMAP_DSS_CHANNEL_DIGIT  = 1,
0083     OMAP_DSS_CHANNEL_LCD2   = 2,
0084     OMAP_DSS_CHANNEL_LCD3   = 3,
0085     OMAP_DSS_CHANNEL_WB = 4,
0086 };
0087
0088 enum omap_color_mode {
0089     _UNUSED_,
0090 };
0091
0092 enum omap_dss_load_mode {
0093     OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
0094     OMAP_DSS_LOAD_CLUT_ONLY     = 1,
0095     OMAP_DSS_LOAD_FRAME_ONLY    = 2,
0096     OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
0097 };
0098
0099 enum omap_dss_trans_key_type {
0100     OMAP_DSS_COLOR_KEY_GFX_DST = 0,
0101     OMAP_DSS_COLOR_KEY_VID_SRC = 1,
0102 };
0103
0104 enum omap_dss_signal_level {
0105     OMAPDSS_SIG_ACTIVE_LOW,
0106     OMAPDSS_SIG_ACTIVE_HIGH,
0107 };
0108
0109 enum omap_dss_signal_edge {
0110     OMAPDSS_DRIVE_SIG_FALLING_EDGE,
0111     OMAPDSS_DRIVE_SIG_RISING_EDGE,
0112 };
0113
0114 enum omap_dss_venc_type {
0115     OMAP_DSS_VENC_TYPE_COMPOSITE,
0116     OMAP_DSS_VENC_TYPE_SVIDEO,
0117 };
0118
0119 enum omap_dss_rotation_type {
0120     OMAP_DSS_ROT_NONE   = 0,
0121     OMAP_DSS_ROT_TILER  = 1 << 0,
0122 };
0123
0124 enum omap_overlay_caps {
0125     OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
0126     OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
0127     OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
0128     OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
0129     OMAP_DSS_OVL_CAP_POS = 1 << 4,
0130     OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
0131 };
0132
0133 enum omap_dss_output_id {
0134     OMAP_DSS_OUTPUT_DPI = 1 << 0,
0135     OMAP_DSS_OUTPUT_DBI = 1 << 1,
0136     OMAP_DSS_OUTPUT_SDI = 1 << 2,
0137     OMAP_DSS_OUTPUT_DSI1    = 1 << 3,
0138     OMAP_DSS_OUTPUT_DSI2    = 1 << 4,
0139     OMAP_DSS_OUTPUT_VENC    = 1 << 5,
0140     OMAP_DSS_OUTPUT_HDMI    = 1 << 6,
0141 };
0142
0143 struct omap_dss_cpr_coefs {
0144     s16 rr, rg, rb;
0145     s16 gr, gg, gb;
0146     s16 br, bg, bb;
0147 };
0148
0149 struct omap_overlay_info {
0150     dma_addr_t paddr;
0151     dma_addr_t p_uv_addr;  /* for NV12 format */
0152     u16 screen_width;
0153     u16 width;
0154     u16 height;
0155     u32 fourcc;
0156     u8 rotation;
0157     enum omap_dss_rotation_type rotation_type;
0158
0159     u16 pos_x;
0160     u16 pos_y;
0161     u16 out_width;  /* if 0, out_width == width */
0162     u16 out_height; /* if 0, out_height == height */
0163     u8 global_alpha;
0164     u8 pre_mult_alpha;
0165     u8 zorder;
0166
0167     enum drm_color_encoding color_encoding;
0168     enum drm_color_range color_range;
0169 };
0170
0171 struct omap_overlay_manager_info {
0172     u32 default_color;
0173
0174     enum omap_dss_trans_key_type trans_key_type;
0175     u32 trans_key;
0176     bool trans_enabled;
0177
0178     bool partial_alpha_enabled;
0179
0180     bool cpr_enable;
0181     struct omap_dss_cpr_coefs cpr_coefs;
0182 };
0183
0184 struct omap_dss_writeback_info {
0185     u32 paddr;
0186     u32 p_uv_addr;
0187     u16 buf_width;
0188     u16 width;
0189     u16 height;
0190     u32 fourcc;
0191     u8 rotation;
0192     enum omap_dss_rotation_type rotation_type;
0193     u8 pre_mult_alpha;
0194 };
0195
0196 struct omapdss_dsi_ops {
0197     int (*update)(struct omap_dss_device *dssdev);
0198     bool (*is_video_mode)(struct omap_dss_device *dssdev);
0199 };
0200
0201 struct omap_dss_device {
0202     struct device *dev;
0203
0204     struct dss_device *dss;
0205     struct drm_bridge *bridge;
0206     struct drm_bridge *next_bridge;
0207     struct drm_panel *panel;
0208
0209     struct list_head list;
0210
0211     /*
0212      * DSS type that this device generates (for DSS internal devices) or
0213      * requires (for external encoders, connectors and panels). Must be a
0214      * non-zero (different than OMAP_DISPLAY_TYPE_NONE) value.
0215      */
0216     enum omap_display_type type;
0217
0218     const char *name;
0219
0220     const struct omapdss_dsi_ops *dsi_ops;
0221     u32 bus_flags;
0222
0223     /* OMAP DSS output specific fields */
0224
0225     /* DISPC channel for this output */
0226     enum omap_channel dispc_channel;
0227
0228     /* output instance */
0229     enum omap_dss_output_id id;
0230
0231     /* port number in DT */
0232     unsigned int of_port;
0233 };
0234
0235 struct dss_pdata {
0236     struct dss_device *dss;
0237 };
0238
0239 void omapdss_device_register(struct omap_dss_device *dssdev);
0240 void omapdss_device_unregister(struct omap_dss_device *dssdev);
0241 struct omap_dss_device *omapdss_device_get(struct omap_dss_device *dssdev);
0242 void omapdss_device_put(struct omap_dss_device *dssdev);
0243 struct omap_dss_device *omapdss_find_device_by_node(struct device_node *node);
0244 int omapdss_device_connect(struct dss_device *dss,
0245                struct omap_dss_device *src,
0246                struct omap_dss_device *dst);
0247 void omapdss_device_disconnect(struct omap_dss_device *src,
0248                    struct omap_dss_device *dst);
0249
0250 int omap_dss_get_num_overlay_managers(void);
0251
0252 int omap_dss_get_num_overlays(void);
0253
0254 #define for_each_dss_output(d) \
0255     while ((d = omapdss_device_next_output(d)) != NULL)
0256 struct omap_dss_device *omapdss_device_next_output(struct omap_dss_device *from);
0257 int omapdss_device_init_output(struct omap_dss_device *out,
0258                    struct drm_bridge *local_bridge);
0259 void omapdss_device_cleanup_output(struct omap_dss_device *out);
0260
0261 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
0262 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
0263 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
0264
0265 int omapdss_compat_init(void);
0266 void omapdss_compat_uninit(void);
0267
0268 enum dss_writeback_channel {
0269     DSS_WB_LCD1_MGR =   0,
0270     DSS_WB_LCD2_MGR =   1,
0271     DSS_WB_TV_MGR =     2,
0272     DSS_WB_OVL0 =       3,
0273     DSS_WB_OVL1 =       4,
0274     DSS_WB_OVL2 =       5,
0275     DSS_WB_OVL3 =       6,
0276     DSS_WB_LCD3_MGR =   7,
0277 };
0278
0279 void omap_crtc_dss_start_update(struct omap_drm_private *priv,
0280                        enum omap_channel channel);
0281 void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable);
0282 int omap_crtc_dss_enable(struct omap_drm_private *priv, enum omap_channel channel);
0283 void omap_crtc_dss_disable(struct omap_drm_private *priv, enum omap_channel channel);
0284 void omap_crtc_dss_set_timings(struct omap_drm_private *priv,
0285         enum omap_channel channel,
0286         const struct videomode *vm);
0287 void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv,
0288         enum omap_channel channel,
0289         const struct dss_lcd_mgr_config *config);
0290 int omap_crtc_dss_register_framedone(
0291         struct omap_drm_private *priv, enum omap_channel channel,
0292         void (*handler)(void *), void *data);
0293 void omap_crtc_dss_unregister_framedone(
0294         struct omap_drm_private *priv, enum omap_channel channel,
0295         void (*handler)(void *), void *data);
0296
0297 void dss_mgr_set_timings(struct omap_dss_device *dssdev,
0298         const struct videomode *vm);
0299 void dss_mgr_set_lcd_config(struct omap_dss_device *dssdev,
0300         const struct dss_lcd_mgr_config *config);
0301 int dss_mgr_enable(struct omap_dss_device *dssdev);
0302 void dss_mgr_disable(struct omap_dss_device *dssdev);
0303 void dss_mgr_start_update(struct omap_dss_device *dssdev);
0304 int dss_mgr_register_framedone_handler(struct omap_dss_device *dssdev,
0305         void (*handler)(void *), void *data);
0306 void dss_mgr_unregister_framedone_handler(struct omap_dss_device *dssdev,
0307         void (*handler)(void *), void *data);
0308
0309 struct dispc_device *dispc_get_dispc(struct dss_device *dss);
0310
0311 bool omapdss_stack_is_ready(void);
0312 void omapdss_gather_components(struct device *dev);
0313
0314 int omap_dss_init(void);
0315 void omap_dss_exit(void);
0316
0317 #endif /* __OMAP_DRM_DSS_H */