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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * OMAP5 HDMI CORE IP driver library
0004  *
0005  * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
0006  * Authors:
0007  *  Yong Zhi
0008  *  Mythri pk
0009  *  Archit Taneja <archit@ti.com>
0010  *  Tomi Valkeinen <tomi.valkeinen@ti.com>
0011  */
0012 
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/err.h>
0016 #include <linux/io.h>
0017 #include <linux/delay.h>
0018 #include <linux/string.h>
0019 #include <linux/seq_file.h>
0020 #include <drm/drm_edid.h>
0021 #include <sound/asound.h>
0022 #include <sound/asoundef.h>
0023 
0024 #include "hdmi5_core.h"
0025 
0026 void hdmi5_core_ddc_init(struct hdmi_core_data *core)
0027 {
0028     void __iomem *base = core->base;
0029     const unsigned long long iclk = 266000000;  /* DSS L3 ICLK */
0030     const unsigned int ss_scl_high = 4700;      /* ns */
0031     const unsigned int ss_scl_low = 5500;       /* ns */
0032     const unsigned int fs_scl_high = 600;       /* ns */
0033     const unsigned int fs_scl_low = 1300;       /* ns */
0034     const unsigned int sda_hold = 1000;     /* ns */
0035     const unsigned int sfr_div = 10;
0036     unsigned long long sfr;
0037     unsigned int v;
0038 
0039     sfr = iclk / sfr_div;   /* SFR_DIV */
0040     sfr /= 1000;        /* SFR clock in kHz */
0041 
0042     /* Reset */
0043     REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0);
0044     if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ,
0045                 0, 0, 1) != 1)
0046         DSSERR("HDMI I2CM reset failed\n");
0047 
0048     /* Standard (0) or Fast (1) Mode */
0049     REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3);
0050 
0051     /* Standard Mode SCL High counter */
0052     v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000);
0053     REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR,
0054             (v >> 8) & 0xff, 7, 0);
0055     REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR,
0056             v & 0xff, 7, 0);
0057 
0058     /* Standard Mode SCL Low counter */
0059     v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000);
0060     REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR,
0061             (v >> 8) & 0xff, 7, 0);
0062     REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR,
0063             v & 0xff, 7, 0);
0064 
0065     /* Fast Mode SCL High Counter */
0066     v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000);
0067     REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR,
0068             (v >> 8) & 0xff, 7, 0);
0069     REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR,
0070             v & 0xff, 7, 0);
0071 
0072     /* Fast Mode SCL Low Counter */
0073     v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000);
0074     REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR,
0075             (v >> 8) & 0xff, 7, 0);
0076     REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR,
0077             v & 0xff, 7, 0);
0078 
0079     /* SDA Hold Time */
0080     v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000);
0081     REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0);
0082 
0083     REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0);
0084     REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0);
0085 
0086     /* NACK_POL to high */
0087     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7);
0088 
0089     /* NACK_MASK to unmasked */
0090     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6);
0091 
0092     /* ARBITRATION_POL to high */
0093     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3);
0094 
0095     /* ARBITRATION_MASK to unmasked */
0096     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2);
0097 
0098     /* DONE_POL to high */
0099     REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3);
0100 
0101     /* DONE_MASK to unmasked */
0102     REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2);
0103 }
0104 
0105 void hdmi5_core_ddc_uninit(struct hdmi_core_data *core)
0106 {
0107     void __iomem *base = core->base;
0108 
0109     /* Mask I2C interrupts */
0110     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
0111     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
0112     REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
0113 }
0114 
0115 int hdmi5_core_ddc_read(void *data, u8 *buf, unsigned int block, size_t len)
0116 {
0117     struct hdmi_core_data *core = data;
0118     void __iomem *base = core->base;
0119     u8 cur_addr;
0120     const int retries = 1000;
0121     u8 seg_ptr = block / 2;
0122     u8 edidbase = ((block % 2) * EDID_LENGTH);
0123 
0124     REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0);
0125 
0126     /*
0127      * TODO: We use polling here, although we probably should use proper
0128      * interrupts.
0129      */
0130     for (cur_addr = 0; cur_addr < len; ++cur_addr) {
0131         int i;
0132 
0133         /* clear ERROR and DONE */
0134         REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
0135 
0136         REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS,
0137                 edidbase + cur_addr, 7, 0);
0138 
0139         if (seg_ptr)
0140             REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1);
0141         else
0142             REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0);
0143 
0144         for (i = 0; i < retries; ++i) {
0145             u32 stat;
0146 
0147             stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0);
0148 
0149             /* I2CM_ERROR */
0150             if (stat & 1) {
0151                 DSSERR("HDMI I2C Master Error\n");
0152                 return -EIO;
0153             }
0154 
0155             /* I2CM_DONE */
0156             if (stat & (1 << 1))
0157                 break;
0158 
0159             usleep_range(250, 1000);
0160         }
0161 
0162         if (i == retries) {
0163             DSSERR("HDMI I2C timeout reading EDID\n");
0164             return -EIO;
0165         }
0166 
0167         buf[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
0168     }
0169 
0170     return 0;
0171 
0172 }
0173 
0174 void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s)
0175 {
0176 
0177 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
0178         hdmi_read_reg(core->base, r))
0179 
0180     DUMPCORE(HDMI_CORE_FC_INVIDCONF);
0181     DUMPCORE(HDMI_CORE_FC_INHACTIV0);
0182     DUMPCORE(HDMI_CORE_FC_INHACTIV1);
0183     DUMPCORE(HDMI_CORE_FC_INHBLANK0);
0184     DUMPCORE(HDMI_CORE_FC_INHBLANK1);
0185     DUMPCORE(HDMI_CORE_FC_INVACTIV0);
0186     DUMPCORE(HDMI_CORE_FC_INVACTIV1);
0187     DUMPCORE(HDMI_CORE_FC_INVBLANK);
0188     DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0);
0189     DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1);
0190     DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0);
0191     DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1);
0192     DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY);
0193     DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH);
0194     DUMPCORE(HDMI_CORE_FC_CTRLDUR);
0195     DUMPCORE(HDMI_CORE_FC_EXCTRLDUR);
0196     DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC);
0197     DUMPCORE(HDMI_CORE_FC_CH0PREAM);
0198     DUMPCORE(HDMI_CORE_FC_CH1PREAM);
0199     DUMPCORE(HDMI_CORE_FC_CH2PREAM);
0200     DUMPCORE(HDMI_CORE_FC_AVICONF0);
0201     DUMPCORE(HDMI_CORE_FC_AVICONF1);
0202     DUMPCORE(HDMI_CORE_FC_AVICONF2);
0203     DUMPCORE(HDMI_CORE_FC_AVIVID);
0204     DUMPCORE(HDMI_CORE_FC_PRCONF);
0205 
0206     DUMPCORE(HDMI_CORE_MC_CLKDIS);
0207     DUMPCORE(HDMI_CORE_MC_SWRSTZREQ);
0208     DUMPCORE(HDMI_CORE_MC_FLOWCTRL);
0209     DUMPCORE(HDMI_CORE_MC_PHYRSTZ);
0210     DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK);
0211 
0212     DUMPCORE(HDMI_CORE_I2CM_SLAVE);
0213     DUMPCORE(HDMI_CORE_I2CM_ADDRESS);
0214     DUMPCORE(HDMI_CORE_I2CM_DATAO);
0215     DUMPCORE(HDMI_CORE_I2CM_DATAI);
0216     DUMPCORE(HDMI_CORE_I2CM_OPERATION);
0217     DUMPCORE(HDMI_CORE_I2CM_INT);
0218     DUMPCORE(HDMI_CORE_I2CM_CTLINT);
0219     DUMPCORE(HDMI_CORE_I2CM_DIV);
0220     DUMPCORE(HDMI_CORE_I2CM_SEGADDR);
0221     DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ);
0222     DUMPCORE(HDMI_CORE_I2CM_SEGPTR);
0223     DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR);
0224     DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR);
0225     DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR);
0226     DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR);
0227     DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR);
0228     DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR);
0229     DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR);
0230     DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR);
0231     DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR);
0232 }
0233 
0234 static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
0235                const struct hdmi_config *cfg)
0236 {
0237     DSSDBG("hdmi_core_init\n");
0238 
0239     video_cfg->v_fc_config.vm = cfg->vm;
0240 
0241     /* video core */
0242     video_cfg->data_enable_pol = 1; /* It is always 1*/
0243     video_cfg->hblank = cfg->vm.hfront_porch +
0244                 cfg->vm.hback_porch + cfg->vm.hsync_len;
0245     video_cfg->vblank_osc = 0;
0246     video_cfg->vblank = cfg->vm.vsync_len + cfg->vm.vfront_porch +
0247                 cfg->vm.vback_porch;
0248     video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
0249 
0250     if (cfg->vm.flags & DISPLAY_FLAGS_INTERLACED) {
0251         /* set vblank_osc if vblank is fractional */
0252         if (video_cfg->vblank % 2 != 0)
0253             video_cfg->vblank_osc = 1;
0254 
0255         video_cfg->v_fc_config.vm.vactive /= 2;
0256         video_cfg->vblank /= 2;
0257         video_cfg->v_fc_config.vm.vfront_porch /= 2;
0258         video_cfg->v_fc_config.vm.vsync_len /= 2;
0259         video_cfg->v_fc_config.vm.vback_porch /= 2;
0260     }
0261 
0262     if (cfg->vm.flags & DISPLAY_FLAGS_DOUBLECLK) {
0263         video_cfg->v_fc_config.vm.hactive *= 2;
0264         video_cfg->hblank *= 2;
0265         video_cfg->v_fc_config.vm.hfront_porch *= 2;
0266         video_cfg->v_fc_config.vm.hsync_len *= 2;
0267         video_cfg->v_fc_config.vm.hback_porch *= 2;
0268     }
0269 }
0270 
0271 /* DSS_HDMI_CORE_VIDEO_CONFIG */
0272 static void hdmi_core_video_config(struct hdmi_core_data *core,
0273             const struct hdmi_core_vid_config *cfg)
0274 {
0275     void __iomem *base = core->base;
0276     const struct videomode *vm = &cfg->v_fc_config.vm;
0277     unsigned char r = 0;
0278     bool vsync_pol, hsync_pol;
0279 
0280     vsync_pol = !!(vm->flags & DISPLAY_FLAGS_VSYNC_HIGH);
0281     hsync_pol = !!(vm->flags & DISPLAY_FLAGS_HSYNC_HIGH);
0282 
0283     /* Set hsync, vsync and data-enable polarity  */
0284     r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
0285     r = FLD_MOD(r, vsync_pol, 6, 6);
0286     r = FLD_MOD(r, hsync_pol, 5, 5);
0287     r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
0288     r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
0289     r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 0, 0);
0290     hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
0291 
0292     /* set x resolution */
0293     REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, vm->hactive >> 8, 4, 0);
0294     REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, vm->hactive & 0xFF, 7, 0);
0295 
0296     /* set y resolution */
0297     REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, vm->vactive >> 8, 4, 0);
0298     REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, vm->vactive & 0xFF, 7, 0);
0299 
0300     /* set horizontal blanking pixels */
0301     REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0);
0302     REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0);
0303 
0304     /* set vertial blanking pixels */
0305     REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0);
0306 
0307     /* set horizontal sync offset */
0308     REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, vm->hfront_porch >> 8,
0309             4, 0);
0310     REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, vm->hfront_porch & 0xFF,
0311             7, 0);
0312 
0313     /* set vertical sync offset */
0314     REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, vm->vfront_porch, 7, 0);
0315 
0316     /* set horizontal sync pulse width */
0317     REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, (vm->hsync_len >> 8),
0318             1, 0);
0319     REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, vm->hsync_len & 0xFF,
0320             7, 0);
0321 
0322     /*  set vertical sync pulse width */
0323     REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, vm->vsync_len, 5, 0);
0324 
0325     /* select DVI mode */
0326     REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
0327             cfg->v_fc_config.hdmi_dvi_mode, 3, 3);
0328 
0329     if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
0330         REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 2, 7, 4);
0331     else
0332         REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 1, 7, 4);
0333 }
0334 
0335 static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)
0336 {
0337     void __iomem *base = core->base;
0338     int clr_depth = 0;  /* 24 bit color depth */
0339 
0340     /* COLOR_DEPTH */
0341     REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4);
0342     /* BYPASS_EN */
0343     REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6);
0344     /* PP_EN */
0345     REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5);
0346     /* YCC422_EN */
0347     REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3);
0348     /* PP_STUFFING */
0349     REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1);
0350     /* YCC422_STUFFING */
0351     REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2);
0352     /* OUTPUT_SELECTOR */
0353     REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
0354 }
0355 
0356 static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
0357 {
0358     int video_mapping = 1;  /* for 24 bit color depth */
0359 
0360     /* VIDEO_MAPPING */
0361     REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0);
0362 }
0363 
0364 static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
0365     struct hdmi_avi_infoframe *frame)
0366 {
0367     void __iomem *base = core->base;
0368     u8 data[HDMI_INFOFRAME_SIZE(AVI)];
0369     u8 *ptr;
0370     unsigned int y, a, b, s;
0371     unsigned int c, m, r;
0372     unsigned int itc, ec, q, sc;
0373     unsigned int vic;
0374     unsigned int yq, cn, pr;
0375 
0376     hdmi_avi_infoframe_pack(frame, data, sizeof(data));
0377 
0378     print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data,
0379         HDMI_INFOFRAME_SIZE(AVI), false);
0380 
0381     ptr = data + HDMI_INFOFRAME_HEADER_SIZE;
0382 
0383     y = (ptr[0] >> 5) & 0x3;
0384     a = (ptr[0] >> 4) & 0x1;
0385     b = (ptr[0] >> 2) & 0x3;
0386     s = (ptr[0] >> 0) & 0x3;
0387 
0388     c = (ptr[1] >> 6) & 0x3;
0389     m = (ptr[1] >> 4) & 0x3;
0390     r = (ptr[1] >> 0) & 0xf;
0391 
0392     itc = (ptr[2] >> 7) & 0x1;
0393     ec = (ptr[2] >> 4) & 0x7;
0394     q = (ptr[2] >> 2) & 0x3;
0395     sc = (ptr[2] >> 0) & 0x3;
0396 
0397     vic = ptr[3];
0398 
0399     yq = (ptr[4] >> 6) & 0x3;
0400     cn = (ptr[4] >> 4) & 0x3;
0401     pr = (ptr[4] >> 0) & 0xf;
0402 
0403     hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0,
0404         (a << 6) | (s << 4) | (b << 2) | (y << 0));
0405 
0406     hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1,
0407         (c << 6) | (m << 4) | (r << 0));
0408 
0409     hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2,
0410         (itc << 7) | (ec << 4) | (q << 2) | (sc << 0));
0411 
0412     hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic);
0413 
0414     hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3,
0415         (yq << 2) | (cn << 0));
0416 
0417     REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0);
0418 }
0419 
0420 static void hdmi_core_write_csc(struct hdmi_core_data *core,
0421         const struct csc_table *csc_coeff)
0422 {
0423     void __iomem *base = core->base;
0424 
0425     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff->a1 >> 8, 6, 0);
0426     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff->a1, 7, 0);
0427     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff->a2 >> 8, 6, 0);
0428     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff->a2, 7, 0);
0429     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff->a3 >> 8, 6, 0);
0430     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff->a3, 7, 0);
0431     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff->a4 >> 8, 6, 0);
0432     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff->a4, 7, 0);
0433     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff->b1 >> 8, 6, 0);
0434     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff->b1, 7, 0);
0435     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff->b2 >> 8, 6, 0);
0436     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff->b2, 7, 0);
0437     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff->b3 >> 8, 6, 0);
0438     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff->b3, 7, 0);
0439     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff->b4 >> 8, 6, 0);
0440     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff->b4, 7, 0);
0441     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff->c1 >> 8, 6, 0);
0442     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff->c1, 7, 0);
0443     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff->c2 >> 8, 6, 0);
0444     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff->c2, 7, 0);
0445     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff->c3 >> 8, 6, 0);
0446     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff->c3, 7, 0);
0447     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff->c4 >> 8, 6, 0);
0448     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff->c4, 7, 0);
0449 
0450     /* enable CSC */
0451     REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
0452 }
0453 
0454 static void hdmi_core_configure_range(struct hdmi_core_data *core,
0455                       enum hdmi_quantization_range range)
0456 {
0457     static const struct csc_table csc_limited_range = {
0458         7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32
0459     };
0460     static const struct csc_table csc_full_range = {
0461         8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0
0462     };
0463     const struct csc_table *csc_coeff;
0464 
0465     /* CSC_COLORDEPTH  = 24 bits*/
0466     REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, 0, 7, 4);
0467 
0468     switch (range) {
0469     case HDMI_QUANTIZATION_RANGE_FULL:
0470         csc_coeff = &csc_full_range;
0471         break;
0472 
0473     case HDMI_QUANTIZATION_RANGE_DEFAULT:
0474     case HDMI_QUANTIZATION_RANGE_LIMITED:
0475     default:
0476         csc_coeff = &csc_limited_range;
0477         break;
0478     }
0479 
0480     hdmi_core_write_csc(core, csc_coeff);
0481 }
0482 
0483 static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
0484 {
0485     void __iomem *base = core->base;
0486 
0487     DSSDBG("hdmi_core_enable_video_path\n");
0488 
0489     REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0);
0490     REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0);
0491     REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0);
0492     REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0);
0493     REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0);
0494     REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0);
0495     REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0);
0496     REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1);
0497 }
0498 
0499 static void hdmi_core_mask_interrupts(struct hdmi_core_data *core)
0500 {
0501     void __iomem *base = core->base;
0502 
0503     /* Master IRQ mask */
0504     REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0);
0505 
0506     /* Mask all the interrupts in HDMI core */
0507 
0508     REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0);
0509     REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0);
0510     REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0);
0511     REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0);
0512 
0513     REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2);
0514     REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0);
0515 
0516     REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0);
0517 
0518     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
0519     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
0520     REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
0521 
0522     REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0);
0523 
0524     REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
0525 
0526     /* Clear all the current interrupt bits */
0527 
0528     REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
0529     REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0);
0530     REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0);
0531     REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0);
0532 
0533     REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0);
0534 
0535     REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0);
0536 
0537     REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
0538 
0539     REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
0540 }
0541 
0542 static void hdmi_core_enable_interrupts(struct hdmi_core_data *core)
0543 {
0544     /* Unmute interrupts */
0545     REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0);
0546 }
0547 
0548 int hdmi5_core_handle_irqs(struct hdmi_core_data *core)
0549 {
0550     void __iomem *base = core->base;
0551 
0552     REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0);
0553     REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0);
0554     REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0);
0555     REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0);
0556     REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
0557     REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0);
0558     REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0);
0559     REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
0560     REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0);
0561 
0562     return 0;
0563 }
0564 
0565 void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
0566         struct hdmi_config *cfg)
0567 {
0568     struct videomode vm;
0569     struct hdmi_video_format video_format;
0570     struct hdmi_core_vid_config v_core_cfg;
0571     enum hdmi_quantization_range range;
0572 
0573     hdmi_core_mask_interrupts(core);
0574 
0575     if (cfg->hdmi_dvi_mode == HDMI_HDMI) {
0576         char vic = cfg->infoframe.video_code;
0577 
0578         /* All CEA modes other than VIC 1 use limited quantization range. */
0579         range = vic > 1 ? HDMI_QUANTIZATION_RANGE_LIMITED :
0580             HDMI_QUANTIZATION_RANGE_FULL;
0581     } else {
0582         range = HDMI_QUANTIZATION_RANGE_FULL;
0583     }
0584 
0585     hdmi_core_init(&v_core_cfg, cfg);
0586 
0587     hdmi_wp_init_vid_fmt_timings(&video_format, &vm, cfg);
0588 
0589     hdmi_wp_video_config_timing(wp, &vm);
0590 
0591     /* video config */
0592     video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
0593 
0594     hdmi_wp_video_config_format(wp, &video_format);
0595 
0596     hdmi_wp_video_config_interface(wp, &vm);
0597 
0598     hdmi_core_configure_range(core, range);
0599     cfg->infoframe.quantization_range = range;
0600 
0601     /*
0602      * configure core video part, set software reset in the core
0603      */
0604     v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL;
0605 
0606     hdmi_core_video_config(core, &v_core_cfg);
0607 
0608     hdmi_core_config_video_packetizer(core);
0609     hdmi_core_config_video_sampler(core);
0610 
0611     if (cfg->hdmi_dvi_mode == HDMI_HDMI)
0612         hdmi_core_write_avi_infoframe(core, &cfg->infoframe);
0613 
0614     hdmi_core_enable_video_path(core);
0615 
0616     hdmi_core_enable_interrupts(core);
0617 }
0618 
0619 static void hdmi5_core_audio_config(struct hdmi_core_data *core,
0620             struct hdmi_core_audio_config *cfg)
0621 {
0622     void __iomem *base = core->base;
0623     u8 val;
0624 
0625     /* Mute audio before configuring */
0626     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4);
0627 
0628     /* Set the N parameter */
0629     REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0);
0630     REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0);
0631     REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0);
0632 
0633     /*
0634      * CTS manual mode. Automatic mode is not supported when using audio
0635      * parallel interface.
0636      */
0637     REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4);
0638     REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0);
0639     REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0);
0640     REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0);
0641 
0642     /* Layout of Audio Sample Packets: 2-channel or multichannels */
0643     if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
0644         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0);
0645     else
0646         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0);
0647 
0648     /* Configure IEC-609580 Validity bits */
0649     /* Channel 0 is valid */
0650     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0);
0651     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4);
0652 
0653     if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
0654         val = 1;
0655     else
0656         val = 0;
0657 
0658     /* Channels 1, 2 setting */
0659     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1);
0660     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5);
0661     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2);
0662     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6);
0663     /* Channel 3 setting */
0664     if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH)
0665         val = 1;
0666     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3);
0667     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7);
0668 
0669     /* Configure IEC-60958 User bits */
0670     /* TODO: should be set by user. */
0671     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0);
0672 
0673     /* Configure IEC-60958 Channel Status word */
0674     /* CGMSA */
0675     val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA;
0676     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4);
0677 
0678     /* Copyright */
0679     val = (cfg->iec60958_cfg->status[0] &
0680             IEC958_AES0_CON_NOT_COPYRIGHT) >> 2;
0681     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0);
0682 
0683     /* Category */
0684     hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1),
0685         cfg->iec60958_cfg->status[1]);
0686 
0687     /* PCM audio mode */
0688     val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6;
0689     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4);
0690 
0691     /* Source number */
0692     val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE;
0693     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0);
0694 
0695     /* Channel number right 0  */
0696     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0);
0697     /* Channel number right 1*/
0698     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4);
0699     /* Channel number right 2  */
0700     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0);
0701     /* Channel number right 3*/
0702     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4);
0703     /* Channel number left 0  */
0704     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0);
0705     /* Channel number left 1*/
0706     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4);
0707     /* Channel number left 2  */
0708     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0);
0709     /* Channel number left 3*/
0710     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4);
0711 
0712     /* Clock accuracy and sample rate */
0713     hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7),
0714         cfg->iec60958_cfg->status[3]);
0715 
0716     /* Original sample rate and word length */
0717     hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8),
0718         cfg->iec60958_cfg->status[4]);
0719 
0720     /* Enable FIFO empty and full interrupts */
0721     REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2);
0722 
0723     /* Configure GPA */
0724     /* select HBR/SPDIF interfaces */
0725     if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) {
0726         /* select HBR/SPDIF interfaces */
0727         REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
0728         /* enable two channels in GPA */
0729         REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0);
0730     } else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) {
0731         /* select HBR/SPDIF interfaces */
0732         REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
0733         /* enable six channels in GPA */
0734         REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0);
0735     } else {
0736         /* select HBR/SPDIF interfaces */
0737         REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
0738         /* enable eight channels in GPA */
0739         REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0);
0740     }
0741 
0742     /* disable HBR */
0743     REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0);
0744     /* enable PCUV */
0745     REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1);
0746     /* enable GPA FIFO full and empty mask */
0747     REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0);
0748     /* set polarity of GPA FIFO empty interrupts */
0749     REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0);
0750 
0751     /* unmute audio */
0752     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4);
0753 }
0754 
0755 static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core,
0756      struct snd_cea_861_aud_if *info_aud)
0757 {
0758     void __iomem *base = core->base;
0759 
0760     /* channel count and coding type fields in AUDICONF0 are swapped */
0761     hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0,
0762         (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 |
0763         (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4);
0764 
0765     hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss);
0766     hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca);
0767     hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3,
0768       (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_DM_INH) >> 3 |
0769       (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_LSV));
0770 }
0771 
0772 int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
0773             struct omap_dss_audio *audio, u32 pclk)
0774 {
0775     struct hdmi_audio_format audio_format;
0776     struct hdmi_audio_dma audio_dma;
0777     struct hdmi_core_audio_config core_cfg;
0778     int n, cts, channel_count;
0779     unsigned int fs_nr;
0780     bool word_length_16b = false;
0781 
0782     if (!audio || !audio->iec || !audio->cea || !core)
0783         return -EINVAL;
0784 
0785     core_cfg.iec60958_cfg = audio->iec;
0786 
0787     if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) &&
0788         (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16))
0789             word_length_16b = true;
0790 
0791     /* only 16-bit word length supported atm */
0792     if (!word_length_16b)
0793         return -EINVAL;
0794 
0795     switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
0796     case IEC958_AES3_CON_FS_32000:
0797         fs_nr = 32000;
0798         break;
0799     case IEC958_AES3_CON_FS_44100:
0800         fs_nr = 44100;
0801         break;
0802     case IEC958_AES3_CON_FS_48000:
0803         fs_nr = 48000;
0804         break;
0805     case IEC958_AES3_CON_FS_88200:
0806         fs_nr = 88200;
0807         break;
0808     case IEC958_AES3_CON_FS_96000:
0809         fs_nr = 96000;
0810         break;
0811     case IEC958_AES3_CON_FS_176400:
0812         fs_nr = 176400;
0813         break;
0814     case IEC958_AES3_CON_FS_192000:
0815         fs_nr = 192000;
0816         break;
0817     default:
0818         return -EINVAL;
0819     }
0820 
0821     hdmi_compute_acr(pclk, fs_nr, &n, &cts);
0822     core_cfg.n = n;
0823     core_cfg.cts = cts;
0824 
0825     /* Audio channels settings */
0826     channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC)
0827                 + 1;
0828 
0829     if (channel_count == 2)
0830         core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
0831     else if (channel_count == 6)
0832         core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH;
0833     else
0834         core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH;
0835 
0836     /* DMA settings */
0837     if (word_length_16b)
0838         audio_dma.transfer_size = 0x10;
0839     else
0840         audio_dma.transfer_size = 0x20;
0841     audio_dma.block_size = 0xC0;
0842     audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
0843     audio_dma.fifo_threshold = 0x20; /* in number of samples */
0844 
0845     /* audio FIFO format settings for 16-bit samples*/
0846     audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
0847     audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
0848     audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
0849     audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
0850 
0851     /* only LPCM atm */
0852     audio_format.type = HDMI_AUDIO_TYPE_LPCM;
0853 
0854     /* only allowed option */
0855     audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
0856 
0857     /* disable start/stop signals of IEC 60958 blocks */
0858     audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
0859 
0860     /* configure DMA and audio FIFO format*/
0861     hdmi_wp_audio_config_dma(wp, &audio_dma);
0862     hdmi_wp_audio_config_format(wp, &audio_format);
0863 
0864     /* configure the core */
0865     hdmi5_core_audio_config(core, &core_cfg);
0866 
0867     /* configure CEA 861 audio infoframe */
0868     hdmi5_core_audio_infoframe_cfg(core, audio->cea);
0869 
0870     return 0;
0871 }
0872 
0873 int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
0874 {
0875     core->base = devm_platform_ioremap_resource_byname(pdev, "core");
0876     if (IS_ERR(core->base))
0877         return PTR_ERR(core->base);
0878 
0879     return 0;
0880 }
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