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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2009 Nokia Corporation
0004  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
0005  *
0006  * Some code and ideas taken from drivers/video/omap/ driver
0007  * by Imre Deak.
0008  */
0009 
0010 #ifndef __OMAP2_DSS_H
0011 #define __OMAP2_DSS_H
0012 
0013 #include <linux/interrupt.h>
0014 
0015 #include "omapdss.h"
0016 
0017 struct dispc_device;
0018 struct dss_debugfs_entry;
0019 struct platform_device;
0020 struct seq_file;
0021 
0022 #define MAX_DSS_LCD_MANAGERS    3
0023 #define MAX_NUM_DSI     2
0024 
0025 #ifdef pr_fmt
0026 #undef pr_fmt
0027 #endif
0028 
0029 #ifdef DSS_SUBSYS_NAME
0030 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
0031 #else
0032 #define pr_fmt(fmt) fmt
0033 #endif
0034 
0035 #define DSSDBG(format, ...) \
0036     pr_debug(format, ## __VA_ARGS__)
0037 
0038 #ifdef DSS_SUBSYS_NAME
0039 #define DSSERR(format, ...) \
0040     pr_err("omapdss " DSS_SUBSYS_NAME " error: " format, ##__VA_ARGS__)
0041 #else
0042 #define DSSERR(format, ...) \
0043     pr_err("omapdss error: " format, ##__VA_ARGS__)
0044 #endif
0045 
0046 #ifdef DSS_SUBSYS_NAME
0047 #define DSSINFO(format, ...) \
0048     pr_info("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
0049 #else
0050 #define DSSINFO(format, ...) \
0051     pr_info("omapdss: " format, ## __VA_ARGS__)
0052 #endif
0053 
0054 #ifdef DSS_SUBSYS_NAME
0055 #define DSSWARN(format, ...) \
0056     pr_warn("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
0057 #else
0058 #define DSSWARN(format, ...) \
0059     pr_warn("omapdss: " format, ##__VA_ARGS__)
0060 #endif
0061 
0062 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
0063    number. For example 7:0 */
0064 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
0065 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
0066 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
0067 #define FLD_MOD(orig, val, start, end) \
0068     (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
0069 
0070 enum dss_model {
0071     DSS_MODEL_OMAP2,
0072     DSS_MODEL_OMAP3,
0073     DSS_MODEL_OMAP4,
0074     DSS_MODEL_OMAP5,
0075     DSS_MODEL_DRA7,
0076 };
0077 
0078 enum dss_io_pad_mode {
0079     DSS_IO_PAD_MODE_RESET,
0080     DSS_IO_PAD_MODE_RFBI,
0081     DSS_IO_PAD_MODE_BYPASS,
0082 };
0083 
0084 enum dss_hdmi_venc_clk_source_select {
0085     DSS_VENC_TV_CLK = 0,
0086     DSS_HDMI_M_PCLK = 1,
0087 };
0088 
0089 enum dss_dsi_content_type {
0090     DSS_DSI_CONTENT_DCS,
0091     DSS_DSI_CONTENT_GENERIC,
0092 };
0093 
0094 enum dss_clk_source {
0095     DSS_CLK_SRC_FCK = 0,
0096 
0097     DSS_CLK_SRC_PLL1_1,
0098     DSS_CLK_SRC_PLL1_2,
0099     DSS_CLK_SRC_PLL1_3,
0100 
0101     DSS_CLK_SRC_PLL2_1,
0102     DSS_CLK_SRC_PLL2_2,
0103     DSS_CLK_SRC_PLL2_3,
0104 
0105     DSS_CLK_SRC_HDMI_PLL,
0106 };
0107 
0108 enum dss_pll_id {
0109     DSS_PLL_DSI1,
0110     DSS_PLL_DSI2,
0111     DSS_PLL_HDMI,
0112     DSS_PLL_VIDEO1,
0113     DSS_PLL_VIDEO2,
0114 };
0115 
0116 struct dss_pll;
0117 
0118 #define DSS_PLL_MAX_HSDIVS 4
0119 
0120 enum dss_pll_type {
0121     DSS_PLL_TYPE_A,
0122     DSS_PLL_TYPE_B,
0123 };
0124 
0125 /*
0126  * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
0127  * Type-B PLLs: clkout[0] refers to m2.
0128  */
0129 struct dss_pll_clock_info {
0130     /* rates that we get with dividers below */
0131     unsigned long fint;
0132     unsigned long clkdco;
0133     unsigned long clkout[DSS_PLL_MAX_HSDIVS];
0134 
0135     /* dividers */
0136     u16 n;
0137     u16 m;
0138     u32 mf;
0139     u16 mX[DSS_PLL_MAX_HSDIVS];
0140     u16 sd;
0141 };
0142 
0143 struct dss_pll_ops {
0144     int (*enable)(struct dss_pll *pll);
0145     void (*disable)(struct dss_pll *pll);
0146     int (*set_config)(struct dss_pll *pll,
0147         const struct dss_pll_clock_info *cinfo);
0148 };
0149 
0150 struct dss_pll_hw {
0151     enum dss_pll_type type;
0152 
0153     unsigned int n_max;
0154     unsigned int m_min;
0155     unsigned int m_max;
0156     unsigned int mX_max;
0157 
0158     unsigned long fint_min, fint_max;
0159     unsigned long clkdco_min, clkdco_low, clkdco_max;
0160 
0161     u8 n_msb, n_lsb;
0162     u8 m_msb, m_lsb;
0163     u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
0164 
0165     bool has_stopmode;
0166     bool has_freqsel;
0167     bool has_selfreqdco;
0168     bool has_refsel;
0169 
0170     /* DRA7 errata i886: use high N & M to avoid jitter */
0171     bool errata_i886;
0172 
0173     /* DRA7 errata i932: retry pll lock on failure */
0174     bool errata_i932;
0175 };
0176 
0177 struct dss_pll {
0178     const char *name;
0179     enum dss_pll_id id;
0180     struct dss_device *dss;
0181 
0182     struct clk *clkin;
0183     struct regulator *regulator;
0184 
0185     void __iomem *base;
0186 
0187     const struct dss_pll_hw *hw;
0188 
0189     const struct dss_pll_ops *ops;
0190 
0191     struct dss_pll_clock_info cinfo;
0192 };
0193 
0194 /* Defines a generic omap register field */
0195 struct dss_reg_field {
0196     u8 start, end;
0197 };
0198 
0199 struct dispc_clock_info {
0200     /* rates that we get with dividers below */
0201     unsigned long lck;
0202     unsigned long pck;
0203 
0204     /* dividers */
0205     u16 lck_div;
0206     u16 pck_div;
0207 };
0208 
0209 struct dss_lcd_mgr_config {
0210     enum dss_io_pad_mode io_pad_mode;
0211 
0212     bool stallmode;
0213     bool fifohandcheck;
0214 
0215     struct dispc_clock_info clock_info;
0216 
0217     int video_port_width;
0218 
0219     int lcden_sig_polarity;
0220 };
0221 
0222 #define DSS_SZ_REGS         SZ_512
0223 
0224 struct dss_device {
0225     struct platform_device *pdev;
0226     void __iomem    *base;
0227     struct regmap   *syscon_pll_ctrl;
0228     u32     syscon_pll_ctrl_offset;
0229 
0230     struct platform_device *drm_pdev;
0231 
0232     struct clk  *parent_clk;
0233     struct clk  *dss_clk;
0234     unsigned long   dss_clk_rate;
0235 
0236     unsigned long   cache_req_pck;
0237     unsigned long   cache_prate;
0238     struct dispc_clock_info cache_dispc_cinfo;
0239 
0240     enum dss_clk_source dsi_clk_source[MAX_NUM_DSI];
0241     enum dss_clk_source dispc_clk_source;
0242     enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
0243 
0244     bool        ctx_valid;
0245     u32     ctx[DSS_SZ_REGS / sizeof(u32)];
0246 
0247     const struct dss_features *feat;
0248 
0249     struct {
0250         struct dentry *root;
0251         struct dss_debugfs_entry *clk;
0252         struct dss_debugfs_entry *dss;
0253     } debugfs;
0254 
0255     struct dss_pll *plls[4];
0256     struct dss_pll  *video1_pll;
0257     struct dss_pll  *video2_pll;
0258 
0259     struct dispc_device *dispc;
0260     struct omap_drm_private *mgr_ops_priv;
0261 };
0262 
0263 /* core */
0264 static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput)
0265 {
0266     /* To be implemented when the OMAP platform will provide this feature */
0267     return 0;
0268 }
0269 
0270 static inline bool dss_mgr_is_lcd(enum omap_channel id)
0271 {
0272     if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
0273             id == OMAP_DSS_CHANNEL_LCD3)
0274         return true;
0275     else
0276         return false;
0277 }
0278 
0279 /* DSS */
0280 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
0281 struct dss_debugfs_entry *
0282 dss_debugfs_create_file(struct dss_device *dss, const char *name,
0283             int (*show_fn)(struct seq_file *s, void *data),
0284             void *data);
0285 void dss_debugfs_remove_file(struct dss_debugfs_entry *entry);
0286 #else
0287 static inline struct dss_debugfs_entry *
0288 dss_debugfs_create_file(struct dss_device *dss, const char *name,
0289             int (*show_fn)(struct seq_file *s, void *data),
0290             void *data)
0291 {
0292     return NULL;
0293 }
0294 
0295 static inline void dss_debugfs_remove_file(struct dss_debugfs_entry *entry)
0296 {
0297 }
0298 #endif /* CONFIG_OMAP2_DSS_DEBUGFS */
0299 
0300 struct dss_device *dss_get_device(struct device *dev);
0301 
0302 int dss_runtime_get(struct dss_device *dss);
0303 void dss_runtime_put(struct dss_device *dss);
0304 
0305 unsigned long dss_get_dispc_clk_rate(struct dss_device *dss);
0306 unsigned long dss_get_max_fck_rate(struct dss_device *dss);
0307 int dss_dpi_select_source(struct dss_device *dss, int port,
0308               enum omap_channel channel);
0309 void dss_select_hdmi_venc_clk_source(struct dss_device *dss,
0310                      enum dss_hdmi_venc_clk_source_select src);
0311 const char *dss_get_clk_source_name(enum dss_clk_source clk_src);
0312 
0313 /* DSS VIDEO PLL */
0314 struct dss_pll *dss_video_pll_init(struct dss_device *dss,
0315                    struct platform_device *pdev, int id,
0316                    struct regulator *regulator);
0317 void dss_video_pll_uninit(struct dss_pll *pll);
0318 
0319 void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable);
0320 
0321 void dss_sdi_init(struct dss_device *dss, int datapairs);
0322 int dss_sdi_enable(struct dss_device *dss);
0323 void dss_sdi_disable(struct dss_device *dss);
0324 
0325 void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module,
0326                    enum dss_clk_source clk_src);
0327 void dss_select_lcd_clk_source(struct dss_device *dss,
0328                    enum omap_channel channel,
0329                    enum dss_clk_source clk_src);
0330 enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss);
0331 enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss,
0332                        int dsi_module);
0333 enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss,
0334                        enum omap_channel channel);
0335 
0336 void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type);
0337 void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable);
0338 
0339 int dss_set_fck_rate(struct dss_device *dss, unsigned long rate);
0340 
0341 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
0342 bool dss_div_calc(struct dss_device *dss, unsigned long pck,
0343           unsigned long fck_min, dss_div_calc_func func, void *data);
0344 
0345 /* SDI */
0346 #ifdef CONFIG_OMAP2_DSS_SDI
0347 int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
0348           struct device_node *port);
0349 void sdi_uninit_port(struct device_node *port);
0350 #else
0351 static inline int sdi_init_port(struct dss_device *dss,
0352                 struct platform_device *pdev,
0353                 struct device_node *port)
0354 {
0355     return 0;
0356 }
0357 static inline void sdi_uninit_port(struct device_node *port)
0358 {
0359 }
0360 #endif
0361 
0362 /* DSI */
0363 
0364 #ifdef CONFIG_OMAP2_DSS_DSI
0365 
0366 void dsi_irq_handler(void);
0367 
0368 #endif
0369 
0370 /* DPI */
0371 #ifdef CONFIG_OMAP2_DSS_DPI
0372 int dpi_init_port(struct dss_device *dss, struct platform_device *pdev,
0373           struct device_node *port, enum dss_model dss_model);
0374 void dpi_uninit_port(struct device_node *port);
0375 #else
0376 static inline int dpi_init_port(struct dss_device *dss,
0377                 struct platform_device *pdev,
0378                 struct device_node *port,
0379                 enum dss_model dss_model)
0380 {
0381     return 0;
0382 }
0383 static inline void dpi_uninit_port(struct device_node *port)
0384 {
0385 }
0386 #endif
0387 
0388 /* DISPC */
0389 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s);
0390 
0391 int dispc_runtime_get(struct dispc_device *dispc);
0392 void dispc_runtime_put(struct dispc_device *dispc);
0393 
0394 int dispc_get_num_ovls(struct dispc_device *dispc);
0395 int dispc_get_num_mgrs(struct dispc_device *dispc);
0396 
0397 const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc,
0398                         enum omap_plane_id plane);
0399 
0400 void dispc_ovl_get_max_size(struct dispc_device *dispc, u16 *width, u16 *height);
0401 bool dispc_ovl_color_mode_supported(struct dispc_device *dispc,
0402                     enum omap_plane_id plane, u32 fourcc);
0403 enum omap_overlay_caps dispc_ovl_get_caps(struct dispc_device *dispc, enum omap_plane_id plane);
0404 
0405 u32 dispc_read_irqstatus(struct dispc_device *dispc);
0406 void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask);
0407 void dispc_write_irqenable(struct dispc_device *dispc, u32 mask);
0408 
0409 int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler,
0410                  void *dev_id);
0411 void dispc_free_irq(struct dispc_device *dispc, void *dev_id);
0412 
0413 u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc,
0414                    enum omap_channel channel);
0415 u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc,
0416                        enum omap_channel channel);
0417 u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc,
0418                        enum omap_channel channel);
0419 u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc);
0420 
0421 u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc);
0422 
0423 void dispc_mgr_enable(struct dispc_device *dispc,
0424                  enum omap_channel channel, bool enable);
0425 
0426 bool dispc_mgr_go_busy(struct dispc_device *dispc,
0427                   enum omap_channel channel);
0428 
0429 void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel);
0430 
0431 void dispc_mgr_set_lcd_config(struct dispc_device *dispc,
0432                      enum omap_channel channel,
0433                      const struct dss_lcd_mgr_config *config);
0434 void dispc_mgr_set_timings(struct dispc_device *dispc,
0435                   enum omap_channel channel,
0436                   const struct videomode *vm);
0437 void dispc_mgr_setup(struct dispc_device *dispc,
0438                 enum omap_channel channel,
0439                 const struct omap_overlay_manager_info *info);
0440 
0441 int dispc_mgr_check_timings(struct dispc_device *dispc,
0442                    enum omap_channel channel,
0443                    const struct videomode *vm);
0444 
0445 u32 dispc_mgr_gamma_size(struct dispc_device *dispc,
0446                 enum omap_channel channel);
0447 void dispc_mgr_set_gamma(struct dispc_device *dispc,
0448                 enum omap_channel channel,
0449                 const struct drm_color_lut *lut,
0450                 unsigned int length);
0451 
0452 int dispc_ovl_setup(struct dispc_device *dispc,
0453                enum omap_plane_id plane,
0454                const struct omap_overlay_info *oi,
0455                const struct videomode *vm, bool mem_to_mem,
0456                enum omap_channel channel);
0457 
0458 int dispc_ovl_enable(struct dispc_device *dispc,
0459                 enum omap_plane_id plane, bool enable);
0460 
0461 bool dispc_has_writeback(struct dispc_device *dispc);
0462 int dispc_wb_setup(struct dispc_device *dispc,
0463            const struct omap_dss_writeback_info *wi,
0464            bool mem_to_mem, const struct videomode *vm,
0465            enum dss_writeback_channel channel_in);
0466 bool dispc_wb_go_busy(struct dispc_device *dispc);
0467 void dispc_wb_go(struct dispc_device *dispc);
0468 
0469 void dispc_enable_sidle(struct dispc_device *dispc);
0470 void dispc_disable_sidle(struct dispc_device *dispc);
0471 
0472 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable);
0473 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable);
0474 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable);
0475 
0476 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
0477         unsigned long pck, void *data);
0478 bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq,
0479             unsigned long pck_min, unsigned long pck_max,
0480             dispc_div_calc_func func, void *data);
0481 
0482 int dispc_calc_clock_rates(struct dispc_device *dispc,
0483                unsigned long dispc_fclk_rate,
0484                struct dispc_clock_info *cinfo);
0485 
0486 
0487 void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc,
0488                   enum omap_plane_id plane, u32 low, u32 high);
0489 void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc,
0490                        enum omap_plane_id plane,
0491                        u32 *fifo_low, u32 *fifo_high,
0492                        bool use_fifomerge, bool manual_update);
0493 
0494 void dispc_mgr_set_clock_div(struct dispc_device *dispc,
0495                  enum omap_channel channel,
0496                  const struct dispc_clock_info *cinfo);
0497 int dispc_mgr_get_clock_div(struct dispc_device *dispc,
0498                 enum omap_channel channel,
0499                 struct dispc_clock_info *cinfo);
0500 void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk);
0501 
0502 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
0503 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned int *irq_arr)
0504 {
0505     int b;
0506     for (b = 0; b < 32; ++b) {
0507         if (irqstatus & (1 << b))
0508             irq_arr[b]++;
0509     }
0510 }
0511 #endif
0512 
0513 /* PLL */
0514 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
0515         unsigned long clkdco, void *data);
0516 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
0517         void *data);
0518 
0519 int dss_pll_register(struct dss_device *dss, struct dss_pll *pll);
0520 void dss_pll_unregister(struct dss_pll *pll);
0521 struct dss_pll *dss_pll_find(struct dss_device *dss, const char *name);
0522 struct dss_pll *dss_pll_find_by_src(struct dss_device *dss,
0523                     enum dss_clk_source src);
0524 unsigned int dss_pll_get_clkout_idx_for_src(enum dss_clk_source src);
0525 int dss_pll_enable(struct dss_pll *pll);
0526 void dss_pll_disable(struct dss_pll *pll);
0527 int dss_pll_set_config(struct dss_pll *pll,
0528         const struct dss_pll_clock_info *cinfo);
0529 
0530 bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
0531         unsigned long out_min, unsigned long out_max,
0532         dss_hsdiv_calc_func func, void *data);
0533 bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
0534         unsigned long pll_min, unsigned long pll_max,
0535         dss_pll_calc_func func, void *data);
0536 
0537 bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
0538     unsigned long target_clkout, struct dss_pll_clock_info *cinfo);
0539 
0540 int dss_pll_write_config_type_a(struct dss_pll *pll,
0541         const struct dss_pll_clock_info *cinfo);
0542 int dss_pll_write_config_type_b(struct dss_pll *pll,
0543         const struct dss_pll_clock_info *cinfo);
0544 int dss_pll_wait_reset_done(struct dss_pll *pll);
0545 
0546 extern struct platform_driver omap_dsshw_driver;
0547 extern struct platform_driver omap_dispchw_driver;
0548 #ifdef CONFIG_OMAP2_DSS_DSI
0549 extern struct platform_driver omap_dsihw_driver;
0550 #endif
0551 #ifdef CONFIG_OMAP2_DSS_VENC
0552 extern struct platform_driver omap_venchw_driver;
0553 #endif
0554 #ifdef CONFIG_OMAP4_DSS_HDMI
0555 extern struct platform_driver omapdss_hdmi4hw_driver;
0556 #endif
0557 #ifdef CONFIG_OMAP5_DSS_HDMI
0558 extern struct platform_driver omapdss_hdmi5hw_driver;
0559 #endif
0560 
0561 #endif
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