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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2009 Nokia Corporation
0004  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
0005  *
0006  * Some code and ideas taken from drivers/video/omap/ driver
0007  * by Imre Deak.
0008  */
0009 
0010 #define DSS_SUBSYS_NAME "DSS"
0011 
0012 #include <linux/debugfs.h>
0013 #include <linux/dma-mapping.h>
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/io.h>
0017 #include <linux/export.h>
0018 #include <linux/err.h>
0019 #include <linux/delay.h>
0020 #include <linux/seq_file.h>
0021 #include <linux/clk.h>
0022 #include <linux/pinctrl/consumer.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/pm_runtime.h>
0025 #include <linux/gfp.h>
0026 #include <linux/sizes.h>
0027 #include <linux/mfd/syscon.h>
0028 #include <linux/regmap.h>
0029 #include <linux/of.h>
0030 #include <linux/of_device.h>
0031 #include <linux/of_graph.h>
0032 #include <linux/regulator/consumer.h>
0033 #include <linux/suspend.h>
0034 #include <linux/component.h>
0035 #include <linux/sys_soc.h>
0036 
0037 #include "omapdss.h"
0038 #include "dss.h"
0039 
0040 struct dss_reg {
0041     u16 idx;
0042 };
0043 
0044 #define DSS_REG(idx)            ((const struct dss_reg) { idx })
0045 
0046 #define DSS_REVISION            DSS_REG(0x0000)
0047 #define DSS_SYSCONFIG           DSS_REG(0x0010)
0048 #define DSS_SYSSTATUS           DSS_REG(0x0014)
0049 #define DSS_CONTROL         DSS_REG(0x0040)
0050 #define DSS_SDI_CONTROL         DSS_REG(0x0044)
0051 #define DSS_PLL_CONTROL         DSS_REG(0x0048)
0052 #define DSS_SDI_STATUS          DSS_REG(0x005C)
0053 
0054 #define REG_GET(dss, idx, start, end) \
0055     FLD_GET(dss_read_reg(dss, idx), start, end)
0056 
0057 #define REG_FLD_MOD(dss, idx, val, start, end) \
0058     dss_write_reg(dss, idx, \
0059               FLD_MOD(dss_read_reg(dss, idx), val, start, end))
0060 
0061 struct dss_ops {
0062     int (*dpi_select_source)(struct dss_device *dss, int port,
0063                  enum omap_channel channel);
0064     int (*select_lcd_source)(struct dss_device *dss,
0065                  enum omap_channel channel,
0066                  enum dss_clk_source clk_src);
0067 };
0068 
0069 struct dss_features {
0070     enum dss_model model;
0071     u8 fck_div_max;
0072     unsigned int fck_freq_max;
0073     u8 dss_fck_multiplier;
0074     const char *parent_clk_name;
0075     const enum omap_display_type *ports;
0076     int num_ports;
0077     const enum omap_dss_output_id *outputs;
0078     const struct dss_ops *ops;
0079     struct dss_reg_field dispc_clk_switch;
0080     bool has_lcd_clk_src;
0081 };
0082 
0083 static const char * const dss_generic_clk_source_names[] = {
0084     [DSS_CLK_SRC_FCK]   = "FCK",
0085     [DSS_CLK_SRC_PLL1_1]    = "PLL1:1",
0086     [DSS_CLK_SRC_PLL1_2]    = "PLL1:2",
0087     [DSS_CLK_SRC_PLL1_3]    = "PLL1:3",
0088     [DSS_CLK_SRC_PLL2_1]    = "PLL2:1",
0089     [DSS_CLK_SRC_PLL2_2]    = "PLL2:2",
0090     [DSS_CLK_SRC_PLL2_3]    = "PLL2:3",
0091     [DSS_CLK_SRC_HDMI_PLL]  = "HDMI PLL",
0092 };
0093 
0094 static inline void dss_write_reg(struct dss_device *dss,
0095                  const struct dss_reg idx, u32 val)
0096 {
0097     __raw_writel(val, dss->base + idx.idx);
0098 }
0099 
0100 static inline u32 dss_read_reg(struct dss_device *dss, const struct dss_reg idx)
0101 {
0102     return __raw_readl(dss->base + idx.idx);
0103 }
0104 
0105 #define SR(dss, reg) \
0106     dss->ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(dss, DSS_##reg)
0107 #define RR(dss, reg) \
0108     dss_write_reg(dss, DSS_##reg, dss->ctx[(DSS_##reg).idx / sizeof(u32)])
0109 
0110 static void dss_save_context(struct dss_device *dss)
0111 {
0112     DSSDBG("dss_save_context\n");
0113 
0114     SR(dss, CONTROL);
0115 
0116     if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
0117         SR(dss, SDI_CONTROL);
0118         SR(dss, PLL_CONTROL);
0119     }
0120 
0121     dss->ctx_valid = true;
0122 
0123     DSSDBG("context saved\n");
0124 }
0125 
0126 static void dss_restore_context(struct dss_device *dss)
0127 {
0128     DSSDBG("dss_restore_context\n");
0129 
0130     if (!dss->ctx_valid)
0131         return;
0132 
0133     RR(dss, CONTROL);
0134 
0135     if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
0136         RR(dss, SDI_CONTROL);
0137         RR(dss, PLL_CONTROL);
0138     }
0139 
0140     DSSDBG("context restored\n");
0141 }
0142 
0143 #undef SR
0144 #undef RR
0145 
0146 void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable)
0147 {
0148     unsigned int shift;
0149     unsigned int val;
0150 
0151     if (!pll->dss->syscon_pll_ctrl)
0152         return;
0153 
0154     val = !enable;
0155 
0156     switch (pll->id) {
0157     case DSS_PLL_VIDEO1:
0158         shift = 0;
0159         break;
0160     case DSS_PLL_VIDEO2:
0161         shift = 1;
0162         break;
0163     case DSS_PLL_HDMI:
0164         shift = 2;
0165         break;
0166     default:
0167         DSSERR("illegal DSS PLL ID %d\n", pll->id);
0168         return;
0169     }
0170 
0171     regmap_update_bits(pll->dss->syscon_pll_ctrl,
0172                pll->dss->syscon_pll_ctrl_offset,
0173                1 << shift, val << shift);
0174 }
0175 
0176 static int dss_ctrl_pll_set_control_mux(struct dss_device *dss,
0177                     enum dss_clk_source clk_src,
0178                     enum omap_channel channel)
0179 {
0180     unsigned int shift, val;
0181 
0182     if (!dss->syscon_pll_ctrl)
0183         return -EINVAL;
0184 
0185     switch (channel) {
0186     case OMAP_DSS_CHANNEL_LCD:
0187         shift = 3;
0188 
0189         switch (clk_src) {
0190         case DSS_CLK_SRC_PLL1_1:
0191             val = 0; break;
0192         case DSS_CLK_SRC_HDMI_PLL:
0193             val = 1; break;
0194         default:
0195             DSSERR("error in PLL mux config for LCD\n");
0196             return -EINVAL;
0197         }
0198 
0199         break;
0200     case OMAP_DSS_CHANNEL_LCD2:
0201         shift = 5;
0202 
0203         switch (clk_src) {
0204         case DSS_CLK_SRC_PLL1_3:
0205             val = 0; break;
0206         case DSS_CLK_SRC_PLL2_3:
0207             val = 1; break;
0208         case DSS_CLK_SRC_HDMI_PLL:
0209             val = 2; break;
0210         default:
0211             DSSERR("error in PLL mux config for LCD2\n");
0212             return -EINVAL;
0213         }
0214 
0215         break;
0216     case OMAP_DSS_CHANNEL_LCD3:
0217         shift = 7;
0218 
0219         switch (clk_src) {
0220         case DSS_CLK_SRC_PLL2_1:
0221             val = 0; break;
0222         case DSS_CLK_SRC_PLL1_3:
0223             val = 1; break;
0224         case DSS_CLK_SRC_HDMI_PLL:
0225             val = 2; break;
0226         default:
0227             DSSERR("error in PLL mux config for LCD3\n");
0228             return -EINVAL;
0229         }
0230 
0231         break;
0232     default:
0233         DSSERR("error in PLL mux config\n");
0234         return -EINVAL;
0235     }
0236 
0237     regmap_update_bits(dss->syscon_pll_ctrl, dss->syscon_pll_ctrl_offset,
0238         0x3 << shift, val << shift);
0239 
0240     return 0;
0241 }
0242 
0243 void dss_sdi_init(struct dss_device *dss, int datapairs)
0244 {
0245     u32 l;
0246 
0247     BUG_ON(datapairs > 3 || datapairs < 1);
0248 
0249     l = dss_read_reg(dss, DSS_SDI_CONTROL);
0250     l = FLD_MOD(l, 0xf, 19, 15);        /* SDI_PDIV */
0251     l = FLD_MOD(l, datapairs-1, 3, 2);  /* SDI_PRSEL */
0252     l = FLD_MOD(l, 2, 1, 0);        /* SDI_BWSEL */
0253     dss_write_reg(dss, DSS_SDI_CONTROL, l);
0254 
0255     l = dss_read_reg(dss, DSS_PLL_CONTROL);
0256     l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
0257     l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
0258     l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
0259     dss_write_reg(dss, DSS_PLL_CONTROL, l);
0260 }
0261 
0262 int dss_sdi_enable(struct dss_device *dss)
0263 {
0264     unsigned long timeout;
0265 
0266     dispc_pck_free_enable(dss->dispc, 1);
0267 
0268     /* Reset SDI PLL */
0269     REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
0270     udelay(1);  /* wait 2x PCLK */
0271 
0272     /* Lock SDI PLL */
0273     REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
0274 
0275     /* Waiting for PLL lock request to complete */
0276     timeout = jiffies + msecs_to_jiffies(500);
0277     while (dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 6)) {
0278         if (time_after_eq(jiffies, timeout)) {
0279             DSSERR("PLL lock request timed out\n");
0280             goto err1;
0281         }
0282     }
0283 
0284     /* Clearing PLL_GO bit */
0285     REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 28, 28);
0286 
0287     /* Waiting for PLL to lock */
0288     timeout = jiffies + msecs_to_jiffies(500);
0289     while (!(dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 5))) {
0290         if (time_after_eq(jiffies, timeout)) {
0291             DSSERR("PLL lock timed out\n");
0292             goto err1;
0293         }
0294     }
0295 
0296     dispc_lcd_enable_signal(dss->dispc, 1);
0297 
0298     /* Waiting for SDI reset to complete */
0299     timeout = jiffies + msecs_to_jiffies(500);
0300     while (!(dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 2))) {
0301         if (time_after_eq(jiffies, timeout)) {
0302             DSSERR("SDI reset timed out\n");
0303             goto err2;
0304         }
0305     }
0306 
0307     return 0;
0308 
0309  err2:
0310     dispc_lcd_enable_signal(dss->dispc, 0);
0311  err1:
0312     /* Reset SDI PLL */
0313     REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
0314 
0315     dispc_pck_free_enable(dss->dispc, 0);
0316 
0317     return -ETIMEDOUT;
0318 }
0319 
0320 void dss_sdi_disable(struct dss_device *dss)
0321 {
0322     dispc_lcd_enable_signal(dss->dispc, 0);
0323 
0324     dispc_pck_free_enable(dss->dispc, 0);
0325 
0326     /* Reset SDI PLL */
0327     REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
0328 }
0329 
0330 const char *dss_get_clk_source_name(enum dss_clk_source clk_src)
0331 {
0332     return dss_generic_clk_source_names[clk_src];
0333 }
0334 
0335 static void dss_dump_clocks(struct dss_device *dss, struct seq_file *s)
0336 {
0337     const char *fclk_name;
0338     unsigned long fclk_rate;
0339 
0340     if (dss_runtime_get(dss))
0341         return;
0342 
0343     seq_printf(s, "- DSS -\n");
0344 
0345     fclk_name = dss_get_clk_source_name(DSS_CLK_SRC_FCK);
0346     fclk_rate = clk_get_rate(dss->dss_clk);
0347 
0348     seq_printf(s, "%s = %lu\n",
0349             fclk_name,
0350             fclk_rate);
0351 
0352     dss_runtime_put(dss);
0353 }
0354 
0355 static int dss_dump_regs(struct seq_file *s, void *p)
0356 {
0357     struct dss_device *dss = s->private;
0358 
0359 #define DUMPREG(dss, r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(dss, r))
0360 
0361     if (dss_runtime_get(dss))
0362         return 0;
0363 
0364     DUMPREG(dss, DSS_REVISION);
0365     DUMPREG(dss, DSS_SYSCONFIG);
0366     DUMPREG(dss, DSS_SYSSTATUS);
0367     DUMPREG(dss, DSS_CONTROL);
0368 
0369     if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
0370         DUMPREG(dss, DSS_SDI_CONTROL);
0371         DUMPREG(dss, DSS_PLL_CONTROL);
0372         DUMPREG(dss, DSS_SDI_STATUS);
0373     }
0374 
0375     dss_runtime_put(dss);
0376 #undef DUMPREG
0377     return 0;
0378 }
0379 
0380 static int dss_debug_dump_clocks(struct seq_file *s, void *p)
0381 {
0382     struct dss_device *dss = s->private;
0383 
0384     dss_dump_clocks(dss, s);
0385     dispc_dump_clocks(dss->dispc, s);
0386     return 0;
0387 }
0388 
0389 static int dss_get_channel_index(enum omap_channel channel)
0390 {
0391     switch (channel) {
0392     case OMAP_DSS_CHANNEL_LCD:
0393         return 0;
0394     case OMAP_DSS_CHANNEL_LCD2:
0395         return 1;
0396     case OMAP_DSS_CHANNEL_LCD3:
0397         return 2;
0398     default:
0399         WARN_ON(1);
0400         return 0;
0401     }
0402 }
0403 
0404 static void dss_select_dispc_clk_source(struct dss_device *dss,
0405                     enum dss_clk_source clk_src)
0406 {
0407     int b;
0408 
0409     /*
0410      * We always use PRCM clock as the DISPC func clock, except on DSS3,
0411      * where we don't have separate DISPC and LCD clock sources.
0412      */
0413     if (WARN_ON(dss->feat->has_lcd_clk_src && clk_src != DSS_CLK_SRC_FCK))
0414         return;
0415 
0416     switch (clk_src) {
0417     case DSS_CLK_SRC_FCK:
0418         b = 0;
0419         break;
0420     case DSS_CLK_SRC_PLL1_1:
0421         b = 1;
0422         break;
0423     case DSS_CLK_SRC_PLL2_1:
0424         b = 2;
0425         break;
0426     default:
0427         BUG();
0428         return;
0429     }
0430 
0431     REG_FLD_MOD(dss, DSS_CONTROL, b,        /* DISPC_CLK_SWITCH */
0432             dss->feat->dispc_clk_switch.start,
0433             dss->feat->dispc_clk_switch.end);
0434 
0435     dss->dispc_clk_source = clk_src;
0436 }
0437 
0438 void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module,
0439                    enum dss_clk_source clk_src)
0440 {
0441     int b, pos;
0442 
0443     switch (clk_src) {
0444     case DSS_CLK_SRC_FCK:
0445         b = 0;
0446         break;
0447     case DSS_CLK_SRC_PLL1_2:
0448         BUG_ON(dsi_module != 0);
0449         b = 1;
0450         break;
0451     case DSS_CLK_SRC_PLL2_2:
0452         BUG_ON(dsi_module != 1);
0453         b = 1;
0454         break;
0455     default:
0456         BUG();
0457         return;
0458     }
0459 
0460     pos = dsi_module == 0 ? 1 : 10;
0461     REG_FLD_MOD(dss, DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */
0462 
0463     dss->dsi_clk_source[dsi_module] = clk_src;
0464 }
0465 
0466 static int dss_lcd_clk_mux_dra7(struct dss_device *dss,
0467                 enum omap_channel channel,
0468                 enum dss_clk_source clk_src)
0469 {
0470     const u8 ctrl_bits[] = {
0471         [OMAP_DSS_CHANNEL_LCD] = 0,
0472         [OMAP_DSS_CHANNEL_LCD2] = 12,
0473         [OMAP_DSS_CHANNEL_LCD3] = 19,
0474     };
0475 
0476     u8 ctrl_bit = ctrl_bits[channel];
0477     int r;
0478 
0479     if (clk_src == DSS_CLK_SRC_FCK) {
0480         /* LCDx_CLK_SWITCH */
0481         REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
0482         return -EINVAL;
0483     }
0484 
0485     r = dss_ctrl_pll_set_control_mux(dss, clk_src, channel);
0486     if (r)
0487         return r;
0488 
0489     REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
0490 
0491     return 0;
0492 }
0493 
0494 static int dss_lcd_clk_mux_omap5(struct dss_device *dss,
0495                  enum omap_channel channel,
0496                  enum dss_clk_source clk_src)
0497 {
0498     const u8 ctrl_bits[] = {
0499         [OMAP_DSS_CHANNEL_LCD] = 0,
0500         [OMAP_DSS_CHANNEL_LCD2] = 12,
0501         [OMAP_DSS_CHANNEL_LCD3] = 19,
0502     };
0503     const enum dss_clk_source allowed_plls[] = {
0504         [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1,
0505         [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_FCK,
0506         [OMAP_DSS_CHANNEL_LCD3] = DSS_CLK_SRC_PLL2_1,
0507     };
0508 
0509     u8 ctrl_bit = ctrl_bits[channel];
0510 
0511     if (clk_src == DSS_CLK_SRC_FCK) {
0512         /* LCDx_CLK_SWITCH */
0513         REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
0514         return -EINVAL;
0515     }
0516 
0517     if (WARN_ON(allowed_plls[channel] != clk_src))
0518         return -EINVAL;
0519 
0520     REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
0521 
0522     return 0;
0523 }
0524 
0525 static int dss_lcd_clk_mux_omap4(struct dss_device *dss,
0526                  enum omap_channel channel,
0527                  enum dss_clk_source clk_src)
0528 {
0529     const u8 ctrl_bits[] = {
0530         [OMAP_DSS_CHANNEL_LCD] = 0,
0531         [OMAP_DSS_CHANNEL_LCD2] = 12,
0532     };
0533     const enum dss_clk_source allowed_plls[] = {
0534         [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1,
0535         [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_PLL2_1,
0536     };
0537 
0538     u8 ctrl_bit = ctrl_bits[channel];
0539 
0540     if (clk_src == DSS_CLK_SRC_FCK) {
0541         /* LCDx_CLK_SWITCH */
0542         REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
0543         return 0;
0544     }
0545 
0546     if (WARN_ON(allowed_plls[channel] != clk_src))
0547         return -EINVAL;
0548 
0549     REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
0550 
0551     return 0;
0552 }
0553 
0554 void dss_select_lcd_clk_source(struct dss_device *dss,
0555                    enum omap_channel channel,
0556                    enum dss_clk_source clk_src)
0557 {
0558     int idx = dss_get_channel_index(channel);
0559     int r;
0560 
0561     if (!dss->feat->has_lcd_clk_src) {
0562         dss_select_dispc_clk_source(dss, clk_src);
0563         dss->lcd_clk_source[idx] = clk_src;
0564         return;
0565     }
0566 
0567     r = dss->feat->ops->select_lcd_source(dss, channel, clk_src);
0568     if (r)
0569         return;
0570 
0571     dss->lcd_clk_source[idx] = clk_src;
0572 }
0573 
0574 enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss)
0575 {
0576     return dss->dispc_clk_source;
0577 }
0578 
0579 enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss,
0580                        int dsi_module)
0581 {
0582     return dss->dsi_clk_source[dsi_module];
0583 }
0584 
0585 enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss,
0586                        enum omap_channel channel)
0587 {
0588     if (dss->feat->has_lcd_clk_src) {
0589         int idx = dss_get_channel_index(channel);
0590         return dss->lcd_clk_source[idx];
0591     } else {
0592         /* LCD_CLK source is the same as DISPC_FCLK source for
0593          * OMAP2 and OMAP3 */
0594         return dss->dispc_clk_source;
0595     }
0596 }
0597 
0598 bool dss_div_calc(struct dss_device *dss, unsigned long pck,
0599           unsigned long fck_min, dss_div_calc_func func, void *data)
0600 {
0601     int fckd, fckd_start, fckd_stop;
0602     unsigned long fck;
0603     unsigned long fck_hw_max;
0604     unsigned long fckd_hw_max;
0605     unsigned long prate;
0606     unsigned int m;
0607 
0608     fck_hw_max = dss->feat->fck_freq_max;
0609 
0610     if (dss->parent_clk == NULL) {
0611         unsigned int pckd;
0612 
0613         pckd = fck_hw_max / pck;
0614 
0615         fck = pck * pckd;
0616 
0617         fck = clk_round_rate(dss->dss_clk, fck);
0618 
0619         return func(fck, data);
0620     }
0621 
0622     fckd_hw_max = dss->feat->fck_div_max;
0623 
0624     m = dss->feat->dss_fck_multiplier;
0625     prate = clk_get_rate(dss->parent_clk);
0626 
0627     fck_min = fck_min ? fck_min : 1;
0628 
0629     fckd_start = min(prate * m / fck_min, fckd_hw_max);
0630     fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
0631 
0632     for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
0633         fck = DIV_ROUND_UP(prate, fckd) * m;
0634 
0635         if (func(fck, data))
0636             return true;
0637     }
0638 
0639     return false;
0640 }
0641 
0642 int dss_set_fck_rate(struct dss_device *dss, unsigned long rate)
0643 {
0644     int r;
0645 
0646     DSSDBG("set fck to %lu\n", rate);
0647 
0648     r = clk_set_rate(dss->dss_clk, rate);
0649     if (r)
0650         return r;
0651 
0652     dss->dss_clk_rate = clk_get_rate(dss->dss_clk);
0653 
0654     WARN_ONCE(dss->dss_clk_rate != rate, "clk rate mismatch: %lu != %lu",
0655           dss->dss_clk_rate, rate);
0656 
0657     return 0;
0658 }
0659 
0660 unsigned long dss_get_dispc_clk_rate(struct dss_device *dss)
0661 {
0662     return dss->dss_clk_rate;
0663 }
0664 
0665 unsigned long dss_get_max_fck_rate(struct dss_device *dss)
0666 {
0667     return dss->feat->fck_freq_max;
0668 }
0669 
0670 static int dss_setup_default_clock(struct dss_device *dss)
0671 {
0672     unsigned long max_dss_fck, prate;
0673     unsigned long fck;
0674     unsigned int fck_div;
0675     int r;
0676 
0677     max_dss_fck = dss->feat->fck_freq_max;
0678 
0679     if (dss->parent_clk == NULL) {
0680         fck = clk_round_rate(dss->dss_clk, max_dss_fck);
0681     } else {
0682         prate = clk_get_rate(dss->parent_clk);
0683 
0684         fck_div = DIV_ROUND_UP(prate * dss->feat->dss_fck_multiplier,
0685                 max_dss_fck);
0686         fck = DIV_ROUND_UP(prate, fck_div)
0687             * dss->feat->dss_fck_multiplier;
0688     }
0689 
0690     r = dss_set_fck_rate(dss, fck);
0691     if (r)
0692         return r;
0693 
0694     return 0;
0695 }
0696 
0697 void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type)
0698 {
0699     int l = 0;
0700 
0701     if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
0702         l = 0;
0703     else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
0704         l = 1;
0705     else
0706         BUG();
0707 
0708     /* venc out selection. 0 = comp, 1 = svideo */
0709     REG_FLD_MOD(dss, DSS_CONTROL, l, 6, 6);
0710 }
0711 
0712 void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable)
0713 {
0714     /* DAC Power-Down Control */
0715     REG_FLD_MOD(dss, DSS_CONTROL, enable, 5, 5);
0716 }
0717 
0718 void dss_select_hdmi_venc_clk_source(struct dss_device *dss,
0719                      enum dss_hdmi_venc_clk_source_select src)
0720 {
0721     enum omap_dss_output_id outputs;
0722 
0723     outputs = dss->feat->outputs[OMAP_DSS_CHANNEL_DIGIT];
0724 
0725     /* Complain about invalid selections */
0726     WARN_ON((src == DSS_VENC_TV_CLK) && !(outputs & OMAP_DSS_OUTPUT_VENC));
0727     WARN_ON((src == DSS_HDMI_M_PCLK) && !(outputs & OMAP_DSS_OUTPUT_HDMI));
0728 
0729     /* Select only if we have options */
0730     if ((outputs & OMAP_DSS_OUTPUT_VENC) &&
0731         (outputs & OMAP_DSS_OUTPUT_HDMI))
0732         /* VENC_HDMI_SWITCH */
0733         REG_FLD_MOD(dss, DSS_CONTROL, src, 15, 15);
0734 }
0735 
0736 static int dss_dpi_select_source_omap2_omap3(struct dss_device *dss, int port,
0737                          enum omap_channel channel)
0738 {
0739     if (channel != OMAP_DSS_CHANNEL_LCD)
0740         return -EINVAL;
0741 
0742     return 0;
0743 }
0744 
0745 static int dss_dpi_select_source_omap4(struct dss_device *dss, int port,
0746                        enum omap_channel channel)
0747 {
0748     int val;
0749 
0750     switch (channel) {
0751     case OMAP_DSS_CHANNEL_LCD2:
0752         val = 0;
0753         break;
0754     case OMAP_DSS_CHANNEL_DIGIT:
0755         val = 1;
0756         break;
0757     default:
0758         return -EINVAL;
0759     }
0760 
0761     REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 17);
0762 
0763     return 0;
0764 }
0765 
0766 static int dss_dpi_select_source_omap5(struct dss_device *dss, int port,
0767                        enum omap_channel channel)
0768 {
0769     int val;
0770 
0771     switch (channel) {
0772     case OMAP_DSS_CHANNEL_LCD:
0773         val = 1;
0774         break;
0775     case OMAP_DSS_CHANNEL_LCD2:
0776         val = 2;
0777         break;
0778     case OMAP_DSS_CHANNEL_LCD3:
0779         val = 3;
0780         break;
0781     case OMAP_DSS_CHANNEL_DIGIT:
0782         val = 0;
0783         break;
0784     default:
0785         return -EINVAL;
0786     }
0787 
0788     REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 16);
0789 
0790     return 0;
0791 }
0792 
0793 static int dss_dpi_select_source_dra7xx(struct dss_device *dss, int port,
0794                     enum omap_channel channel)
0795 {
0796     switch (port) {
0797     case 0:
0798         return dss_dpi_select_source_omap5(dss, port, channel);
0799     case 1:
0800         if (channel != OMAP_DSS_CHANNEL_LCD2)
0801             return -EINVAL;
0802         break;
0803     case 2:
0804         if (channel != OMAP_DSS_CHANNEL_LCD3)
0805             return -EINVAL;
0806         break;
0807     default:
0808         return -EINVAL;
0809     }
0810 
0811     return 0;
0812 }
0813 
0814 int dss_dpi_select_source(struct dss_device *dss, int port,
0815               enum omap_channel channel)
0816 {
0817     return dss->feat->ops->dpi_select_source(dss, port, channel);
0818 }
0819 
0820 static int dss_get_clocks(struct dss_device *dss)
0821 {
0822     struct clk *clk;
0823 
0824     clk = devm_clk_get(&dss->pdev->dev, "fck");
0825     if (IS_ERR(clk)) {
0826         DSSERR("can't get clock fck\n");
0827         return PTR_ERR(clk);
0828     }
0829 
0830     dss->dss_clk = clk;
0831 
0832     if (dss->feat->parent_clk_name) {
0833         clk = clk_get(NULL, dss->feat->parent_clk_name);
0834         if (IS_ERR(clk)) {
0835             DSSERR("Failed to get %s\n",
0836                    dss->feat->parent_clk_name);
0837             return PTR_ERR(clk);
0838         }
0839     } else {
0840         clk = NULL;
0841     }
0842 
0843     dss->parent_clk = clk;
0844 
0845     return 0;
0846 }
0847 
0848 static void dss_put_clocks(struct dss_device *dss)
0849 {
0850     if (dss->parent_clk)
0851         clk_put(dss->parent_clk);
0852 }
0853 
0854 int dss_runtime_get(struct dss_device *dss)
0855 {
0856     int r;
0857 
0858     DSSDBG("dss_runtime_get\n");
0859 
0860     r = pm_runtime_get_sync(&dss->pdev->dev);
0861     if (WARN_ON(r < 0)) {
0862         pm_runtime_put_noidle(&dss->pdev->dev);
0863         return r;
0864     }
0865     return 0;
0866 }
0867 
0868 void dss_runtime_put(struct dss_device *dss)
0869 {
0870     int r;
0871 
0872     DSSDBG("dss_runtime_put\n");
0873 
0874     r = pm_runtime_put_sync(&dss->pdev->dev);
0875     WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
0876 }
0877 
0878 struct dss_device *dss_get_device(struct device *dev)
0879 {
0880     return dev_get_drvdata(dev);
0881 }
0882 
0883 /* DEBUGFS */
0884 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
0885 static int dss_initialize_debugfs(struct dss_device *dss)
0886 {
0887     struct dentry *dir;
0888 
0889     dir = debugfs_create_dir("omapdss", NULL);
0890     if (IS_ERR(dir))
0891         return PTR_ERR(dir);
0892 
0893     dss->debugfs.root = dir;
0894 
0895     return 0;
0896 }
0897 
0898 static void dss_uninitialize_debugfs(struct dss_device *dss)
0899 {
0900     debugfs_remove_recursive(dss->debugfs.root);
0901 }
0902 
0903 struct dss_debugfs_entry {
0904     struct dentry *dentry;
0905     int (*show_fn)(struct seq_file *s, void *data);
0906     void *data;
0907 };
0908 
0909 static int dss_debug_open(struct inode *inode, struct file *file)
0910 {
0911     struct dss_debugfs_entry *entry = inode->i_private;
0912 
0913     return single_open(file, entry->show_fn, entry->data);
0914 }
0915 
0916 static const struct file_operations dss_debug_fops = {
0917     .open       = dss_debug_open,
0918     .read       = seq_read,
0919     .llseek     = seq_lseek,
0920     .release    = single_release,
0921 };
0922 
0923 struct dss_debugfs_entry *
0924 dss_debugfs_create_file(struct dss_device *dss, const char *name,
0925             int (*show_fn)(struct seq_file *s, void *data),
0926             void *data)
0927 {
0928     struct dss_debugfs_entry *entry;
0929 
0930     entry = kzalloc(sizeof(*entry), GFP_KERNEL);
0931     if (!entry)
0932         return ERR_PTR(-ENOMEM);
0933 
0934     entry->show_fn = show_fn;
0935     entry->data = data;
0936     entry->dentry = debugfs_create_file(name, 0444, dss->debugfs.root,
0937                         entry, &dss_debug_fops);
0938 
0939     return entry;
0940 }
0941 
0942 void dss_debugfs_remove_file(struct dss_debugfs_entry *entry)
0943 {
0944     if (IS_ERR_OR_NULL(entry))
0945         return;
0946 
0947     debugfs_remove(entry->dentry);
0948     kfree(entry);
0949 }
0950 
0951 #else /* CONFIG_OMAP2_DSS_DEBUGFS */
0952 static inline int dss_initialize_debugfs(struct dss_device *dss)
0953 {
0954     return 0;
0955 }
0956 static inline void dss_uninitialize_debugfs(struct dss_device *dss)
0957 {
0958 }
0959 #endif /* CONFIG_OMAP2_DSS_DEBUGFS */
0960 
0961 static const struct dss_ops dss_ops_omap2_omap3 = {
0962     .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
0963 };
0964 
0965 static const struct dss_ops dss_ops_omap4 = {
0966     .dpi_select_source = &dss_dpi_select_source_omap4,
0967     .select_lcd_source = &dss_lcd_clk_mux_omap4,
0968 };
0969 
0970 static const struct dss_ops dss_ops_omap5 = {
0971     .dpi_select_source = &dss_dpi_select_source_omap5,
0972     .select_lcd_source = &dss_lcd_clk_mux_omap5,
0973 };
0974 
0975 static const struct dss_ops dss_ops_dra7 = {
0976     .dpi_select_source = &dss_dpi_select_source_dra7xx,
0977     .select_lcd_source = &dss_lcd_clk_mux_dra7,
0978 };
0979 
0980 static const enum omap_display_type omap2plus_ports[] = {
0981     OMAP_DISPLAY_TYPE_DPI,
0982 };
0983 
0984 static const enum omap_display_type omap34xx_ports[] = {
0985     OMAP_DISPLAY_TYPE_DPI,
0986     OMAP_DISPLAY_TYPE_SDI,
0987 };
0988 
0989 static const enum omap_display_type dra7xx_ports[] = {
0990     OMAP_DISPLAY_TYPE_DPI,
0991     OMAP_DISPLAY_TYPE_DPI,
0992     OMAP_DISPLAY_TYPE_DPI,
0993 };
0994 
0995 static const enum omap_dss_output_id omap2_dss_supported_outputs[] = {
0996     /* OMAP_DSS_CHANNEL_LCD */
0997     OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
0998 
0999     /* OMAP_DSS_CHANNEL_DIGIT */
1000     OMAP_DSS_OUTPUT_VENC,
1001 };
1002 
1003 static const enum omap_dss_output_id omap3430_dss_supported_outputs[] = {
1004     /* OMAP_DSS_CHANNEL_LCD */
1005     OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1006     OMAP_DSS_OUTPUT_SDI | OMAP_DSS_OUTPUT_DSI1,
1007 
1008     /* OMAP_DSS_CHANNEL_DIGIT */
1009     OMAP_DSS_OUTPUT_VENC,
1010 };
1011 
1012 static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = {
1013     /* OMAP_DSS_CHANNEL_LCD */
1014     OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1015     OMAP_DSS_OUTPUT_DSI1,
1016 
1017     /* OMAP_DSS_CHANNEL_DIGIT */
1018     OMAP_DSS_OUTPUT_VENC,
1019 };
1020 
1021 static const enum omap_dss_output_id am43xx_dss_supported_outputs[] = {
1022     /* OMAP_DSS_CHANNEL_LCD */
1023     OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
1024 };
1025 
1026 static const enum omap_dss_output_id omap4_dss_supported_outputs[] = {
1027     /* OMAP_DSS_CHANNEL_LCD */
1028     OMAP_DSS_OUTPUT_DBI | OMAP_DSS_OUTPUT_DSI1,
1029 
1030     /* OMAP_DSS_CHANNEL_DIGIT */
1031     OMAP_DSS_OUTPUT_VENC | OMAP_DSS_OUTPUT_HDMI,
1032 
1033     /* OMAP_DSS_CHANNEL_LCD2 */
1034     OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1035     OMAP_DSS_OUTPUT_DSI2,
1036 };
1037 
1038 static const enum omap_dss_output_id omap5_dss_supported_outputs[] = {
1039     /* OMAP_DSS_CHANNEL_LCD */
1040     OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1041     OMAP_DSS_OUTPUT_DSI1 | OMAP_DSS_OUTPUT_DSI2,
1042 
1043     /* OMAP_DSS_CHANNEL_DIGIT */
1044     OMAP_DSS_OUTPUT_HDMI,
1045 
1046     /* OMAP_DSS_CHANNEL_LCD2 */
1047     OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1048     OMAP_DSS_OUTPUT_DSI1,
1049 
1050     /* OMAP_DSS_CHANNEL_LCD3 */
1051     OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
1052     OMAP_DSS_OUTPUT_DSI2,
1053 };
1054 
1055 static const struct dss_features omap24xx_dss_feats = {
1056     .model          =   DSS_MODEL_OMAP2,
1057     /*
1058      * fck div max is really 16, but the divider range has gaps. The range
1059      * from 1 to 6 has no gaps, so let's use that as a max.
1060      */
1061     .fck_div_max        =   6,
1062     .fck_freq_max       =   133000000,
1063     .dss_fck_multiplier =   2,
1064     .parent_clk_name    =   "core_ck",
1065     .ports          =   omap2plus_ports,
1066     .num_ports      =   ARRAY_SIZE(omap2plus_ports),
1067     .outputs        =   omap2_dss_supported_outputs,
1068     .ops            =   &dss_ops_omap2_omap3,
1069     .dispc_clk_switch   =   { 0, 0 },
1070     .has_lcd_clk_src    =   false,
1071 };
1072 
1073 static const struct dss_features omap34xx_dss_feats = {
1074     .model          =   DSS_MODEL_OMAP3,
1075     .fck_div_max        =   16,
1076     .fck_freq_max       =   173000000,
1077     .dss_fck_multiplier =   2,
1078     .parent_clk_name    =   "dpll4_ck",
1079     .ports          =   omap34xx_ports,
1080     .outputs        =   omap3430_dss_supported_outputs,
1081     .num_ports      =   ARRAY_SIZE(omap34xx_ports),
1082     .ops            =   &dss_ops_omap2_omap3,
1083     .dispc_clk_switch   =   { 0, 0 },
1084     .has_lcd_clk_src    =   false,
1085 };
1086 
1087 static const struct dss_features omap3630_dss_feats = {
1088     .model          =   DSS_MODEL_OMAP3,
1089     .fck_div_max        =   31,
1090     .fck_freq_max       =   173000000,
1091     .dss_fck_multiplier =   1,
1092     .parent_clk_name    =   "dpll4_ck",
1093     .ports          =   omap2plus_ports,
1094     .num_ports      =   ARRAY_SIZE(omap2plus_ports),
1095     .outputs        =   omap3630_dss_supported_outputs,
1096     .ops            =   &dss_ops_omap2_omap3,
1097     .dispc_clk_switch   =   { 0, 0 },
1098     .has_lcd_clk_src    =   false,
1099 };
1100 
1101 static const struct dss_features omap44xx_dss_feats = {
1102     .model          =   DSS_MODEL_OMAP4,
1103     .fck_div_max        =   32,
1104     .fck_freq_max       =   186000000,
1105     .dss_fck_multiplier =   1,
1106     .parent_clk_name    =   "dpll_per_x2_ck",
1107     .ports          =   omap2plus_ports,
1108     .num_ports      =   ARRAY_SIZE(omap2plus_ports),
1109     .outputs        =   omap4_dss_supported_outputs,
1110     .ops            =   &dss_ops_omap4,
1111     .dispc_clk_switch   =   { 9, 8 },
1112     .has_lcd_clk_src    =   true,
1113 };
1114 
1115 static const struct dss_features omap54xx_dss_feats = {
1116     .model          =   DSS_MODEL_OMAP5,
1117     .fck_div_max        =   64,
1118     .fck_freq_max       =   209250000,
1119     .dss_fck_multiplier =   1,
1120     .parent_clk_name    =   "dpll_per_x2_ck",
1121     .ports          =   omap2plus_ports,
1122     .num_ports      =   ARRAY_SIZE(omap2plus_ports),
1123     .outputs        =   omap5_dss_supported_outputs,
1124     .ops            =   &dss_ops_omap5,
1125     .dispc_clk_switch   =   { 9, 7 },
1126     .has_lcd_clk_src    =   true,
1127 };
1128 
1129 static const struct dss_features am43xx_dss_feats = {
1130     .model          =   DSS_MODEL_OMAP3,
1131     .fck_div_max        =   0,
1132     .fck_freq_max       =   200000000,
1133     .dss_fck_multiplier =   0,
1134     .parent_clk_name    =   NULL,
1135     .ports          =   omap2plus_ports,
1136     .num_ports      =   ARRAY_SIZE(omap2plus_ports),
1137     .outputs        =   am43xx_dss_supported_outputs,
1138     .ops            =   &dss_ops_omap2_omap3,
1139     .dispc_clk_switch   =   { 0, 0 },
1140     .has_lcd_clk_src    =   true,
1141 };
1142 
1143 static const struct dss_features dra7xx_dss_feats = {
1144     .model          =   DSS_MODEL_DRA7,
1145     .fck_div_max        =   64,
1146     .fck_freq_max       =   209250000,
1147     .dss_fck_multiplier =   1,
1148     .parent_clk_name    =   "dpll_per_x2_ck",
1149     .ports          =   dra7xx_ports,
1150     .num_ports      =   ARRAY_SIZE(dra7xx_ports),
1151     .outputs        =   omap5_dss_supported_outputs,
1152     .ops            =   &dss_ops_dra7,
1153     .dispc_clk_switch   =   { 9, 7 },
1154     .has_lcd_clk_src    =   true,
1155 };
1156 
1157 static void __dss_uninit_ports(struct dss_device *dss, unsigned int num_ports)
1158 {
1159     struct platform_device *pdev = dss->pdev;
1160     struct device_node *parent = pdev->dev.of_node;
1161     struct device_node *port;
1162     unsigned int i;
1163 
1164     for (i = 0; i < num_ports; i++) {
1165         port = of_graph_get_port_by_id(parent, i);
1166         if (!port)
1167             continue;
1168 
1169         switch (dss->feat->ports[i]) {
1170         case OMAP_DISPLAY_TYPE_DPI:
1171             dpi_uninit_port(port);
1172             break;
1173         case OMAP_DISPLAY_TYPE_SDI:
1174             sdi_uninit_port(port);
1175             break;
1176         default:
1177             break;
1178         }
1179     }
1180 }
1181 
1182 static int dss_init_ports(struct dss_device *dss)
1183 {
1184     struct platform_device *pdev = dss->pdev;
1185     struct device_node *parent = pdev->dev.of_node;
1186     struct device_node *port;
1187     unsigned int i;
1188     int r;
1189 
1190     for (i = 0; i < dss->feat->num_ports; i++) {
1191         port = of_graph_get_port_by_id(parent, i);
1192         if (!port)
1193             continue;
1194 
1195         switch (dss->feat->ports[i]) {
1196         case OMAP_DISPLAY_TYPE_DPI:
1197             r = dpi_init_port(dss, pdev, port, dss->feat->model);
1198             if (r)
1199                 goto error;
1200             break;
1201 
1202         case OMAP_DISPLAY_TYPE_SDI:
1203             r = sdi_init_port(dss, pdev, port);
1204             if (r)
1205                 goto error;
1206             break;
1207 
1208         default:
1209             break;
1210         }
1211     }
1212 
1213     return 0;
1214 
1215 error:
1216     __dss_uninit_ports(dss, i);
1217     return r;
1218 }
1219 
1220 static void dss_uninit_ports(struct dss_device *dss)
1221 {
1222     __dss_uninit_ports(dss, dss->feat->num_ports);
1223 }
1224 
1225 static int dss_video_pll_probe(struct dss_device *dss)
1226 {
1227     struct platform_device *pdev = dss->pdev;
1228     struct device_node *np = pdev->dev.of_node;
1229     struct regulator *pll_regulator;
1230     int r;
1231 
1232     if (!np)
1233         return 0;
1234 
1235     if (of_property_read_bool(np, "syscon-pll-ctrl")) {
1236         dss->syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np,
1237             "syscon-pll-ctrl");
1238         if (IS_ERR(dss->syscon_pll_ctrl)) {
1239             dev_err(&pdev->dev,
1240                 "failed to get syscon-pll-ctrl regmap\n");
1241             return PTR_ERR(dss->syscon_pll_ctrl);
1242         }
1243 
1244         if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1,
1245                 &dss->syscon_pll_ctrl_offset)) {
1246             dev_err(&pdev->dev,
1247                 "failed to get syscon-pll-ctrl offset\n");
1248             return -EINVAL;
1249         }
1250     }
1251 
1252     pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video");
1253     if (IS_ERR(pll_regulator)) {
1254         r = PTR_ERR(pll_regulator);
1255 
1256         switch (r) {
1257         case -ENOENT:
1258             pll_regulator = NULL;
1259             break;
1260 
1261         case -EPROBE_DEFER:
1262             return -EPROBE_DEFER;
1263 
1264         default:
1265             DSSERR("can't get DPLL VDDA regulator\n");
1266             return r;
1267         }
1268     }
1269 
1270     if (of_property_match_string(np, "reg-names", "pll1") >= 0) {
1271         dss->video1_pll = dss_video_pll_init(dss, pdev, 0,
1272                              pll_regulator);
1273         if (IS_ERR(dss->video1_pll))
1274             return PTR_ERR(dss->video1_pll);
1275     }
1276 
1277     if (of_property_match_string(np, "reg-names", "pll2") >= 0) {
1278         dss->video2_pll = dss_video_pll_init(dss, pdev, 1,
1279                              pll_regulator);
1280         if (IS_ERR(dss->video2_pll)) {
1281             dss_video_pll_uninit(dss->video1_pll);
1282             return PTR_ERR(dss->video2_pll);
1283         }
1284     }
1285 
1286     return 0;
1287 }
1288 
1289 /* DSS HW IP initialisation */
1290 static const struct of_device_id dss_of_match[] = {
1291     { .compatible = "ti,omap2-dss", .data = &omap24xx_dss_feats },
1292     { .compatible = "ti,omap3-dss", .data = &omap3630_dss_feats },
1293     { .compatible = "ti,omap4-dss", .data = &omap44xx_dss_feats },
1294     { .compatible = "ti,omap5-dss", .data = &omap54xx_dss_feats },
1295     { .compatible = "ti,dra7-dss",  .data = &dra7xx_dss_feats },
1296     {},
1297 };
1298 MODULE_DEVICE_TABLE(of, dss_of_match);
1299 
1300 static const struct soc_device_attribute dss_soc_devices[] = {
1301     { .machine = "OMAP3430/3530", .data = &omap34xx_dss_feats },
1302     { .machine = "AM35??",        .data = &omap34xx_dss_feats },
1303     { .family  = "AM43xx",        .data = &am43xx_dss_feats },
1304     { /* sentinel */ }
1305 };
1306 
1307 static int dss_bind(struct device *dev)
1308 {
1309     struct dss_device *dss = dev_get_drvdata(dev);
1310     struct platform_device *drm_pdev;
1311     struct dss_pdata pdata;
1312     int r;
1313 
1314     r = component_bind_all(dev, NULL);
1315     if (r)
1316         return r;
1317 
1318     pm_set_vt_switch(0);
1319 
1320     pdata.dss = dss;
1321     drm_pdev = platform_device_register_data(NULL, "omapdrm", 0,
1322                          &pdata, sizeof(pdata));
1323     if (IS_ERR(drm_pdev)) {
1324         component_unbind_all(dev, NULL);
1325         return PTR_ERR(drm_pdev);
1326     }
1327 
1328     dss->drm_pdev = drm_pdev;
1329 
1330     return 0;
1331 }
1332 
1333 static void dss_unbind(struct device *dev)
1334 {
1335     struct dss_device *dss = dev_get_drvdata(dev);
1336 
1337     platform_device_unregister(dss->drm_pdev);
1338 
1339     component_unbind_all(dev, NULL);
1340 }
1341 
1342 static const struct component_master_ops dss_component_ops = {
1343     .bind = dss_bind,
1344     .unbind = dss_unbind,
1345 };
1346 
1347 struct dss_component_match_data {
1348     struct device *dev;
1349     struct component_match **match;
1350 };
1351 
1352 static int dss_add_child_component(struct device *dev, void *data)
1353 {
1354     struct dss_component_match_data *cmatch = data;
1355     struct component_match **match = cmatch->match;
1356 
1357     /*
1358      * HACK
1359      * We don't have a working driver for rfbi, so skip it here always.
1360      * Otherwise dss will never get probed successfully, as it will wait
1361      * for rfbi to get probed.
1362      */
1363     if (strstr(dev_name(dev), "rfbi"))
1364         return 0;
1365 
1366     /*
1367      * Handle possible interconnect target modules defined within the DSS.
1368      * The DSS components can be children of an interconnect target module
1369      * after the device tree has been updated for the module data.
1370      * See also omapdss_boot_init() for compatible fixup.
1371      */
1372     if (strstr(dev_name(dev), "target-module"))
1373         return device_for_each_child(dev, cmatch,
1374                          dss_add_child_component);
1375 
1376     component_match_add(cmatch->dev, match, component_compare_dev, dev);
1377 
1378     return 0;
1379 }
1380 
1381 static int dss_probe_hardware(struct dss_device *dss)
1382 {
1383     u32 rev;
1384     int r;
1385 
1386     r = dss_runtime_get(dss);
1387     if (r)
1388         return r;
1389 
1390     dss->dss_clk_rate = clk_get_rate(dss->dss_clk);
1391 
1392     /* Select DPLL */
1393     REG_FLD_MOD(dss, DSS_CONTROL, 0, 0, 0);
1394 
1395     dss_select_dispc_clk_source(dss, DSS_CLK_SRC_FCK);
1396 
1397 #ifdef CONFIG_OMAP2_DSS_VENC
1398     REG_FLD_MOD(dss, DSS_CONTROL, 1, 4, 4); /* venc dac demen */
1399     REG_FLD_MOD(dss, DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
1400     REG_FLD_MOD(dss, DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
1401 #endif
1402     dss->dsi_clk_source[0] = DSS_CLK_SRC_FCK;
1403     dss->dsi_clk_source[1] = DSS_CLK_SRC_FCK;
1404     dss->dispc_clk_source = DSS_CLK_SRC_FCK;
1405     dss->lcd_clk_source[0] = DSS_CLK_SRC_FCK;
1406     dss->lcd_clk_source[1] = DSS_CLK_SRC_FCK;
1407 
1408     rev = dss_read_reg(dss, DSS_REVISION);
1409     pr_info("OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
1410 
1411     dss_runtime_put(dss);
1412 
1413     return 0;
1414 }
1415 
1416 static int dss_probe(struct platform_device *pdev)
1417 {
1418     const struct soc_device_attribute *soc;
1419     struct dss_component_match_data cmatch;
1420     struct component_match *match = NULL;
1421     struct dss_device *dss;
1422     int r;
1423 
1424     dss = kzalloc(sizeof(*dss), GFP_KERNEL);
1425     if (!dss)
1426         return -ENOMEM;
1427 
1428     dss->pdev = pdev;
1429     platform_set_drvdata(pdev, dss);
1430 
1431     r = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1432     if (r) {
1433         dev_err(&pdev->dev, "Failed to set the DMA mask\n");
1434         goto err_free_dss;
1435     }
1436 
1437     /*
1438      * The various OMAP3-based SoCs can't be told apart using the compatible
1439      * string, use SoC device matching.
1440      */
1441     soc = soc_device_match(dss_soc_devices);
1442     if (soc)
1443         dss->feat = soc->data;
1444     else
1445         dss->feat = of_match_device(dss_of_match, &pdev->dev)->data;
1446 
1447     /* Map I/O registers, get and setup clocks. */
1448     dss->base = devm_platform_ioremap_resource(pdev, 0);
1449     if (IS_ERR(dss->base)) {
1450         r = PTR_ERR(dss->base);
1451         goto err_free_dss;
1452     }
1453 
1454     r = dss_get_clocks(dss);
1455     if (r)
1456         goto err_free_dss;
1457 
1458     r = dss_setup_default_clock(dss);
1459     if (r)
1460         goto err_put_clocks;
1461 
1462     /* Setup the video PLLs and the DPI and SDI ports. */
1463     r = dss_video_pll_probe(dss);
1464     if (r)
1465         goto err_put_clocks;
1466 
1467     r = dss_init_ports(dss);
1468     if (r)
1469         goto err_uninit_plls;
1470 
1471     /* Enable runtime PM and probe the hardware. */
1472     pm_runtime_enable(&pdev->dev);
1473 
1474     r = dss_probe_hardware(dss);
1475     if (r)
1476         goto err_pm_runtime_disable;
1477 
1478     /* Initialize debugfs. */
1479     r = dss_initialize_debugfs(dss);
1480     if (r)
1481         goto err_pm_runtime_disable;
1482 
1483     dss->debugfs.clk = dss_debugfs_create_file(dss, "clk",
1484                            dss_debug_dump_clocks, dss);
1485     dss->debugfs.dss = dss_debugfs_create_file(dss, "dss", dss_dump_regs,
1486                            dss);
1487 
1488     /* Add all the child devices as components. */
1489     r = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
1490     if (r)
1491         goto err_uninit_debugfs;
1492 
1493     omapdss_gather_components(&pdev->dev);
1494 
1495     cmatch.dev = &pdev->dev;
1496     cmatch.match = &match;
1497     device_for_each_child(&pdev->dev, &cmatch, dss_add_child_component);
1498 
1499     r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match);
1500     if (r)
1501         goto err_of_depopulate;
1502 
1503     return 0;
1504 
1505 err_of_depopulate:
1506     of_platform_depopulate(&pdev->dev);
1507 
1508 err_uninit_debugfs:
1509     dss_debugfs_remove_file(dss->debugfs.clk);
1510     dss_debugfs_remove_file(dss->debugfs.dss);
1511     dss_uninitialize_debugfs(dss);
1512 
1513 err_pm_runtime_disable:
1514     pm_runtime_disable(&pdev->dev);
1515     dss_uninit_ports(dss);
1516 
1517 err_uninit_plls:
1518     if (dss->video1_pll)
1519         dss_video_pll_uninit(dss->video1_pll);
1520     if (dss->video2_pll)
1521         dss_video_pll_uninit(dss->video2_pll);
1522 
1523 err_put_clocks:
1524     dss_put_clocks(dss);
1525 
1526 err_free_dss:
1527     kfree(dss);
1528 
1529     return r;
1530 }
1531 
1532 static int dss_remove(struct platform_device *pdev)
1533 {
1534     struct dss_device *dss = platform_get_drvdata(pdev);
1535 
1536     of_platform_depopulate(&pdev->dev);
1537 
1538     component_master_del(&pdev->dev, &dss_component_ops);
1539 
1540     dss_debugfs_remove_file(dss->debugfs.clk);
1541     dss_debugfs_remove_file(dss->debugfs.dss);
1542     dss_uninitialize_debugfs(dss);
1543 
1544     pm_runtime_disable(&pdev->dev);
1545 
1546     dss_uninit_ports(dss);
1547 
1548     if (dss->video1_pll)
1549         dss_video_pll_uninit(dss->video1_pll);
1550 
1551     if (dss->video2_pll)
1552         dss_video_pll_uninit(dss->video2_pll);
1553 
1554     dss_put_clocks(dss);
1555 
1556     kfree(dss);
1557 
1558     return 0;
1559 }
1560 
1561 static void dss_shutdown(struct platform_device *pdev)
1562 {
1563     DSSDBG("shutdown\n");
1564 }
1565 
1566 static __maybe_unused int dss_runtime_suspend(struct device *dev)
1567 {
1568     struct dss_device *dss = dev_get_drvdata(dev);
1569 
1570     dss_save_context(dss);
1571     dss_set_min_bus_tput(dev, 0);
1572 
1573     pinctrl_pm_select_sleep_state(dev);
1574 
1575     return 0;
1576 }
1577 
1578 static __maybe_unused int dss_runtime_resume(struct device *dev)
1579 {
1580     struct dss_device *dss = dev_get_drvdata(dev);
1581     int r;
1582 
1583     pinctrl_pm_select_default_state(dev);
1584 
1585     /*
1586      * Set an arbitrarily high tput request to ensure OPP100.
1587      * What we should really do is to make a request to stay in OPP100,
1588      * without any tput requirements, but that is not currently possible
1589      * via the PM layer.
1590      */
1591 
1592     r = dss_set_min_bus_tput(dev, 1000000000);
1593     if (r)
1594         return r;
1595 
1596     dss_restore_context(dss);
1597     return 0;
1598 }
1599 
1600 static const struct dev_pm_ops dss_pm_ops = {
1601     SET_RUNTIME_PM_OPS(dss_runtime_suspend, dss_runtime_resume, NULL)
1602     SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1603 };
1604 
1605 struct platform_driver omap_dsshw_driver = {
1606     .probe      = dss_probe,
1607     .remove     = dss_remove,
1608     .shutdown   = dss_shutdown,
1609     .driver         = {
1610         .name   = "omapdss_dss",
1611         .pm = &dss_pm_ops,
1612         .of_match_table = dss_of_match,
1613         .suppress_bind_attrs = true,
1614     },
1615 };
1616 
1617 /* INIT */
1618 static struct platform_driver * const omap_dss_drivers[] = {
1619     &omap_dsshw_driver,
1620     &omap_dispchw_driver,
1621 #ifdef CONFIG_OMAP2_DSS_DSI
1622     &omap_dsihw_driver,
1623 #endif
1624 #ifdef CONFIG_OMAP2_DSS_VENC
1625     &omap_venchw_driver,
1626 #endif
1627 #ifdef CONFIG_OMAP4_DSS_HDMI
1628     &omapdss_hdmi4hw_driver,
1629 #endif
1630 #ifdef CONFIG_OMAP5_DSS_HDMI
1631     &omapdss_hdmi5hw_driver,
1632 #endif
1633 };
1634 
1635 int __init omap_dss_init(void)
1636 {
1637     return platform_register_drivers(omap_dss_drivers,
1638                      ARRAY_SIZE(omap_dss_drivers));
1639 }
1640 
1641 void omap_dss_exit(void)
1642 {
1643     platform_unregister_drivers(omap_dss_drivers,
1644                     ARRAY_SIZE(omap_dss_drivers));
1645 }
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