omapdrm/dss/dsi.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
0004  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
0005  */
0006
0007 #ifndef __OMAP_DRM_DSS_DSI_H
0008 #define __OMAP_DRM_DSS_DSI_H
0009
0010 #include <drm/drm_mipi_dsi.h>
0011
0012 struct dsi_reg {
0013     u16 module;
0014     u16 idx;
0015 };
0016
0017 #define DSI_REG(mod, idx)       ((const struct dsi_reg) { mod, idx })
0018
0019 /* DSI Protocol Engine */
0020
0021 #define DSI_PROTO           0
0022 #define DSI_PROTO_SZ            0x200
0023
0024 #define DSI_REVISION            DSI_REG(DSI_PROTO, 0x0000)
0025 #define DSI_SYSCONFIG           DSI_REG(DSI_PROTO, 0x0010)
0026 #define DSI_SYSSTATUS           DSI_REG(DSI_PROTO, 0x0014)
0027 #define DSI_IRQSTATUS           DSI_REG(DSI_PROTO, 0x0018)
0028 #define DSI_IRQENABLE           DSI_REG(DSI_PROTO, 0x001C)
0029 #define DSI_CTRL            DSI_REG(DSI_PROTO, 0x0040)
0030 #define DSI_GNQ             DSI_REG(DSI_PROTO, 0x0044)
0031 #define DSI_COMPLEXIO_CFG1      DSI_REG(DSI_PROTO, 0x0048)
0032 #define DSI_COMPLEXIO_IRQ_STATUS    DSI_REG(DSI_PROTO, 0x004C)
0033 #define DSI_COMPLEXIO_IRQ_ENABLE    DSI_REG(DSI_PROTO, 0x0050)
0034 #define DSI_CLK_CTRL            DSI_REG(DSI_PROTO, 0x0054)
0035 #define DSI_TIMING1         DSI_REG(DSI_PROTO, 0x0058)
0036 #define DSI_TIMING2         DSI_REG(DSI_PROTO, 0x005C)
0037 #define DSI_VM_TIMING1          DSI_REG(DSI_PROTO, 0x0060)
0038 #define DSI_VM_TIMING2          DSI_REG(DSI_PROTO, 0x0064)
0039 #define DSI_VM_TIMING3          DSI_REG(DSI_PROTO, 0x0068)
0040 #define DSI_CLK_TIMING          DSI_REG(DSI_PROTO, 0x006C)
0041 #define DSI_TX_FIFO_VC_SIZE     DSI_REG(DSI_PROTO, 0x0070)
0042 #define DSI_RX_FIFO_VC_SIZE     DSI_REG(DSI_PROTO, 0x0074)
0043 #define DSI_COMPLEXIO_CFG2      DSI_REG(DSI_PROTO, 0x0078)
0044 #define DSI_RX_FIFO_VC_FULLNESS     DSI_REG(DSI_PROTO, 0x007C)
0045 #define DSI_VM_TIMING4          DSI_REG(DSI_PROTO, 0x0080)
0046 #define DSI_TX_FIFO_VC_EMPTINESS    DSI_REG(DSI_PROTO, 0x0084)
0047 #define DSI_VM_TIMING5          DSI_REG(DSI_PROTO, 0x0088)
0048 #define DSI_VM_TIMING6          DSI_REG(DSI_PROTO, 0x008C)
0049 #define DSI_VM_TIMING7          DSI_REG(DSI_PROTO, 0x0090)
0050 #define DSI_STOPCLK_TIMING      DSI_REG(DSI_PROTO, 0x0094)
0051 #define DSI_VC_CTRL(n)          DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
0052 #define DSI_VC_TE(n)            DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
0053 #define DSI_VC_LONG_PACKET_HEADER(n)    DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
0054 #define DSI_VC_LONG_PACKET_PAYLOAD(n)   DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
0055 #define DSI_VC_SHORT_PACKET_HEADER(n)   DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
0056 #define DSI_VC_IRQSTATUS(n)     DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
0057 #define DSI_VC_IRQENABLE(n)     DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
0058
0059 /* DSIPHY_SCP */
0060
0061 #define DSI_PHY             1
0062 #define DSI_PHY_OFFSET          0x200
0063 #define DSI_PHY_SZ          0x40
0064
0065 #define DSI_DSIPHY_CFG0         DSI_REG(DSI_PHY, 0x0000)
0066 #define DSI_DSIPHY_CFG1         DSI_REG(DSI_PHY, 0x0004)
0067 #define DSI_DSIPHY_CFG2         DSI_REG(DSI_PHY, 0x0008)
0068 #define DSI_DSIPHY_CFG5         DSI_REG(DSI_PHY, 0x0014)
0069 #define DSI_DSIPHY_CFG10        DSI_REG(DSI_PHY, 0x0028)
0070
0071 /* DSI_PLL_CTRL_SCP */
0072
0073 #define DSI_PLL             2
0074 #define DSI_PLL_OFFSET          0x300
0075 #define DSI_PLL_SZ          0x20
0076
0077 #define DSI_PLL_CONTROL         DSI_REG(DSI_PLL, 0x0000)
0078 #define DSI_PLL_STATUS          DSI_REG(DSI_PLL, 0x0004)
0079 #define DSI_PLL_GO          DSI_REG(DSI_PLL, 0x0008)
0080 #define DSI_PLL_CONFIGURATION1      DSI_REG(DSI_PLL, 0x000C)
0081 #define DSI_PLL_CONFIGURATION2      DSI_REG(DSI_PLL, 0x0010)
0082
0083 /* Global interrupts */
0084 #define DSI_IRQ_VC0     (1 << 0)
0085 #define DSI_IRQ_VC1     (1 << 1)
0086 #define DSI_IRQ_VC2     (1 << 2)
0087 #define DSI_IRQ_VC3     (1 << 3)
0088 #define DSI_IRQ_WAKEUP      (1 << 4)
0089 #define DSI_IRQ_RESYNC      (1 << 5)
0090 #define DSI_IRQ_PLL_LOCK    (1 << 7)
0091 #define DSI_IRQ_PLL_UNLOCK  (1 << 8)
0092 #define DSI_IRQ_PLL_RECALL  (1 << 9)
0093 #define DSI_IRQ_COMPLEXIO_ERR   (1 << 10)
0094 #define DSI_IRQ_HS_TX_TIMEOUT   (1 << 14)
0095 #define DSI_IRQ_LP_RX_TIMEOUT   (1 << 15)
0096 #define DSI_IRQ_TE_TRIGGER  (1 << 16)
0097 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
0098 #define DSI_IRQ_SYNC_LOST   (1 << 18)
0099 #define DSI_IRQ_LDO_POWER_GOOD  (1 << 19)
0100 #define DSI_IRQ_TA_TIMEOUT  (1 << 20)
0101 #define DSI_IRQ_ERROR_MASK \
0102     (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
0103     DSI_IRQ_TA_TIMEOUT)
0104 #define DSI_IRQ_CHANNEL_MASK    0xf
0105
0106 /* Virtual channel interrupts */
0107 #define DSI_VC_IRQ_CS       (1 << 0)
0108 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
0109 #define DSI_VC_IRQ_PACKET_SENT  (1 << 2)
0110 #define DSI_VC_IRQ_FIFO_TX_OVF  (1 << 3)
0111 #define DSI_VC_IRQ_FIFO_RX_OVF  (1 << 4)
0112 #define DSI_VC_IRQ_BTA      (1 << 5)
0113 #define DSI_VC_IRQ_ECC_NO_CORR  (1 << 6)
0114 #define DSI_VC_IRQ_FIFO_TX_UDF  (1 << 7)
0115 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
0116 #define DSI_VC_IRQ_ERROR_MASK \
0117     (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
0118     DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
0119     DSI_VC_IRQ_FIFO_TX_UDF)
0120
0121 /* ComplexIO interrupts */
0122 #define DSI_CIO_IRQ_ERRSYNCESC1     (1 << 0)
0123 #define DSI_CIO_IRQ_ERRSYNCESC2     (1 << 1)
0124 #define DSI_CIO_IRQ_ERRSYNCESC3     (1 << 2)
0125 #define DSI_CIO_IRQ_ERRSYNCESC4     (1 << 3)
0126 #define DSI_CIO_IRQ_ERRSYNCESC5     (1 << 4)
0127 #define DSI_CIO_IRQ_ERRESC1     (1 << 5)
0128 #define DSI_CIO_IRQ_ERRESC2     (1 << 6)
0129 #define DSI_CIO_IRQ_ERRESC3     (1 << 7)
0130 #define DSI_CIO_IRQ_ERRESC4     (1 << 8)
0131 #define DSI_CIO_IRQ_ERRESC5     (1 << 9)
0132 #define DSI_CIO_IRQ_ERRCONTROL1     (1 << 10)
0133 #define DSI_CIO_IRQ_ERRCONTROL2     (1 << 11)
0134 #define DSI_CIO_IRQ_ERRCONTROL3     (1 << 12)
0135 #define DSI_CIO_IRQ_ERRCONTROL4     (1 << 13)
0136 #define DSI_CIO_IRQ_ERRCONTROL5     (1 << 14)
0137 #define DSI_CIO_IRQ_STATEULPS1      (1 << 15)
0138 #define DSI_CIO_IRQ_STATEULPS2      (1 << 16)
0139 #define DSI_CIO_IRQ_STATEULPS3      (1 << 17)
0140 #define DSI_CIO_IRQ_STATEULPS4      (1 << 18)
0141 #define DSI_CIO_IRQ_STATEULPS5      (1 << 19)
0142 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1  (1 << 20)
0143 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1  (1 << 21)
0144 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2  (1 << 22)
0145 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2  (1 << 23)
0146 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3  (1 << 24)
0147 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3  (1 << 25)
0148 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4  (1 << 26)
0149 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4  (1 << 27)
0150 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5  (1 << 28)
0151 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5  (1 << 29)
0152 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0  (1 << 30)
0153 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1  (1 << 31)
0154 #define DSI_CIO_IRQ_ERROR_MASK \
0155     (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
0156      DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
0157      DSI_CIO_IRQ_ERRSYNCESC5 | \
0158      DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
0159      DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
0160      DSI_CIO_IRQ_ERRESC5 | \
0161      DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
0162      DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
0163      DSI_CIO_IRQ_ERRCONTROL5 | \
0164      DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
0165      DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
0166      DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
0167      DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
0168      DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
0169
0170 enum omap_dss_dsi_mode {
0171     OMAP_DSS_DSI_CMD_MODE = 0,
0172     OMAP_DSS_DSI_VIDEO_MODE,
0173 };
0174
0175 enum omap_dss_dsi_trans_mode {
0176     /* Sync Pulses: both sync start and end packets sent */
0177     OMAP_DSS_DSI_PULSE_MODE,
0178     /* Sync Events: only sync start packets sent */
0179     OMAP_DSS_DSI_EVENT_MODE,
0180     /* Burst: only sync start packets sent, pixels are time compressed */
0181     OMAP_DSS_DSI_BURST_MODE,
0182 };
0183
0184 struct omap_dss_dsi_videomode_timings {
0185     unsigned long hsclk;
0186
0187     unsigned int ndl;
0188     unsigned int bitspp;
0189
0190     /* pixels */
0191     u16 hact;
0192     /* lines */
0193     u16 vact;
0194
0195     /* DSI video mode blanking data */
0196     /* Unit: byte clock cycles */
0197     u16 hss;
0198     u16 hsa;
0199     u16 hse;
0200     u16 hfp;
0201     u16 hbp;
0202     /* Unit: line clocks */
0203     u16 vsa;
0204     u16 vfp;
0205     u16 vbp;
0206
0207     /* DSI blanking modes */
0208     int blanking_mode;
0209     int hsa_blanking_mode;
0210     int hbp_blanking_mode;
0211     int hfp_blanking_mode;
0212
0213     enum omap_dss_dsi_trans_mode trans_mode;
0214
0215     int window_sync;
0216 };
0217
0218 struct omap_dss_dsi_config {
0219     enum omap_dss_dsi_mode mode;
0220     enum mipi_dsi_pixel_format pixel_format;
0221     const struct videomode *vm;
0222
0223     unsigned long hs_clk_min, hs_clk_max;
0224     unsigned long lp_clk_min, lp_clk_max;
0225
0226     enum omap_dss_dsi_trans_mode trans_mode;
0227 };
0228
0229 /* DSI PLL HSDIV indices */
0230 #define HSDIV_DISPC 0
0231 #define HSDIV_DSI   1
0232
0233 #define DSI_MAX_NR_ISRS                2
0234 #define DSI_MAX_NR_LANES    5
0235
0236 enum dsi_model {
0237     DSI_MODEL_OMAP3,
0238     DSI_MODEL_OMAP4,
0239     DSI_MODEL_OMAP5,
0240 };
0241
0242 enum dsi_lane_function {
0243     DSI_LANE_UNUSED = 0,
0244     DSI_LANE_CLK,
0245     DSI_LANE_DATA1,
0246     DSI_LANE_DATA2,
0247     DSI_LANE_DATA3,
0248     DSI_LANE_DATA4,
0249 };
0250
0251 struct dsi_lane_config {
0252     enum dsi_lane_function function;
0253     u8 polarity;
0254 };
0255
0256 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
0257
0258 struct dsi_isr_data {
0259     omap_dsi_isr_t  isr;
0260     void        *arg;
0261     u32     mask;
0262 };
0263
0264 enum fifo_size {
0265     DSI_FIFO_SIZE_0     = 0,
0266     DSI_FIFO_SIZE_32    = 1,
0267     DSI_FIFO_SIZE_64    = 2,
0268     DSI_FIFO_SIZE_96    = 3,
0269     DSI_FIFO_SIZE_128   = 4,
0270 };
0271
0272 enum dsi_vc_source {
0273     DSI_VC_SOURCE_L4 = 0,
0274     DSI_VC_SOURCE_VP,
0275 };
0276
0277 struct dsi_irq_stats {
0278     unsigned long last_reset;
0279     unsigned int irq_count;
0280     unsigned int dsi_irqs[32];
0281     unsigned int vc_irqs[4][32];
0282     unsigned int cio_irqs[32];
0283 };
0284
0285 struct dsi_isr_tables {
0286     struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
0287     struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
0288     struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
0289 };
0290
0291 struct dsi_lp_clock_info {
0292     unsigned long lp_clk;
0293     u16 lp_clk_div;
0294 };
0295
0296 struct dsi_clk_calc_ctx {
0297     struct dsi_data *dsi;
0298     struct dss_pll *pll;
0299
0300     /* inputs */
0301
0302     const struct omap_dss_dsi_config *config;
0303
0304     unsigned long req_pck_min, req_pck_nom, req_pck_max;
0305
0306     /* outputs */
0307
0308     struct dss_pll_clock_info dsi_cinfo;
0309     struct dispc_clock_info dispc_cinfo;
0310     struct dsi_lp_clock_info lp_cinfo;
0311
0312     struct videomode vm;
0313     struct omap_dss_dsi_videomode_timings dsi_vm;
0314 };
0315
0316 struct dsi_module_id_data {
0317     u32 address;
0318     int id;
0319 };
0320
0321 enum dsi_quirks {
0322     DSI_QUIRK_PLL_PWR_BUG = (1 << 0),   /* DSI-PLL power command 0x3 is not working */
0323     DSI_QUIRK_DCS_CMD_CONFIG_VC = (1 << 1),
0324     DSI_QUIRK_VC_OCP_WIDTH = (1 << 2),
0325     DSI_QUIRK_REVERSE_TXCLKESC = (1 << 3),
0326     DSI_QUIRK_GNQ = (1 << 4),
0327     DSI_QUIRK_PHY_DCC = (1 << 5),
0328 };
0329
0330 struct dsi_of_data {
0331     enum dsi_model model;
0332     const struct dss_pll_hw *pll_hw;
0333     const struct dsi_module_id_data *modules;
0334     unsigned int max_fck_freq;
0335     unsigned int max_pll_lpdiv;
0336     enum dsi_quirks quirks;
0337 };
0338
0339 struct dsi_data {
0340     struct device *dev;
0341     void __iomem *proto_base;
0342     void __iomem *phy_base;
0343     void __iomem *pll_base;
0344
0345     const struct dsi_of_data *data;
0346     int module_id;
0347
0348     int irq;
0349
0350     bool is_enabled;
0351
0352     struct clk *dss_clk;
0353     struct regmap *syscon;
0354     struct dss_device *dss;
0355
0356     struct mipi_dsi_host host;
0357
0358     struct dispc_clock_info user_dispc_cinfo;
0359     struct dss_pll_clock_info user_dsi_cinfo;
0360
0361     struct dsi_lp_clock_info user_lp_cinfo;
0362     struct dsi_lp_clock_info current_lp_cinfo;
0363
0364     struct dss_pll pll;
0365
0366     bool vdds_dsi_enabled;
0367     struct regulator *vdds_dsi_reg;
0368
0369     struct mipi_dsi_device *dsidev;
0370
0371     struct {
0372         enum dsi_vc_source source;
0373         enum fifo_size tx_fifo_size;
0374         enum fifo_size rx_fifo_size;
0375     } vc[4];
0376
0377     struct mutex lock;
0378     struct semaphore bus_lock;
0379
0380     spinlock_t irq_lock;
0381     struct dsi_isr_tables isr_tables;
0382     /* space for a copy used by the interrupt handler */
0383     struct dsi_isr_tables isr_tables_copy;
0384
0385     int update_vc;
0386 #ifdef DSI_PERF_MEASURE
0387     unsigned int update_bytes;
0388 #endif
0389
0390     /* external TE GPIO */
0391     struct gpio_desc *te_gpio;
0392     int te_irq;
0393     struct delayed_work te_timeout_work;
0394     atomic_t do_ext_te_update;
0395
0396     bool te_enabled;
0397     bool iface_enabled;
0398     bool video_enabled;
0399
0400     struct delayed_work framedone_timeout_work;
0401
0402 #ifdef DSI_CATCH_MISSING_TE
0403     struct timer_list te_timer;
0404 #endif
0405
0406     unsigned long cache_req_pck;
0407     unsigned long cache_clk_freq;
0408     struct dss_pll_clock_info cache_cinfo;
0409
0410     u32     errors;
0411     spinlock_t  errors_lock;
0412 #ifdef DSI_PERF_MEASURE
0413     ktime_t perf_setup_time;
0414     ktime_t perf_start_time;
0415 #endif
0416     int debug_read;
0417     int debug_write;
0418     struct {
0419         struct dss_debugfs_entry *irqs;
0420         struct dss_debugfs_entry *regs;
0421         struct dss_debugfs_entry *clks;
0422     } debugfs;
0423
0424 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
0425     spinlock_t irq_stats_lock;
0426     struct dsi_irq_stats irq_stats;
0427 #endif
0428
0429     unsigned int num_lanes_supported;
0430     unsigned int line_buffer_size;
0431
0432     struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
0433     unsigned int num_lanes_used;
0434
0435     unsigned int scp_clk_refcount;
0436
0437     struct omap_dss_dsi_config config;
0438
0439     struct dss_lcd_mgr_config mgr_config;
0440     struct videomode vm;
0441     enum mipi_dsi_pixel_format pix_fmt;
0442     enum omap_dss_dsi_mode mode;
0443     struct omap_dss_dsi_videomode_timings vm_timings;
0444
0445     struct omap_dss_device output;
0446     struct drm_bridge bridge;
0447
0448     struct delayed_work dsi_disable_work;
0449 };
0450
0451 struct dsi_packet_sent_handler_data {
0452     struct dsi_data *dsi;
0453     struct completion *completion;
0454 };
0455
0456 #endif /* __OMAP_DRM_DSS_DSI_H */