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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
0004  * Author: Archit Taneja <archit@ti.com>
0005  */
0006 
0007 #ifndef __OMAP2_DISPC_REG_H
0008 #define __OMAP2_DISPC_REG_H
0009 
0010 /* DISPC common registers */
0011 #define DISPC_REVISION          0x0000
0012 #define DISPC_SYSCONFIG         0x0010
0013 #define DISPC_SYSSTATUS         0x0014
0014 #define DISPC_IRQSTATUS         0x0018
0015 #define DISPC_IRQENABLE         0x001C
0016 #define DISPC_CONTROL           0x0040
0017 #define DISPC_CONFIG            0x0044
0018 #define DISPC_CAPABLE           0x0048
0019 #define DISPC_LINE_STATUS       0x005C
0020 #define DISPC_LINE_NUMBER       0x0060
0021 #define DISPC_GLOBAL_ALPHA      0x0074
0022 #define DISPC_CONTROL2          0x0238
0023 #define DISPC_CONFIG2           0x0620
0024 #define DISPC_DIVISOR           0x0804
0025 #define DISPC_GLOBAL_BUFFER     0x0800
0026 #define DISPC_CONTROL3                  0x0848
0027 #define DISPC_CONFIG3                   0x084C
0028 #define DISPC_MSTANDBY_CTRL     0x0858
0029 #define DISPC_GLOBAL_MFLAG_ATTRIBUTE    0x085C
0030 
0031 #define DISPC_GAMMA_TABLE0      0x0630
0032 #define DISPC_GAMMA_TABLE1      0x0634
0033 #define DISPC_GAMMA_TABLE2      0x0638
0034 #define DISPC_GAMMA_TABLE3      0x0850
0035 
0036 /* DISPC overlay registers */
0037 #define DISPC_OVL_BA0(n)        (DISPC_OVL_BASE(n) + \
0038                     DISPC_BA0_OFFSET(n))
0039 #define DISPC_OVL_BA1(n)        (DISPC_OVL_BASE(n) + \
0040                     DISPC_BA1_OFFSET(n))
0041 #define DISPC_OVL_BA0_UV(n)     (DISPC_OVL_BASE(n) + \
0042                     DISPC_BA0_UV_OFFSET(n))
0043 #define DISPC_OVL_BA1_UV(n)     (DISPC_OVL_BASE(n) + \
0044                     DISPC_BA1_UV_OFFSET(n))
0045 #define DISPC_OVL_POSITION(n)       (DISPC_OVL_BASE(n) + \
0046                     DISPC_POS_OFFSET(n))
0047 #define DISPC_OVL_SIZE(n)       (DISPC_OVL_BASE(n) + \
0048                     DISPC_SIZE_OFFSET(n))
0049 #define DISPC_OVL_ATTRIBUTES(n)     (DISPC_OVL_BASE(n) + \
0050                     DISPC_ATTR_OFFSET(n))
0051 #define DISPC_OVL_ATTRIBUTES2(n)    (DISPC_OVL_BASE(n) + \
0052                     DISPC_ATTR2_OFFSET(n))
0053 #define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
0054                     DISPC_FIFO_THRESH_OFFSET(n))
0055 #define DISPC_OVL_FIFO_SIZE_STATUS(n)   (DISPC_OVL_BASE(n) + \
0056                     DISPC_FIFO_SIZE_STATUS_OFFSET(n))
0057 #define DISPC_OVL_ROW_INC(n)        (DISPC_OVL_BASE(n) + \
0058                     DISPC_ROW_INC_OFFSET(n))
0059 #define DISPC_OVL_PIXEL_INC(n)      (DISPC_OVL_BASE(n) + \
0060                     DISPC_PIX_INC_OFFSET(n))
0061 #define DISPC_OVL_WINDOW_SKIP(n)    (DISPC_OVL_BASE(n) + \
0062                     DISPC_WINDOW_SKIP_OFFSET(n))
0063 #define DISPC_OVL_TABLE_BA(n)       (DISPC_OVL_BASE(n) + \
0064                     DISPC_TABLE_BA_OFFSET(n))
0065 #define DISPC_OVL_FIR(n)        (DISPC_OVL_BASE(n) + \
0066                     DISPC_FIR_OFFSET(n))
0067 #define DISPC_OVL_FIR2(n)       (DISPC_OVL_BASE(n) + \
0068                     DISPC_FIR2_OFFSET(n))
0069 #define DISPC_OVL_PICTURE_SIZE(n)   (DISPC_OVL_BASE(n) + \
0070                     DISPC_PIC_SIZE_OFFSET(n))
0071 #define DISPC_OVL_ACCU0(n)      (DISPC_OVL_BASE(n) + \
0072                     DISPC_ACCU0_OFFSET(n))
0073 #define DISPC_OVL_ACCU1(n)      (DISPC_OVL_BASE(n) + \
0074                     DISPC_ACCU1_OFFSET(n))
0075 #define DISPC_OVL_ACCU2_0(n)        (DISPC_OVL_BASE(n) + \
0076                     DISPC_ACCU2_0_OFFSET(n))
0077 #define DISPC_OVL_ACCU2_1(n)        (DISPC_OVL_BASE(n) + \
0078                     DISPC_ACCU2_1_OFFSET(n))
0079 #define DISPC_OVL_FIR_COEF_H(n, i)  (DISPC_OVL_BASE(n) + \
0080                     DISPC_FIR_COEF_H_OFFSET(n, i))
0081 #define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
0082                     DISPC_FIR_COEF_HV_OFFSET(n, i))
0083 #define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
0084                     DISPC_FIR_COEF_H2_OFFSET(n, i))
0085 #define DISPC_OVL_FIR_COEF_HV2(n, i)    (DISPC_OVL_BASE(n) + \
0086                     DISPC_FIR_COEF_HV2_OFFSET(n, i))
0087 #define DISPC_OVL_CONV_COEF(n, i)   (DISPC_OVL_BASE(n) + \
0088                     DISPC_CONV_COEF_OFFSET(n, i))
0089 #define DISPC_OVL_FIR_COEF_V(n, i)  (DISPC_OVL_BASE(n) + \
0090                     DISPC_FIR_COEF_V_OFFSET(n, i))
0091 #define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
0092                     DISPC_FIR_COEF_V2_OFFSET(n, i))
0093 #define DISPC_OVL_PRELOAD(n)        (DISPC_OVL_BASE(n) + \
0094                     DISPC_PRELOAD_OFFSET(n))
0095 #define DISPC_OVL_MFLAG_THRESHOLD(n)    DISPC_MFLAG_THRESHOLD_OFFSET(n)
0096 
0097 /* DISPC up/downsampling FIR filter coefficient structure */
0098 struct dispc_coef {
0099     s8 hc4_vc22;
0100     s8 hc3_vc2;
0101     u8 hc2_vc1;
0102     s8 hc1_vc0;
0103     s8 hc0_vc00;
0104 };
0105 
0106 const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
0107 
0108 /* DISPC manager/channel specific registers */
0109 static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
0110 {
0111     switch (channel) {
0112     case OMAP_DSS_CHANNEL_LCD:
0113         return 0x004C;
0114     case OMAP_DSS_CHANNEL_DIGIT:
0115         return 0x0050;
0116     case OMAP_DSS_CHANNEL_LCD2:
0117         return 0x03AC;
0118     case OMAP_DSS_CHANNEL_LCD3:
0119         return 0x0814;
0120     default:
0121         BUG();
0122         return 0;
0123     }
0124 }
0125 
0126 static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
0127 {
0128     switch (channel) {
0129     case OMAP_DSS_CHANNEL_LCD:
0130         return 0x0054;
0131     case OMAP_DSS_CHANNEL_DIGIT:
0132         return 0x0058;
0133     case OMAP_DSS_CHANNEL_LCD2:
0134         return 0x03B0;
0135     case OMAP_DSS_CHANNEL_LCD3:
0136         return 0x0818;
0137     default:
0138         BUG();
0139         return 0;
0140     }
0141 }
0142 
0143 static inline u16 DISPC_TIMING_H(enum omap_channel channel)
0144 {
0145     switch (channel) {
0146     case OMAP_DSS_CHANNEL_LCD:
0147         return 0x0064;
0148     case OMAP_DSS_CHANNEL_DIGIT:
0149         BUG();
0150         return 0;
0151     case OMAP_DSS_CHANNEL_LCD2:
0152         return 0x0400;
0153     case OMAP_DSS_CHANNEL_LCD3:
0154         return 0x0840;
0155     default:
0156         BUG();
0157         return 0;
0158     }
0159 }
0160 
0161 static inline u16 DISPC_TIMING_V(enum omap_channel channel)
0162 {
0163     switch (channel) {
0164     case OMAP_DSS_CHANNEL_LCD:
0165         return 0x0068;
0166     case OMAP_DSS_CHANNEL_DIGIT:
0167         BUG();
0168         return 0;
0169     case OMAP_DSS_CHANNEL_LCD2:
0170         return 0x0404;
0171     case OMAP_DSS_CHANNEL_LCD3:
0172         return 0x0844;
0173     default:
0174         BUG();
0175         return 0;
0176     }
0177 }
0178 
0179 static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
0180 {
0181     switch (channel) {
0182     case OMAP_DSS_CHANNEL_LCD:
0183         return 0x006C;
0184     case OMAP_DSS_CHANNEL_DIGIT:
0185         BUG();
0186         return 0;
0187     case OMAP_DSS_CHANNEL_LCD2:
0188         return 0x0408;
0189     case OMAP_DSS_CHANNEL_LCD3:
0190         return 0x083C;
0191     default:
0192         BUG();
0193         return 0;
0194     }
0195 }
0196 
0197 static inline u16 DISPC_DIVISORo(enum omap_channel channel)
0198 {
0199     switch (channel) {
0200     case OMAP_DSS_CHANNEL_LCD:
0201         return 0x0070;
0202     case OMAP_DSS_CHANNEL_DIGIT:
0203         BUG();
0204         return 0;
0205     case OMAP_DSS_CHANNEL_LCD2:
0206         return 0x040C;
0207     case OMAP_DSS_CHANNEL_LCD3:
0208         return 0x0838;
0209     default:
0210         BUG();
0211         return 0;
0212     }
0213 }
0214 
0215 /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
0216 static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
0217 {
0218     switch (channel) {
0219     case OMAP_DSS_CHANNEL_LCD:
0220         return 0x007C;
0221     case OMAP_DSS_CHANNEL_DIGIT:
0222         return 0x0078;
0223     case OMAP_DSS_CHANNEL_LCD2:
0224         return 0x03CC;
0225     case OMAP_DSS_CHANNEL_LCD3:
0226         return 0x0834;
0227     default:
0228         BUG();
0229         return 0;
0230     }
0231 }
0232 
0233 static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
0234 {
0235     switch (channel) {
0236     case OMAP_DSS_CHANNEL_LCD:
0237         return 0x01D4;
0238     case OMAP_DSS_CHANNEL_DIGIT:
0239         BUG();
0240         return 0;
0241     case OMAP_DSS_CHANNEL_LCD2:
0242         return 0x03C0;
0243     case OMAP_DSS_CHANNEL_LCD3:
0244         return 0x0828;
0245     default:
0246         BUG();
0247         return 0;
0248     }
0249 }
0250 
0251 static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
0252 {
0253     switch (channel) {
0254     case OMAP_DSS_CHANNEL_LCD:
0255         return 0x01D8;
0256     case OMAP_DSS_CHANNEL_DIGIT:
0257         BUG();
0258         return 0;
0259     case OMAP_DSS_CHANNEL_LCD2:
0260         return 0x03C4;
0261     case OMAP_DSS_CHANNEL_LCD3:
0262         return 0x082C;
0263     default:
0264         BUG();
0265         return 0;
0266     }
0267 }
0268 
0269 static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
0270 {
0271     switch (channel) {
0272     case OMAP_DSS_CHANNEL_LCD:
0273         return 0x01DC;
0274     case OMAP_DSS_CHANNEL_DIGIT:
0275         BUG();
0276         return 0;
0277     case OMAP_DSS_CHANNEL_LCD2:
0278         return 0x03C8;
0279     case OMAP_DSS_CHANNEL_LCD3:
0280         return 0x0830;
0281     default:
0282         BUG();
0283         return 0;
0284     }
0285 }
0286 
0287 static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
0288 {
0289     switch (channel) {
0290     case OMAP_DSS_CHANNEL_LCD:
0291         return 0x0220;
0292     case OMAP_DSS_CHANNEL_DIGIT:
0293         BUG();
0294         return 0;
0295     case OMAP_DSS_CHANNEL_LCD2:
0296         return 0x03BC;
0297     case OMAP_DSS_CHANNEL_LCD3:
0298         return 0x0824;
0299     default:
0300         BUG();
0301         return 0;
0302     }
0303 }
0304 
0305 static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
0306 {
0307     switch (channel) {
0308     case OMAP_DSS_CHANNEL_LCD:
0309         return 0x0224;
0310     case OMAP_DSS_CHANNEL_DIGIT:
0311         BUG();
0312         return 0;
0313     case OMAP_DSS_CHANNEL_LCD2:
0314         return 0x03B8;
0315     case OMAP_DSS_CHANNEL_LCD3:
0316         return 0x0820;
0317     default:
0318         BUG();
0319         return 0;
0320     }
0321 }
0322 
0323 static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
0324 {
0325     switch (channel) {
0326     case OMAP_DSS_CHANNEL_LCD:
0327         return 0x0228;
0328     case OMAP_DSS_CHANNEL_DIGIT:
0329         BUG();
0330         return 0;
0331     case OMAP_DSS_CHANNEL_LCD2:
0332         return 0x03B4;
0333     case OMAP_DSS_CHANNEL_LCD3:
0334         return 0x081C;
0335     default:
0336         BUG();
0337         return 0;
0338     }
0339 }
0340 
0341 /* DISPC overlay register base addresses */
0342 static inline u16 DISPC_OVL_BASE(enum omap_plane_id plane)
0343 {
0344     switch (plane) {
0345     case OMAP_DSS_GFX:
0346         return 0x0080;
0347     case OMAP_DSS_VIDEO1:
0348         return 0x00BC;
0349     case OMAP_DSS_VIDEO2:
0350         return 0x014C;
0351     case OMAP_DSS_VIDEO3:
0352         return 0x0300;
0353     case OMAP_DSS_WB:
0354         return 0x0500;
0355     default:
0356         BUG();
0357         return 0;
0358     }
0359 }
0360 
0361 /* DISPC overlay register offsets */
0362 static inline u16 DISPC_BA0_OFFSET(enum omap_plane_id plane)
0363 {
0364     switch (plane) {
0365     case OMAP_DSS_GFX:
0366     case OMAP_DSS_VIDEO1:
0367     case OMAP_DSS_VIDEO2:
0368         return 0x0000;
0369     case OMAP_DSS_VIDEO3:
0370     case OMAP_DSS_WB:
0371         return 0x0008;
0372     default:
0373         BUG();
0374         return 0;
0375     }
0376 }
0377 
0378 static inline u16 DISPC_BA1_OFFSET(enum omap_plane_id plane)
0379 {
0380     switch (plane) {
0381     case OMAP_DSS_GFX:
0382     case OMAP_DSS_VIDEO1:
0383     case OMAP_DSS_VIDEO2:
0384         return 0x0004;
0385     case OMAP_DSS_VIDEO3:
0386     case OMAP_DSS_WB:
0387         return 0x000C;
0388     default:
0389         BUG();
0390         return 0;
0391     }
0392 }
0393 
0394 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane_id plane)
0395 {
0396     switch (plane) {
0397     case OMAP_DSS_GFX:
0398         BUG();
0399         return 0;
0400     case OMAP_DSS_VIDEO1:
0401         return 0x0544;
0402     case OMAP_DSS_VIDEO2:
0403         return 0x04BC;
0404     case OMAP_DSS_VIDEO3:
0405         return 0x0310;
0406     case OMAP_DSS_WB:
0407         return 0x0118;
0408     default:
0409         BUG();
0410         return 0;
0411     }
0412 }
0413 
0414 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane_id plane)
0415 {
0416     switch (plane) {
0417     case OMAP_DSS_GFX:
0418         BUG();
0419         return 0;
0420     case OMAP_DSS_VIDEO1:
0421         return 0x0548;
0422     case OMAP_DSS_VIDEO2:
0423         return 0x04C0;
0424     case OMAP_DSS_VIDEO3:
0425         return 0x0314;
0426     case OMAP_DSS_WB:
0427         return 0x011C;
0428     default:
0429         BUG();
0430         return 0;
0431     }
0432 }
0433 
0434 static inline u16 DISPC_POS_OFFSET(enum omap_plane_id plane)
0435 {
0436     switch (plane) {
0437     case OMAP_DSS_GFX:
0438     case OMAP_DSS_VIDEO1:
0439     case OMAP_DSS_VIDEO2:
0440         return 0x0008;
0441     case OMAP_DSS_VIDEO3:
0442         return 0x009C;
0443     default:
0444         BUG();
0445         return 0;
0446     }
0447 }
0448 
0449 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane_id plane)
0450 {
0451     switch (plane) {
0452     case OMAP_DSS_GFX:
0453     case OMAP_DSS_VIDEO1:
0454     case OMAP_DSS_VIDEO2:
0455         return 0x000C;
0456     case OMAP_DSS_VIDEO3:
0457     case OMAP_DSS_WB:
0458         return 0x00A8;
0459     default:
0460         BUG();
0461         return 0;
0462     }
0463 }
0464 
0465 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane_id plane)
0466 {
0467     switch (plane) {
0468     case OMAP_DSS_GFX:
0469         return 0x0020;
0470     case OMAP_DSS_VIDEO1:
0471     case OMAP_DSS_VIDEO2:
0472         return 0x0010;
0473     case OMAP_DSS_VIDEO3:
0474     case OMAP_DSS_WB:
0475         return 0x0070;
0476     default:
0477         BUG();
0478         return 0;
0479     }
0480 }
0481 
0482 static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane_id plane)
0483 {
0484     switch (plane) {
0485     case OMAP_DSS_GFX:
0486         BUG();
0487         return 0;
0488     case OMAP_DSS_VIDEO1:
0489         return 0x0568;
0490     case OMAP_DSS_VIDEO2:
0491         return 0x04DC;
0492     case OMAP_DSS_VIDEO3:
0493         return 0x032C;
0494     case OMAP_DSS_WB:
0495         return 0x0310;
0496     default:
0497         BUG();
0498         return 0;
0499     }
0500 }
0501 
0502 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane_id plane)
0503 {
0504     switch (plane) {
0505     case OMAP_DSS_GFX:
0506         return 0x0024;
0507     case OMAP_DSS_VIDEO1:
0508     case OMAP_DSS_VIDEO2:
0509         return 0x0014;
0510     case OMAP_DSS_VIDEO3:
0511     case OMAP_DSS_WB:
0512         return 0x008C;
0513     default:
0514         BUG();
0515         return 0;
0516     }
0517 }
0518 
0519 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane_id plane)
0520 {
0521     switch (plane) {
0522     case OMAP_DSS_GFX:
0523         return 0x0028;
0524     case OMAP_DSS_VIDEO1:
0525     case OMAP_DSS_VIDEO2:
0526         return 0x0018;
0527     case OMAP_DSS_VIDEO3:
0528     case OMAP_DSS_WB:
0529         return 0x0088;
0530     default:
0531         BUG();
0532         return 0;
0533     }
0534 }
0535 
0536 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane_id plane)
0537 {
0538     switch (plane) {
0539     case OMAP_DSS_GFX:
0540         return 0x002C;
0541     case OMAP_DSS_VIDEO1:
0542     case OMAP_DSS_VIDEO2:
0543         return 0x001C;
0544     case OMAP_DSS_VIDEO3:
0545     case OMAP_DSS_WB:
0546         return 0x00A4;
0547     default:
0548         BUG();
0549         return 0;
0550     }
0551 }
0552 
0553 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane_id plane)
0554 {
0555     switch (plane) {
0556     case OMAP_DSS_GFX:
0557         return 0x0030;
0558     case OMAP_DSS_VIDEO1:
0559     case OMAP_DSS_VIDEO2:
0560         return 0x0020;
0561     case OMAP_DSS_VIDEO3:
0562     case OMAP_DSS_WB:
0563         return 0x0098;
0564     default:
0565         BUG();
0566         return 0;
0567     }
0568 }
0569 
0570 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane_id plane)
0571 {
0572     switch (plane) {
0573     case OMAP_DSS_GFX:
0574         return 0x0034;
0575     case OMAP_DSS_VIDEO1:
0576     case OMAP_DSS_VIDEO2:
0577     case OMAP_DSS_VIDEO3:
0578         BUG();
0579         return 0;
0580     default:
0581         BUG();
0582         return 0;
0583     }
0584 }
0585 
0586 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane_id plane)
0587 {
0588     switch (plane) {
0589     case OMAP_DSS_GFX:
0590         return 0x0038;
0591     case OMAP_DSS_VIDEO1:
0592     case OMAP_DSS_VIDEO2:
0593     case OMAP_DSS_VIDEO3:
0594         BUG();
0595         return 0;
0596     default:
0597         BUG();
0598         return 0;
0599     }
0600 }
0601 
0602 static inline u16 DISPC_FIR_OFFSET(enum omap_plane_id plane)
0603 {
0604     switch (plane) {
0605     case OMAP_DSS_GFX:
0606         BUG();
0607         return 0;
0608     case OMAP_DSS_VIDEO1:
0609     case OMAP_DSS_VIDEO2:
0610         return 0x0024;
0611     case OMAP_DSS_VIDEO3:
0612     case OMAP_DSS_WB:
0613         return 0x0090;
0614     default:
0615         BUG();
0616         return 0;
0617     }
0618 }
0619 
0620 static inline u16 DISPC_FIR2_OFFSET(enum omap_plane_id plane)
0621 {
0622     switch (plane) {
0623     case OMAP_DSS_GFX:
0624         BUG();
0625         return 0;
0626     case OMAP_DSS_VIDEO1:
0627         return 0x0580;
0628     case OMAP_DSS_VIDEO2:
0629         return 0x055C;
0630     case OMAP_DSS_VIDEO3:
0631         return 0x0424;
0632     case OMAP_DSS_WB:
0633         return 0x290;
0634     default:
0635         BUG();
0636         return 0;
0637     }
0638 }
0639 
0640 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane_id plane)
0641 {
0642     switch (plane) {
0643     case OMAP_DSS_GFX:
0644         BUG();
0645         return 0;
0646     case OMAP_DSS_VIDEO1:
0647     case OMAP_DSS_VIDEO2:
0648         return 0x0028;
0649     case OMAP_DSS_VIDEO3:
0650     case OMAP_DSS_WB:
0651         return 0x0094;
0652     default:
0653         BUG();
0654         return 0;
0655     }
0656 }
0657 
0658 
0659 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane_id plane)
0660 {
0661     switch (plane) {
0662     case OMAP_DSS_GFX:
0663         BUG();
0664         return 0;
0665     case OMAP_DSS_VIDEO1:
0666     case OMAP_DSS_VIDEO2:
0667         return 0x002C;
0668     case OMAP_DSS_VIDEO3:
0669     case OMAP_DSS_WB:
0670         return 0x0000;
0671     default:
0672         BUG();
0673         return 0;
0674     }
0675 }
0676 
0677 static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane_id plane)
0678 {
0679     switch (plane) {
0680     case OMAP_DSS_GFX:
0681         BUG();
0682         return 0;
0683     case OMAP_DSS_VIDEO1:
0684         return 0x0584;
0685     case OMAP_DSS_VIDEO2:
0686         return 0x0560;
0687     case OMAP_DSS_VIDEO3:
0688         return 0x0428;
0689     case OMAP_DSS_WB:
0690         return 0x0294;
0691     default:
0692         BUG();
0693         return 0;
0694     }
0695 }
0696 
0697 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane_id plane)
0698 {
0699     switch (plane) {
0700     case OMAP_DSS_GFX:
0701         BUG();
0702         return 0;
0703     case OMAP_DSS_VIDEO1:
0704     case OMAP_DSS_VIDEO2:
0705         return 0x0030;
0706     case OMAP_DSS_VIDEO3:
0707     case OMAP_DSS_WB:
0708         return 0x0004;
0709     default:
0710         BUG();
0711         return 0;
0712     }
0713 }
0714 
0715 static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane_id plane)
0716 {
0717     switch (plane) {
0718     case OMAP_DSS_GFX:
0719         BUG();
0720         return 0;
0721     case OMAP_DSS_VIDEO1:
0722         return 0x0588;
0723     case OMAP_DSS_VIDEO2:
0724         return 0x0564;
0725     case OMAP_DSS_VIDEO3:
0726         return 0x042C;
0727     case OMAP_DSS_WB:
0728         return 0x0298;
0729     default:
0730         BUG();
0731         return 0;
0732     }
0733 }
0734 
0735 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
0736 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane_id plane, u16 i)
0737 {
0738     switch (plane) {
0739     case OMAP_DSS_GFX:
0740         BUG();
0741         return 0;
0742     case OMAP_DSS_VIDEO1:
0743     case OMAP_DSS_VIDEO2:
0744         return 0x0034 + i * 0x8;
0745     case OMAP_DSS_VIDEO3:
0746     case OMAP_DSS_WB:
0747         return 0x0010 + i * 0x8;
0748     default:
0749         BUG();
0750         return 0;
0751     }
0752 }
0753 
0754 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
0755 static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane_id plane, u16 i)
0756 {
0757     switch (plane) {
0758     case OMAP_DSS_GFX:
0759         BUG();
0760         return 0;
0761     case OMAP_DSS_VIDEO1:
0762         return 0x058C + i * 0x8;
0763     case OMAP_DSS_VIDEO2:
0764         return 0x0568 + i * 0x8;
0765     case OMAP_DSS_VIDEO3:
0766         return 0x0430 + i * 0x8;
0767     case OMAP_DSS_WB:
0768         return 0x02A0 + i * 0x8;
0769     default:
0770         BUG();
0771         return 0;
0772     }
0773 }
0774 
0775 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
0776 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane_id plane, u16 i)
0777 {
0778     switch (plane) {
0779     case OMAP_DSS_GFX:
0780         BUG();
0781         return 0;
0782     case OMAP_DSS_VIDEO1:
0783     case OMAP_DSS_VIDEO2:
0784         return 0x0038 + i * 0x8;
0785     case OMAP_DSS_VIDEO3:
0786     case OMAP_DSS_WB:
0787         return 0x0014 + i * 0x8;
0788     default:
0789         BUG();
0790         return 0;
0791     }
0792 }
0793 
0794 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
0795 static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane_id plane, u16 i)
0796 {
0797     switch (plane) {
0798     case OMAP_DSS_GFX:
0799         BUG();
0800         return 0;
0801     case OMAP_DSS_VIDEO1:
0802         return 0x0590 + i * 8;
0803     case OMAP_DSS_VIDEO2:
0804         return 0x056C + i * 0x8;
0805     case OMAP_DSS_VIDEO3:
0806         return 0x0434 + i * 0x8;
0807     case OMAP_DSS_WB:
0808         return 0x02A4 + i * 0x8;
0809     default:
0810         BUG();
0811         return 0;
0812     }
0813 }
0814 
0815 /* coef index i = {0, 1, 2, 3, 4,} */
0816 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane_id plane, u16 i)
0817 {
0818     switch (plane) {
0819     case OMAP_DSS_GFX:
0820         BUG();
0821         return 0;
0822     case OMAP_DSS_VIDEO1:
0823     case OMAP_DSS_VIDEO2:
0824     case OMAP_DSS_VIDEO3:
0825     case OMAP_DSS_WB:
0826         return 0x0074 + i * 0x4;
0827     default:
0828         BUG();
0829         return 0;
0830     }
0831 }
0832 
0833 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
0834 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane_id plane, u16 i)
0835 {
0836     switch (plane) {
0837     case OMAP_DSS_GFX:
0838         BUG();
0839         return 0;
0840     case OMAP_DSS_VIDEO1:
0841         return 0x0124 + i * 0x4;
0842     case OMAP_DSS_VIDEO2:
0843         return 0x00B4 + i * 0x4;
0844     case OMAP_DSS_VIDEO3:
0845     case OMAP_DSS_WB:
0846         return 0x0050 + i * 0x4;
0847     default:
0848         BUG();
0849         return 0;
0850     }
0851 }
0852 
0853 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
0854 static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane_id plane, u16 i)
0855 {
0856     switch (plane) {
0857     case OMAP_DSS_GFX:
0858         BUG();
0859         return 0;
0860     case OMAP_DSS_VIDEO1:
0861         return 0x05CC + i * 0x4;
0862     case OMAP_DSS_VIDEO2:
0863         return 0x05A8 + i * 0x4;
0864     case OMAP_DSS_VIDEO3:
0865         return 0x0470 + i * 0x4;
0866     case OMAP_DSS_WB:
0867         return 0x02E0 + i * 0x4;
0868     default:
0869         BUG();
0870         return 0;
0871     }
0872 }
0873 
0874 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane_id plane)
0875 {
0876     switch (plane) {
0877     case OMAP_DSS_GFX:
0878         return 0x01AC;
0879     case OMAP_DSS_VIDEO1:
0880         return 0x0174;
0881     case OMAP_DSS_VIDEO2:
0882         return 0x00E8;
0883     case OMAP_DSS_VIDEO3:
0884         return 0x00A0;
0885     default:
0886         BUG();
0887         return 0;
0888     }
0889 }
0890 
0891 static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane_id plane)
0892 {
0893     switch (plane) {
0894     case OMAP_DSS_GFX:
0895         return 0x0860;
0896     case OMAP_DSS_VIDEO1:
0897         return 0x0864;
0898     case OMAP_DSS_VIDEO2:
0899         return 0x0868;
0900     case OMAP_DSS_VIDEO3:
0901         return 0x086c;
0902     case OMAP_DSS_WB:
0903         return 0x0870;
0904     default:
0905         BUG();
0906         return 0;
0907     }
0908 }
0909 #endif
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