subdev/timer/nv04.c

0001 /*
0002  * Copyright 2012 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Ben Skeggs
0023  */
0024 #include "priv.h"
0025 #include "regsnv04.h"
0026
0027 void
0028 nv04_timer_time(struct nvkm_timer *tmr, u64 time)
0029 {
0030     struct nvkm_subdev *subdev = &tmr->subdev;
0031     struct nvkm_device *device = subdev->device;
0032     u32 hi = upper_32_bits(time);
0033     u32 lo = lower_32_bits(time);
0034
0035     nvkm_debug(subdev, "time low        : %08x\n", lo);
0036     nvkm_debug(subdev, "time high       : %08x\n", hi);
0037
0038     nvkm_wr32(device, NV04_PTIMER_TIME_1, hi);
0039     nvkm_wr32(device, NV04_PTIMER_TIME_0, lo);
0040 }
0041
0042 u64
0043 nv04_timer_read(struct nvkm_timer *tmr)
0044 {
0045     struct nvkm_device *device = tmr->subdev.device;
0046     u32 hi, lo;
0047
0048     do {
0049         hi = nvkm_rd32(device, NV04_PTIMER_TIME_1);
0050         lo = nvkm_rd32(device, NV04_PTIMER_TIME_0);
0051     } while (hi != nvkm_rd32(device, NV04_PTIMER_TIME_1));
0052
0053     return ((u64)hi << 32 | lo);
0054 }
0055
0056 void
0057 nv04_timer_alarm_fini(struct nvkm_timer *tmr)
0058 {
0059     struct nvkm_device *device = tmr->subdev.device;
0060     nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000000);
0061 }
0062
0063 void
0064 nv04_timer_alarm_init(struct nvkm_timer *tmr, u32 time)
0065 {
0066     struct nvkm_device *device = tmr->subdev.device;
0067     nvkm_wr32(device, NV04_PTIMER_ALARM_0, time);
0068     nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000001);
0069 }
0070
0071 void
0072 nv04_timer_intr(struct nvkm_timer *tmr)
0073 {
0074     struct nvkm_subdev *subdev = &tmr->subdev;
0075     struct nvkm_device *device = subdev->device;
0076     u32 stat = nvkm_rd32(device, NV04_PTIMER_INTR_0);
0077
0078     if (stat & 0x00000001) {
0079         nvkm_wr32(device, NV04_PTIMER_INTR_0, 0x00000001);
0080         nvkm_timer_alarm_trigger(tmr);
0081         stat &= ~0x00000001;
0082     }
0083
0084     if (stat) {
0085         nvkm_error(subdev, "intr %08x\n", stat);
0086         nvkm_wr32(device, NV04_PTIMER_INTR_0, stat);
0087     }
0088 }
0089
0090 static void
0091 nv04_timer_init(struct nvkm_timer *tmr)
0092 {
0093     struct nvkm_subdev *subdev = &tmr->subdev;
0094     struct nvkm_device *device = subdev->device;
0095     u32 f = 0; /*XXX: nvclk */
0096     u32 n, d;
0097
0098     /* aim for 31.25MHz, which gives us nanosecond timestamps */
0099     d = 1000000 / 32;
0100     n = f;
0101
0102     if (!f) {
0103         n = nvkm_rd32(device, NV04_PTIMER_NUMERATOR);
0104         d = nvkm_rd32(device, NV04_PTIMER_DENOMINATOR);
0105         if (!n || !d) {
0106             n = 1;
0107             d = 1;
0108         }
0109         nvkm_warn(subdev, "unknown input clock freq\n");
0110     }
0111
0112     /* reduce ratio to acceptable values */
0113     while (((n % 5) == 0) && ((d % 5) == 0)) {
0114         n /= 5;
0115         d /= 5;
0116     }
0117
0118     while (((n % 2) == 0) && ((d % 2) == 0)) {
0119         n /= 2;
0120         d /= 2;
0121     }
0122
0123     while (n > 0xffff || d > 0xffff) {
0124         n >>= 1;
0125         d >>= 1;
0126     }
0127
0128     nvkm_debug(subdev, "input frequency : %dHz\n", f);
0129     nvkm_debug(subdev, "numerator       : %08x\n", n);
0130     nvkm_debug(subdev, "denominator     : %08x\n", d);
0131     nvkm_debug(subdev, "timer frequency : %dHz\n", f * d / n);
0132
0133     nvkm_wr32(device, NV04_PTIMER_NUMERATOR, n);
0134     nvkm_wr32(device, NV04_PTIMER_DENOMINATOR, d);
0135 }
0136
0137 static const struct nvkm_timer_func
0138 nv04_timer = {
0139     .init = nv04_timer_init,
0140     .intr = nv04_timer_intr,
0141     .read = nv04_timer_read,
0142     .time = nv04_timer_time,
0143     .alarm_init = nv04_timer_alarm_init,
0144     .alarm_fini = nv04_timer_alarm_fini,
0145 };
0146
0147 int
0148 nv04_timer_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
0149            struct nvkm_timer **ptmr)
0150 {
0151     return nvkm_timer_new_(&nv04_timer, device, type, inst, ptmr);
0152 }