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0025 #include "priv.h"
0026
0027 #include <subdev/fuse.h>
0028
0029 int
0030 g84_temp_get(struct nvkm_therm *therm)
0031 {
0032 struct nvkm_device *device = therm->subdev.device;
0033
0034 if (nvkm_fuse_read(device->fuse, 0x1a8) == 1)
0035 return nvkm_rd32(device, 0x20400);
0036 else
0037 return -ENODEV;
0038 }
0039
0040 void
0041 g84_sensor_setup(struct nvkm_therm *therm)
0042 {
0043 struct nvkm_device *device = therm->subdev.device;
0044
0045
0046 if (nvkm_fuse_read(device->fuse, 0x1a8) == 1) {
0047 nvkm_mask(device, 0x20008, 0x80008000, 0x80000000);
0048 nvkm_mask(device, 0x2000c, 0x80000003, 0x00000000);
0049 mdelay(20);
0050 }
0051 }
0052
0053 static void
0054 g84_therm_program_alarms(struct nvkm_therm *therm)
0055 {
0056 struct nvbios_therm_sensor *sensor = &therm->bios_sensor;
0057 struct nvkm_subdev *subdev = &therm->subdev;
0058 struct nvkm_device *device = subdev->device;
0059 unsigned long flags;
0060
0061 spin_lock_irqsave(&therm->sensor.alarm_program_lock, flags);
0062
0063
0064 nvkm_wr32(device, 0x20000, 0x000003ff);
0065
0066
0067 nvkm_wr32(device, 0x20484, sensor->thrs_shutdown.hysteresis);
0068 nvkm_wr32(device, 0x20480, sensor->thrs_shutdown.temp);
0069
0070
0071 nvkm_wr32(device, 0x204c4, sensor->thrs_fan_boost.temp);
0072
0073
0074 nvkm_wr32(device, 0x204c0, sensor->thrs_critical.temp);
0075
0076
0077 nvkm_wr32(device, 0x20414, sensor->thrs_down_clock.temp);
0078 spin_unlock_irqrestore(&therm->sensor.alarm_program_lock, flags);
0079
0080 nvkm_debug(subdev,
0081 "Programmed thresholds [ %d(%d), %d(%d), %d(%d), %d(%d) ]\n",
0082 sensor->thrs_fan_boost.temp,
0083 sensor->thrs_fan_boost.hysteresis,
0084 sensor->thrs_down_clock.temp,
0085 sensor->thrs_down_clock.hysteresis,
0086 sensor->thrs_critical.temp,
0087 sensor->thrs_critical.hysteresis,
0088 sensor->thrs_shutdown.temp,
0089 sensor->thrs_shutdown.hysteresis);
0090
0091 }
0092
0093
0094 static void
0095 g84_therm_threshold_hyst_emulation(struct nvkm_therm *therm,
0096 uint32_t thrs_reg, u8 status_bit,
0097 const struct nvbios_therm_threshold *thrs,
0098 enum nvkm_therm_thrs thrs_name)
0099 {
0100 struct nvkm_device *device = therm->subdev.device;
0101 enum nvkm_therm_thrs_direction direction;
0102 enum nvkm_therm_thrs_state prev_state, new_state;
0103 int temp, cur;
0104
0105 prev_state = nvkm_therm_sensor_get_threshold_state(therm, thrs_name);
0106 temp = nvkm_rd32(device, thrs_reg);
0107
0108
0109 if (temp == thrs->temp) {
0110 nvkm_wr32(device, thrs_reg, thrs->temp - thrs->hysteresis);
0111 new_state = NVKM_THERM_THRS_HIGHER;
0112 } else {
0113 nvkm_wr32(device, thrs_reg, thrs->temp);
0114 new_state = NVKM_THERM_THRS_LOWER;
0115 }
0116
0117
0118 cur = therm->func->temp_get(therm);
0119 if (new_state == NVKM_THERM_THRS_LOWER && cur > thrs->temp)
0120 new_state = NVKM_THERM_THRS_HIGHER;
0121 else if (new_state == NVKM_THERM_THRS_HIGHER &&
0122 cur < thrs->temp - thrs->hysteresis)
0123 new_state = NVKM_THERM_THRS_LOWER;
0124 nvkm_therm_sensor_set_threshold_state(therm, thrs_name, new_state);
0125
0126
0127 if (prev_state < new_state)
0128 direction = NVKM_THERM_THRS_RISING;
0129 else if (prev_state > new_state)
0130 direction = NVKM_THERM_THRS_FALLING;
0131 else
0132 return;
0133
0134
0135 nvkm_therm_sensor_event(therm, thrs_name, direction);
0136 }
0137
0138 static void
0139 g84_therm_intr(struct nvkm_therm *therm)
0140 {
0141 struct nvkm_subdev *subdev = &therm->subdev;
0142 struct nvkm_device *device = subdev->device;
0143 struct nvbios_therm_sensor *sensor = &therm->bios_sensor;
0144 unsigned long flags;
0145 uint32_t intr;
0146
0147 spin_lock_irqsave(&therm->sensor.alarm_program_lock, flags);
0148
0149 intr = nvkm_rd32(device, 0x20100) & 0x3ff;
0150
0151
0152 if (intr & 0x002) {
0153 g84_therm_threshold_hyst_emulation(therm, 0x20414, 24,
0154 &sensor->thrs_down_clock,
0155 NVKM_THERM_THRS_DOWNCLOCK);
0156 intr &= ~0x002;
0157 }
0158
0159
0160 if (intr & 0x004) {
0161 g84_therm_threshold_hyst_emulation(therm, 0x20480, 20,
0162 &sensor->thrs_shutdown,
0163 NVKM_THERM_THRS_SHUTDOWN);
0164 intr &= ~0x004;
0165 }
0166
0167
0168 if (intr & 0x008) {
0169 g84_therm_threshold_hyst_emulation(therm, 0x204c4, 21,
0170 &sensor->thrs_fan_boost,
0171 NVKM_THERM_THRS_FANBOOST);
0172 intr &= ~0x008;
0173 }
0174
0175
0176 if (intr & 0x010) {
0177 g84_therm_threshold_hyst_emulation(therm, 0x204c0, 22,
0178 &sensor->thrs_critical,
0179 NVKM_THERM_THRS_CRITICAL);
0180 intr &= ~0x010;
0181 }
0182
0183 if (intr)
0184 nvkm_error(subdev, "intr %08x\n", intr);
0185
0186
0187 nvkm_wr32(device, 0x20100, 0xffffffff);
0188 nvkm_wr32(device, 0x1100, 0x10000);
0189
0190 spin_unlock_irqrestore(&therm->sensor.alarm_program_lock, flags);
0191 }
0192
0193 void
0194 g84_therm_fini(struct nvkm_therm *therm)
0195 {
0196 struct nvkm_device *device = therm->subdev.device;
0197
0198
0199 nvkm_wr32(device, 0x20000, 0x00000000);
0200
0201
0202 nvkm_wr32(device, 0x20100, 0xffffffff);
0203 nvkm_wr32(device, 0x1100, 0x10000);
0204 }
0205
0206 void
0207 g84_therm_init(struct nvkm_therm *therm)
0208 {
0209 g84_sensor_setup(therm);
0210 }
0211
0212 static const struct nvkm_therm_func
0213 g84_therm = {
0214 .init = g84_therm_init,
0215 .fini = g84_therm_fini,
0216 .intr = g84_therm_intr,
0217 .pwm_ctrl = nv50_fan_pwm_ctrl,
0218 .pwm_get = nv50_fan_pwm_get,
0219 .pwm_set = nv50_fan_pwm_set,
0220 .pwm_clock = nv50_fan_pwm_clock,
0221 .temp_get = g84_temp_get,
0222 .program_alarms = g84_therm_program_alarms,
0223 };
0224
0225 int
0226 g84_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
0227 struct nvkm_therm **ptherm)
0228 {
0229 struct nvkm_therm *therm;
0230 int ret;
0231
0232 ret = nvkm_therm_new_(&g84_therm, device, type, inst, &therm);
0233 *ptherm = therm;
0234 if (ret)
0235 return ret;
0236
0237
0238 nvkm_therm_sensor_set_threshold_state(therm, NVKM_THERM_THRS_SHUTDOWN,
0239 NVKM_THERM_THRS_LOWER);
0240 nvkm_therm_sensor_set_threshold_state(therm, NVKM_THERM_THRS_FANBOOST,
0241 NVKM_THERM_THRS_LOWER);
0242 nvkm_therm_sensor_set_threshold_state(therm, NVKM_THERM_THRS_CRITICAL,
0243 NVKM_THERM_THRS_LOWER);
0244 nvkm_therm_sensor_set_threshold_state(therm, NVKM_THERM_THRS_DOWNCLOCK,
0245 NVKM_THERM_THRS_LOWER);
0246 return 0;
0247 }