subdev/pmu/memx.c

0001 // SPDX-License-Identifier: MIT
0002 #ifndef __NVKM_PMU_MEMX_H__
0003 #define __NVKM_PMU_MEMX_H__
0004 #include "priv.h"
0005
0006 struct nvkm_memx {
0007     struct nvkm_pmu *pmu;
0008     u32 base;
0009     u32 size;
0010     struct {
0011         u32 mthd;
0012         u32 size;
0013         u32 data[64];
0014     } c;
0015 };
0016
0017 static void
0018 memx_out(struct nvkm_memx *memx)
0019 {
0020     struct nvkm_device *device = memx->pmu->subdev.device;
0021     int i;
0022
0023     if (memx->c.mthd) {
0024         nvkm_wr32(device, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd);
0025         for (i = 0; i < memx->c.size; i++)
0026             nvkm_wr32(device, 0x10a1c4, memx->c.data[i]);
0027         memx->c.mthd = 0;
0028         memx->c.size = 0;
0029     }
0030 }
0031
0032 static void
0033 memx_cmd(struct nvkm_memx *memx, u32 mthd, u32 size, u32 data[])
0034 {
0035     if ((memx->c.size + size >= ARRAY_SIZE(memx->c.data)) ||
0036         (memx->c.mthd && memx->c.mthd != mthd))
0037         memx_out(memx);
0038     memcpy(&memx->c.data[memx->c.size], data, size * sizeof(data[0]));
0039     memx->c.size += size;
0040     memx->c.mthd  = mthd;
0041 }
0042
0043 int
0044 nvkm_memx_init(struct nvkm_pmu *pmu, struct nvkm_memx **pmemx)
0045 {
0046     struct nvkm_device *device = pmu->subdev.device;
0047     struct nvkm_memx *memx;
0048     u32 reply[2];
0049     int ret;
0050
0051     ret = nvkm_pmu_send(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
0052                 MEMX_INFO_DATA, 0);
0053     if (ret)
0054         return ret;
0055
0056     memx = *pmemx = kzalloc(sizeof(*memx), GFP_KERNEL);
0057     if (!memx)
0058         return -ENOMEM;
0059     memx->pmu = pmu;
0060     memx->base = reply[0];
0061     memx->size = reply[1];
0062
0063     /* acquire data segment access */
0064     do {
0065         nvkm_wr32(device, 0x10a580, 0x00000003);
0066     } while (nvkm_rd32(device, 0x10a580) != 0x00000003);
0067     nvkm_wr32(device, 0x10a1c0, 0x01000000 | memx->base);
0068     return 0;
0069 }
0070
0071 int
0072 nvkm_memx_fini(struct nvkm_memx **pmemx, bool exec)
0073 {
0074     struct nvkm_memx *memx = *pmemx;
0075     struct nvkm_pmu *pmu = memx->pmu;
0076     struct nvkm_subdev *subdev = &pmu->subdev;
0077     struct nvkm_device *device = subdev->device;
0078     u32 finish, reply[2];
0079
0080     /* flush the cache... */
0081     memx_out(memx);
0082
0083     /* release data segment access */
0084     finish = nvkm_rd32(device, 0x10a1c0) & 0x00ffffff;
0085     nvkm_wr32(device, 0x10a580, 0x00000000);
0086
0087     /* call MEMX process to execute the script, and wait for reply */
0088     if (exec) {
0089         nvkm_pmu_send(pmu, reply, PROC_MEMX, MEMX_MSG_EXEC,
0090                   memx->base, finish);
0091         nvkm_debug(subdev, "Exec took %uns, PMU_IN %08x\n",
0092                reply[0], reply[1]);
0093     }
0094
0095     kfree(memx);
0096     return 0;
0097 }
0098
0099 void
0100 nvkm_memx_wr32(struct nvkm_memx *memx, u32 addr, u32 data)
0101 {
0102     nvkm_debug(&memx->pmu->subdev, "R[%06x] = %08x\n", addr, data);
0103     memx_cmd(memx, MEMX_WR32, 2, (u32[]){ addr, data });
0104 }
0105
0106 void
0107 nvkm_memx_wait(struct nvkm_memx *memx,
0108           u32 addr, u32 mask, u32 data, u32 nsec)
0109 {
0110     nvkm_debug(&memx->pmu->subdev, "R[%06x] & %08x == %08x, %d us\n",
0111            addr, mask, data, nsec);
0112     memx_cmd(memx, MEMX_WAIT, 4, (u32[]){ addr, mask, data, nsec });
0113     memx_out(memx); /* fuc can't handle multiple */
0114 }
0115
0116 void
0117 nvkm_memx_nsec(struct nvkm_memx *memx, u32 nsec)
0118 {
0119     nvkm_debug(&memx->pmu->subdev, "    DELAY = %d ns\n", nsec);
0120     memx_cmd(memx, MEMX_DELAY, 1, (u32[]){ nsec });
0121     memx_out(memx); /* fuc can't handle multiple */
0122 }
0123
0124 void
0125 nvkm_memx_wait_vblank(struct nvkm_memx *memx)
0126 {
0127     struct nvkm_subdev *subdev = &memx->pmu->subdev;
0128     struct nvkm_device *device = subdev->device;
0129     u32 heads, x, y, px = 0;
0130     int i, head_sync;
0131
0132     if (device->chipset < 0xd0) {
0133         heads = nvkm_rd32(device, 0x610050);
0134         for (i = 0; i < 2; i++) {
0135             /* Heuristic: sync to head with biggest resolution */
0136             if (heads & (2 << (i << 3))) {
0137                 x = nvkm_rd32(device, 0x610b40 + (0x540 * i));
0138                 y = (x & 0xffff0000) >> 16;
0139                 x &= 0x0000ffff;
0140                 if ((x * y) > px) {
0141                     px = (x * y);
0142                     head_sync = i;
0143                 }
0144             }
0145         }
0146     }
0147
0148     if (px == 0) {
0149         nvkm_debug(subdev, "WAIT VBLANK !NO ACTIVE HEAD\n");
0150         return;
0151     }
0152
0153     nvkm_debug(subdev, "WAIT VBLANK HEAD%d\n", head_sync);
0154     memx_cmd(memx, MEMX_VBLANK, 1, (u32[]){ head_sync });
0155     memx_out(memx); /* fuc can't handle multiple */
0156 }
0157
0158 void
0159 nvkm_memx_train(struct nvkm_memx *memx)
0160 {
0161     nvkm_debug(&memx->pmu->subdev, "   MEM TRAIN\n");
0162     memx_cmd(memx, MEMX_TRAIN, 0, NULL);
0163 }
0164
0165 int
0166 nvkm_memx_train_result(struct nvkm_pmu *pmu, u32 *res, int rsize)
0167 {
0168     struct nvkm_device *device = pmu->subdev.device;
0169     u32 reply[2], base, size, i;
0170     int ret;
0171
0172     ret = nvkm_pmu_send(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
0173                 MEMX_INFO_TRAIN, 0);
0174     if (ret)
0175         return ret;
0176
0177     base = reply[0];
0178     size = reply[1] >> 2;
0179     if (size > rsize)
0180         return -ENOMEM;
0181
0182     /* read the packet */
0183     nvkm_wr32(device, 0x10a1c0, 0x02000000 | base);
0184
0185     for (i = 0; i < size; i++)
0186         res[i] = nvkm_rd32(device, 0x10a1c4);
0187
0188     return 0;
0189 }
0190
0191 void
0192 nvkm_memx_block(struct nvkm_memx *memx)
0193 {
0194     nvkm_debug(&memx->pmu->subdev, "   HOST BLOCKED\n");
0195     memx_cmd(memx, MEMX_ENTER, 0, NULL);
0196 }
0197
0198 void
0199 nvkm_memx_unblock(struct nvkm_memx *memx)
0200 {
0201     nvkm_debug(&memx->pmu->subdev, "   HOST UNBLOCKED\n");
0202     memx_cmd(memx, MEMX_LEAVE, 0, NULL);
0203 }
0204 #endif