subdev/pmu/gp10b.c

0001 /*
0002  * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0018  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0019  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0020  * DEALINGS IN THE SOFTWARE.
0021  */
0022 #include "priv.h"
0023
0024 #include <subdev/acr.h>
0025
0026 #include <nvfw/flcn.h>
0027 #include <nvfw/pmu.h>
0028
0029 static int
0030 gp10b_pmu_acr_bootstrap_multiple_falcons_cb(void *priv,
0031                         struct nvfw_falcon_msg *hdr)
0032 {
0033     struct nv_pmu_acr_bootstrap_multiple_falcons_msg *msg =
0034         container_of(hdr, typeof(*msg), msg.hdr);
0035     return msg->falcon_mask;
0036 }
0037 static int
0038 gp10b_pmu_acr_bootstrap_multiple_falcons(struct nvkm_falcon *falcon, u32 mask)
0039 {
0040     struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon);
0041     struct nv_pmu_acr_bootstrap_multiple_falcons_cmd cmd = {
0042         .cmd.hdr.unit_id = NV_PMU_UNIT_ACR,
0043         .cmd.hdr.size = sizeof(cmd),
0044         .cmd.cmd_type = NV_PMU_ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS,
0045         .flags = NV_PMU_ACR_BOOTSTRAP_MULTIPLE_FALCONS_FLAGS_RESET_YES,
0046         .falcon_mask = mask,
0047         .wpr_lo = 0, /*XXX*/
0048         .wpr_hi = 0, /*XXX*/
0049     };
0050     int ret;
0051
0052     ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr,
0053                     gp10b_pmu_acr_bootstrap_multiple_falcons_cb,
0054                     &pmu->subdev, msecs_to_jiffies(1000));
0055     if (ret >= 0) {
0056         if (ret != cmd.falcon_mask)
0057             ret = -EIO;
0058         else
0059             ret = 0;
0060     }
0061
0062     return ret;
0063 }
0064
0065 static const struct nvkm_acr_lsf_func
0066 gp10b_pmu_acr = {
0067     .flags = NVKM_ACR_LSF_DMACTL_REQ_CTX,
0068     .bld_size = sizeof(struct loader_config),
0069     .bld_write = gm20b_pmu_acr_bld_write,
0070     .bld_patch = gm20b_pmu_acr_bld_patch,
0071     .boot = gm20b_pmu_acr_boot,
0072     .bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_PMU) |
0073                  BIT_ULL(NVKM_ACR_LSF_FECS) |
0074                  BIT_ULL(NVKM_ACR_LSF_GPCCS),
0075     .bootstrap_falcon = gm20b_pmu_acr_bootstrap_falcon,
0076     .bootstrap_multiple_falcons = gp10b_pmu_acr_bootstrap_multiple_falcons,
0077 };
0078
0079 static const struct nvkm_pmu_func
0080 gp10b_pmu = {
0081     .flcn = &gm200_pmu_flcn,
0082     .enabled = gf100_pmu_enabled,
0083     .intr = gt215_pmu_intr,
0084     .recv = gm20b_pmu_recv,
0085     .initmsg = gm20b_pmu_initmsg,
0086     .reset = gp102_pmu_reset,
0087 };
0088
0089 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
0090 MODULE_FIRMWARE("nvidia/gp10b/pmu/desc.bin");
0091 MODULE_FIRMWARE("nvidia/gp10b/pmu/image.bin");
0092 MODULE_FIRMWARE("nvidia/gp10b/pmu/sig.bin");
0093 #endif
0094
0095 static const struct nvkm_pmu_fwif
0096 gp10b_pmu_fwif[] = {
0097     {  0, gm20b_pmu_load, &gp10b_pmu, &gp10b_pmu_acr },
0098     { -1, gm200_pmu_nofw, &gp10b_pmu },
0099     {}
0100 };
0101
0102 int
0103 gp10b_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
0104           struct nvkm_pmu **ppmu)
0105 {
0106     return nvkm_pmu_new_(gp10b_pmu_fwif, device, type, inst, ppmu);
0107 }