subdev/pmu/gm20b.c

0001 /*
0002  * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0018  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0019  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0020  * DEALINGS IN THE SOFTWARE.
0021  */
0022 #include "priv.h"
0023
0024 #include <core/memory.h>
0025 #include <subdev/acr.h>
0026
0027 #include <nvfw/flcn.h>
0028 #include <nvfw/pmu.h>
0029
0030 static int
0031 gm20b_pmu_acr_bootstrap_falcon_cb(void *priv, struct nvfw_falcon_msg *hdr)
0032 {
0033     struct nv_pmu_acr_bootstrap_falcon_msg *msg =
0034         container_of(hdr, typeof(*msg), msg.hdr);
0035     return msg->falcon_id;
0036 }
0037
0038 int
0039 gm20b_pmu_acr_bootstrap_falcon(struct nvkm_falcon *falcon,
0040                    enum nvkm_acr_lsf_id id)
0041 {
0042     struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon);
0043     struct nv_pmu_acr_bootstrap_falcon_cmd cmd = {
0044         .cmd.hdr.unit_id = NV_PMU_UNIT_ACR,
0045         .cmd.hdr.size = sizeof(cmd),
0046         .cmd.cmd_type = NV_PMU_ACR_CMD_BOOTSTRAP_FALCON,
0047         .flags = NV_PMU_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES,
0048         .falcon_id = id,
0049     };
0050     int ret;
0051
0052     ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr,
0053                     gm20b_pmu_acr_bootstrap_falcon_cb,
0054                     &pmu->subdev, msecs_to_jiffies(1000));
0055     if (ret >= 0) {
0056         if (ret != cmd.falcon_id)
0057             ret = -EIO;
0058         else
0059             ret = 0;
0060     }
0061
0062     return ret;
0063 }
0064
0065 int
0066 gm20b_pmu_acr_boot(struct nvkm_falcon *falcon)
0067 {
0068     struct nv_pmu_args args = { .secure_mode = true };
0069     const u32 addr_args = falcon->data.limit - sizeof(struct nv_pmu_args);
0070     nvkm_falcon_load_dmem(falcon, &args, addr_args, sizeof(args), 0);
0071     nvkm_falcon_start(falcon);
0072     return 0;
0073 }
0074
0075 void
0076 gm20b_pmu_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
0077 {
0078     struct loader_config hdr;
0079     u64 addr;
0080
0081     nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
0082     addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8);
0083     hdr.code_dma_base  = lower_32_bits((addr + adjust) >> 8);
0084     hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8);
0085     addr = ((u64)hdr.data_dma_base1 << 40 | hdr.data_dma_base << 8);
0086     hdr.data_dma_base  = lower_32_bits((addr + adjust) >> 8);
0087     hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8);
0088     addr = ((u64)hdr.overlay_dma_base1 << 40 | hdr.overlay_dma_base << 8);
0089     hdr.overlay_dma_base  = lower_32_bits((addr + adjust) << 8);
0090     hdr.overlay_dma_base1 = upper_32_bits((addr + adjust) << 8);
0091     nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
0092
0093     loader_config_dump(&acr->subdev, &hdr);
0094 }
0095
0096 void
0097 gm20b_pmu_acr_bld_write(struct nvkm_acr *acr, u32 bld,
0098             struct nvkm_acr_lsfw *lsfw)
0099 {
0100     const u64 base = lsfw->offset.img + lsfw->app_start_offset;
0101     const u64 code = (base + lsfw->app_resident_code_offset) >> 8;
0102     const u64 data = (base + lsfw->app_resident_data_offset) >> 8;
0103     const struct loader_config hdr = {
0104         .dma_idx = FALCON_DMAIDX_UCODE,
0105         .code_dma_base = lower_32_bits(code),
0106         .code_size_total = lsfw->app_size,
0107         .code_size_to_load = lsfw->app_resident_code_size,
0108         .code_entry_point = lsfw->app_imem_entry,
0109         .data_dma_base = lower_32_bits(data),
0110         .data_size = lsfw->app_resident_data_size,
0111         .overlay_dma_base = lower_32_bits(code),
0112         .argc = 1,
0113         .argv = lsfw->falcon->data.limit - sizeof(struct nv_pmu_args),
0114         .code_dma_base1 = upper_32_bits(code),
0115         .data_dma_base1 = upper_32_bits(data),
0116         .overlay_dma_base1 = upper_32_bits(code),
0117     };
0118
0119     nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
0120 }
0121
0122 static const struct nvkm_acr_lsf_func
0123 gm20b_pmu_acr = {
0124     .flags = NVKM_ACR_LSF_DMACTL_REQ_CTX,
0125     .bld_size = sizeof(struct loader_config),
0126     .bld_write = gm20b_pmu_acr_bld_write,
0127     .bld_patch = gm20b_pmu_acr_bld_patch,
0128     .boot = gm20b_pmu_acr_boot,
0129     .bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_PMU) |
0130                  BIT_ULL(NVKM_ACR_LSF_FECS) |
0131                  BIT_ULL(NVKM_ACR_LSF_GPCCS),
0132     .bootstrap_falcon = gm20b_pmu_acr_bootstrap_falcon,
0133 };
0134
0135 static int
0136 gm20b_pmu_acr_init_wpr_callback(void *priv, struct nvfw_falcon_msg *hdr)
0137 {
0138     struct nv_pmu_acr_init_wpr_region_msg *msg =
0139         container_of(hdr, typeof(*msg), msg.hdr);
0140     struct nvkm_pmu *pmu = priv;
0141     struct nvkm_subdev *subdev = &pmu->subdev;
0142
0143     if (msg->error_code) {
0144         nvkm_error(subdev, "ACR WPR init failure: %d\n",
0145                msg->error_code);
0146         return -EINVAL;
0147     }
0148
0149     nvkm_debug(subdev, "ACR WPR init complete\n");
0150     complete_all(&pmu->wpr_ready);
0151     return 0;
0152 }
0153
0154 static int
0155 gm20b_pmu_acr_init_wpr(struct nvkm_pmu *pmu)
0156 {
0157     struct nv_pmu_acr_init_wpr_region_cmd cmd = {
0158         .cmd.hdr.unit_id = NV_PMU_UNIT_ACR,
0159         .cmd.hdr.size = sizeof(cmd),
0160         .cmd.cmd_type = NV_PMU_ACR_CMD_INIT_WPR_REGION,
0161         .region_id = 1,
0162         .wpr_offset = 0,
0163     };
0164
0165     return nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr,
0166                      gm20b_pmu_acr_init_wpr_callback, pmu, 0);
0167 }
0168
0169 int
0170 gm20b_pmu_initmsg(struct nvkm_pmu *pmu)
0171 {
0172     struct nv_pmu_init_msg msg;
0173     int ret;
0174
0175     ret = nvkm_falcon_msgq_recv_initmsg(pmu->msgq, &msg, sizeof(msg));
0176     if (ret)
0177         return ret;
0178
0179     if (msg.hdr.unit_id != NV_PMU_UNIT_INIT ||
0180         msg.msg_type != NV_PMU_INIT_MSG_INIT)
0181         return -EINVAL;
0182
0183     nvkm_falcon_cmdq_init(pmu->hpq, msg.queue_info[0].index,
0184                     msg.queue_info[0].offset,
0185                     msg.queue_info[0].size);
0186     nvkm_falcon_cmdq_init(pmu->lpq, msg.queue_info[1].index,
0187                     msg.queue_info[1].offset,
0188                     msg.queue_info[1].size);
0189     nvkm_falcon_msgq_init(pmu->msgq, msg.queue_info[4].index,
0190                      msg.queue_info[4].offset,
0191                      msg.queue_info[4].size);
0192     return gm20b_pmu_acr_init_wpr(pmu);
0193 }
0194
0195 void
0196 gm20b_pmu_recv(struct nvkm_pmu *pmu)
0197 {
0198     if (!pmu->initmsg_received) {
0199         int ret = pmu->func->initmsg(pmu);
0200         if (ret) {
0201             nvkm_error(&pmu->subdev,
0202                    "error parsing init message: %d\n", ret);
0203             return;
0204         }
0205
0206         pmu->initmsg_received = true;
0207     }
0208
0209     nvkm_falcon_msgq_recv(pmu->msgq);
0210 }
0211
0212 static const struct nvkm_pmu_func
0213 gm20b_pmu = {
0214     .flcn = &gm200_pmu_flcn,
0215     .enabled = gf100_pmu_enabled,
0216     .intr = gt215_pmu_intr,
0217     .recv = gm20b_pmu_recv,
0218     .initmsg = gm20b_pmu_initmsg,
0219     .reset = gf100_pmu_reset,
0220 };
0221
0222 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
0223 MODULE_FIRMWARE("nvidia/gm20b/pmu/desc.bin");
0224 MODULE_FIRMWARE("nvidia/gm20b/pmu/image.bin");
0225 MODULE_FIRMWARE("nvidia/gm20b/pmu/sig.bin");
0226 #endif
0227
0228 int
0229 gm20b_pmu_load(struct nvkm_pmu *pmu, int ver, const struct nvkm_pmu_fwif *fwif)
0230 {
0231     return nvkm_acr_lsfw_load_sig_image_desc(&pmu->subdev, &pmu->falcon,
0232                          NVKM_ACR_LSF_PMU, "pmu/",
0233                          ver, fwif->acr);
0234 }
0235
0236 static const struct nvkm_pmu_fwif
0237 gm20b_pmu_fwif[] = {
0238     {  0, gm20b_pmu_load, &gm20b_pmu, &gm20b_pmu_acr },
0239     { -1, gm200_pmu_nofw, &gm20b_pmu },
0240     {}
0241 };
0242
0243 int
0244 gm20b_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
0245           struct nvkm_pmu **ppmu)
0246 {
0247     return nvkm_pmu_new_(gm20b_pmu_fwif, device, type, inst, ppmu);
0248 }