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0024 #include "priv.h"
0025
0026 static int
0027 gm200_pmu_flcn_reset(struct nvkm_falcon *falcon)
0028 {
0029 struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon);
0030
0031 nvkm_falcon_wr32(falcon, 0x014, 0x0000ffff);
0032 pmu->func->reset(pmu);
0033 return nvkm_falcon_enable(falcon);
0034 }
0035
0036 const struct nvkm_falcon_func
0037 gm200_pmu_flcn = {
0038 .debug = 0xc08,
0039 .fbif = 0xe00,
0040 .load_imem = nvkm_falcon_v1_load_imem,
0041 .load_dmem = nvkm_falcon_v1_load_dmem,
0042 .read_dmem = nvkm_falcon_v1_read_dmem,
0043 .bind_context = nvkm_falcon_v1_bind_context,
0044 .wait_for_halt = nvkm_falcon_v1_wait_for_halt,
0045 .clear_interrupt = nvkm_falcon_v1_clear_interrupt,
0046 .set_start_addr = nvkm_falcon_v1_set_start_addr,
0047 .start = nvkm_falcon_v1_start,
0048 .enable = nvkm_falcon_v1_enable,
0049 .disable = nvkm_falcon_v1_disable,
0050 .reset = gm200_pmu_flcn_reset,
0051 .cmdq = { 0x4a0, 0x4b0, 4 },
0052 .msgq = { 0x4c8, 0x4cc, 0 },
0053 };
0054
0055 static const struct nvkm_pmu_func
0056 gm200_pmu = {
0057 .flcn = &gm200_pmu_flcn,
0058 .enabled = gf100_pmu_enabled,
0059 .reset = gf100_pmu_reset,
0060 };
0061
0062
0063 int
0064 gm200_pmu_nofw(struct nvkm_pmu *pmu, int ver, const struct nvkm_pmu_fwif *fwif)
0065 {
0066 nvkm_warn(&pmu->subdev, "firmware unavailable\n");
0067 return 0;
0068 }
0069
0070 static const struct nvkm_pmu_fwif
0071 gm200_pmu_fwif[] = {
0072 { -1, gm200_pmu_nofw, &gm200_pmu },
0073 {}
0074 };
0075
0076 int
0077 gm200_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
0078 struct nvkm_pmu **ppmu)
0079 {
0080 return nvkm_pmu_new_(gm200_pmu_fwif, device, type, inst, ppmu);
0081 }