0001 /*
0002 * Copyright 2013 Red Hat Inc.
0003 *
0004 * Permission is hereby granted, free of charge, to any person obtaining a
0005 * copy of this software and associated documentation files (the "Software"),
0006 * to deal in the Software without restriction, including without limitation
0007 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008 * and/or sell copies of the Software, and to permit persons to whom the
0009 * Software is furnished to do so, subject to the following conditions:
0010 *
0011 * The above copyright notice and this permission notice shall be included in
0012 * all copies or substantial portions of the Software.
0013 *
0014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
0017 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020 * OTHER DEALINGS IN THE SOFTWARE.
0021 *
0022 * Authors: Ben Skeggs
0023 */
0024
0025 #define GT215 0xa3
0026 #define GF100 0xc0
0027 #define GF119 0xd9
0028 #define GK208 0x108
0029
0030 #include "os.h"
0031
0032 // IO addresses
0033 #define NV_PPWR_INTR_TRIGGER 0x0000
0034 #define NV_PPWR_INTR_TRIGGER_USER1 0x00000080
0035 #define NV_PPWR_INTR_TRIGGER_USER0 0x00000040
0036 #define NV_PPWR_INTR_ACK 0x0004
0037 #define NV_PPWR_INTR_ACK_SUBINTR 0x00000800
0038 #define NV_PPWR_INTR_ACK_WATCHDOG 0x00000002
0039 #define NV_PPWR_INTR 0x0008
0040 #define NV_PPWR_INTR_SUBINTR 0x00000800
0041 #define NV_PPWR_INTR_USER1 0x00000080
0042 #define NV_PPWR_INTR_USER0 0x00000040
0043 #define NV_PPWR_INTR_PAUSE 0x00000020
0044 #define NV_PPWR_INTR_WATCHDOG 0x00000002
0045 #define NV_PPWR_INTR_EN_SET 0x0010
0046 #define NV_PPWR_INTR_EN_SET_SUBINTR 0x00000800
0047 #define NV_PPWR_INTR_EN_SET_WATCHDOG 0x00000002
0048 #define NV_PPWR_INTR_EN_CLR 0x0014
0049 #define NV_PPWR_INTR_EN_CLR_MASK /* fuck i hate envyas */ -1
0050 #define NV_PPWR_INTR_ROUTE 0x001c
0051 #define NV_PPWR_TIMER_LOW 0x002c
0052 #define NV_PPWR_WATCHDOG_TIME 0x0034
0053 #define NV_PPWR_WATCHDOG_ENABLE 0x0038
0054 #define NV_PPWR_CAPS 0x0108
0055 #define NV_PPWR_UAS_CONFIG 0x0164
0056 #define NV_PPWR_UAS_CONFIG_ENABLE 0x00010000
0057 #if NVKM_PPWR_CHIPSET >= GK208
0058 #define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x0450)
0059 #endif
0060 #define NV_PPWR_FIFO_PUT(i) (4 * (i) + 0x04a0)
0061 #define NV_PPWR_FIFO_GET(i) (4 * (i) + 0x04b0)
0062 #define NV_PPWR_FIFO_INTR 0x04c0
0063 #define NV_PPWR_FIFO_INTR_EN 0x04c4
0064 #define NV_PPWR_RFIFO_PUT 0x04c8
0065 #define NV_PPWR_RFIFO_GET 0x04cc
0066 #define NV_PPWR_H2D 0x04d0
0067 #define NV_PPWR_D2H 0x04dc
0068 #if NVKM_PPWR_CHIPSET < GK208
0069 #define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x05d0)
0070 #endif
0071 #define NV_PPWR_SUBINTR 0x0688
0072 #define NV_PPWR_SUBINTR_FIFO 0x00000002
0073 #define NV_PPWR_MMIO_ADDR 0x07a0
0074 #define NV_PPWR_MMIO_DATA 0x07a4
0075 #define NV_PPWR_MMIO_CTRL 0x07ac
0076 #define NV_PPWR_MMIO_CTRL_TRIGGER 0x00010000
0077 #define NV_PPWR_MMIO_CTRL_STATUS 0x00007000
0078 #define NV_PPWR_MMIO_CTRL_STATUS_IDLE 0x00000000
0079 #define NV_PPWR_MMIO_CTRL_MASK 0x000000f0
0080 #define NV_PPWR_MMIO_CTRL_MASK_B32_0 0x000000f0
0081 #define NV_PPWR_MMIO_CTRL_OP 0x00000003
0082 #define NV_PPWR_MMIO_CTRL_OP_RD 0x00000001
0083 #define NV_PPWR_MMIO_CTRL_OP_WR 0x00000002
0084 #define NV_PPWR_OUTPUT 0x07c0
0085 #define NV_PPWR_OUTPUT_FB_PAUSE 0x00000004
0086 #if NVKM_PPWR_CHIPSET < GF119
0087 #define NV_PPWR_OUTPUT_I2C_3_SCL 0x00000100
0088 #define NV_PPWR_OUTPUT_I2C_3_SDA 0x00000200
0089 #define NV_PPWR_OUTPUT_I2C_0_SCL 0x00001000
0090 #define NV_PPWR_OUTPUT_I2C_0_SDA 0x00002000
0091 #define NV_PPWR_OUTPUT_I2C_1_SCL 0x00004000
0092 #define NV_PPWR_OUTPUT_I2C_1_SDA 0x00008000
0093 #define NV_PPWR_OUTPUT_I2C_2_SCL 0x00010000
0094 #define NV_PPWR_OUTPUT_I2C_2_SDA 0x00020000
0095 #define NV_PPWR_OUTPUT_I2C_4_SCL 0x00040000
0096 #define NV_PPWR_OUTPUT_I2C_4_SDA 0x00080000
0097 #define NV_PPWR_OUTPUT_I2C_5_SCL 0x00100000
0098 #define NV_PPWR_OUTPUT_I2C_5_SDA 0x00200000
0099 #define NV_PPWR_OUTPUT_I2C_6_SCL 0x00400000
0100 #define NV_PPWR_OUTPUT_I2C_6_SDA 0x00800000
0101 #define NV_PPWR_OUTPUT_I2C_7_SCL 0x01000000
0102 #define NV_PPWR_OUTPUT_I2C_7_SDA 0x02000000
0103 #define NV_PPWR_OUTPUT_I2C_8_SCL 0x04000000
0104 #define NV_PPWR_OUTPUT_I2C_8_SDA 0x08000000
0105 #define NV_PPWR_OUTPUT_I2C_9_SCL 0x10000000
0106 #define NV_PPWR_OUTPUT_I2C_9_SDA 0x20000000
0107 #else
0108 #define NV_PPWR_OUTPUT_I2C_0_SCL 0x00000400
0109 #define NV_PPWR_OUTPUT_I2C_1_SCL 0x00000800
0110 #define NV_PPWR_OUTPUT_I2C_2_SCL 0x00001000
0111 #define NV_PPWR_OUTPUT_I2C_3_SCL 0x00002000
0112 #define NV_PPWR_OUTPUT_I2C_4_SCL 0x00004000
0113 #define NV_PPWR_OUTPUT_I2C_5_SCL 0x00008000
0114 #define NV_PPWR_OUTPUT_I2C_6_SCL 0x00010000
0115 #define NV_PPWR_OUTPUT_I2C_7_SCL 0x00020000
0116 #define NV_PPWR_OUTPUT_I2C_8_SCL 0x00040000
0117 #define NV_PPWR_OUTPUT_I2C_9_SCL 0x00080000
0118 #define NV_PPWR_OUTPUT_I2C_0_SDA 0x00100000
0119 #define NV_PPWR_OUTPUT_I2C_1_SDA 0x00200000
0120 #define NV_PPWR_OUTPUT_I2C_2_SDA 0x00400000
0121 #define NV_PPWR_OUTPUT_I2C_3_SDA 0x00800000
0122 #define NV_PPWR_OUTPUT_I2C_4_SDA 0x01000000
0123 #define NV_PPWR_OUTPUT_I2C_5_SDA 0x02000000
0124 #define NV_PPWR_OUTPUT_I2C_6_SDA 0x04000000
0125 #define NV_PPWR_OUTPUT_I2C_7_SDA 0x08000000
0126 #define NV_PPWR_OUTPUT_I2C_8_SDA 0x10000000
0127 #define NV_PPWR_OUTPUT_I2C_9_SDA 0x20000000
0128 #endif
0129 #define NV_PPWR_INPUT 0x07c4
0130 #define NV_PPWR_OUTPUT_SET 0x07e0
0131 #define NV_PPWR_OUTPUT_SET_FB_PAUSE 0x00000004
0132 #define NV_PPWR_OUTPUT_CLR 0x07e4
0133 #define NV_PPWR_OUTPUT_CLR_FB_PAUSE 0x00000004
0134
0135 // Inter-process message format
0136 .equ #msg_process 0x00 /* send() target, recv() sender */
0137 .equ #msg_message 0x04
0138 .equ #msg_data0 0x08
0139 .equ #msg_data1 0x0c
0140
0141 // Kernel message IDs
0142 #define KMSG_FIFO 0x00000000
0143 #define KMSG_ALARM 0x00000001
0144
0145 // Process message queue description
0146 .equ #proc_qlen 4 // log2(size of queue entry in bytes)
0147 .equ #proc_qnum 2 // log2(max number of entries in queue)
0148 .equ #proc_qmaskb (1 << #proc_qnum) // max number of entries in queue
0149 .equ #proc_qmaskp (#proc_qmaskb - 1)
0150 .equ #proc_qmaskf ((#proc_qmaskb << 1) - 1)
0151 .equ #proc_qsize (1 << (#proc_qlen + #proc_qnum))
0152
0153 // Process table entry
0154 .equ #proc_id 0x00
0155 .equ #proc_init 0x04
0156 .equ #proc_recv 0x08
0157 .equ #proc_time 0x0c
0158 .equ #proc_qput 0x10
0159 .equ #proc_qget 0x14
0160 .equ #proc_queue 0x18
0161 .equ #proc_size (0x18 + #proc_qsize)
0162
0163 #define process(id,init,recv) /*
0164 */ .b32 id /*
0165 */ .b32 init /*
0166 */ .b32 recv /*
0167 */ .b32 0 /*
0168 */ .b32 0 /*
0169 */ .b32 0 /*
0170 */ .skip 64
0171
0172 #if NVKM_PPWR_CHIPSET < GK208
0173 #define imm32(reg,val) /*
0174 */ movw reg ((val) & 0x0000ffff) /*
0175 */ sethi reg ((val) & 0xffff0000)
0176 #else
0177 #define imm32(reg,val) /*
0178 */ mov reg (val)
0179 #endif
0180
0181 #ifndef NVKM_FALCON_UNSHIFTED_IO
0182 #define nv_iord(reg,ior) /*
0183 */ mov reg ior /*
0184 */ shl b32 reg 6 /*
0185 */ iord reg I[reg + 0x000]
0186 #else
0187 #define nv_iord(reg,ior) /*
0188 */ mov reg ior /*
0189 */ iord reg I[reg + 0x000]
0190 #endif
0191
0192 #ifndef NVKM_FALCON_UNSHIFTED_IO
0193 #define nv_iowr(ior,reg) /*
0194 */ mov $r0 ior /*
0195 */ shl b32 $r0 6 /*
0196 */ iowr I[$r0 + 0x000] reg /*
0197 */ clear b32 $r0
0198 #else
0199 #define nv_iowr(ior,reg) /*
0200 */ mov $r0 ior /*
0201 */ iowr I[$r0 + 0x000] reg /*
0202 */ clear b32 $r0
0203 #endif
0204
0205 #ifndef NVKM_FALCON_UNSHIFTED_IO
0206 #define nv_iowrs(ior,reg) /*
0207 */ mov $r0 ior /*
0208 */ shl b32 $r0 6 /*
0209 */ iowrs I[$r0 + 0x000] reg /*
0210 */ clear b32 $r0
0211 #else
0212 #define nv_iowrs(ior,reg) /*
0213 */ mov $r0 ior /*
0214 */ iowrs I[$r0 + 0x000] reg /*
0215 */ clear b32 $r0
0216 #endif
0217
0218 #define hash #
0219 #define fn(a) a
0220 #ifndef NVKM_FALCON_PC24
0221 #define call(a) call fn(hash)a
0222 #else
0223 #define call(a) lcall fn(hash)a
0224 #endif
0225
0226 #ifndef NVKM_FALCON_MMIO_UAS
0227 #define nv_rd32(reg,addr) /*
0228 */ mov b32 $r14 addr /*
0229 */ call(rd32) /*
0230 */ mov b32 reg $r13
0231 #else
0232 #define nv_rd32(reg,addr) /*
0233 */ sethi $r0 0x14000000 /*
0234 */ or $r0 addr /*
0235 */ ld b32 reg D[$r0] /*
0236 */ clear b32 $r0
0237 #endif
0238
0239 #if !defined(NVKM_FALCON_MMIO_UAS) || defined(NVKM_FALCON_MMIO_TRAP)
0240 #define nv_wr32(addr,reg) /*
0241 */ push addr /*
0242 */ push reg /*
0243 */ pop $r13 /*
0244 */ pop $r14 /*
0245 */ call(wr32)
0246 #else
0247 #define nv_wr32(addr,reg) /*
0248 */ sethi $r0 0x14000000 /*
0249 */ or $r0 addr /*
0250 */ st b32 D[$r0] reg /*
0251 */ clear b32 $r0
0252 #endif
0253
0254 #define st(size, addr, reg) /*
0255 */ imm32($r0, addr) /*
0256 */ st size D[$r0] reg /*
0257 */ clear b32 $r0
0258
0259 #define ld(size, reg, addr) /*
0260 */ imm32($r0, addr) /*
0261 */ ld size reg D[$r0] /*
0262 */ clear b32 $r0
0263
0264 // does a 64+64 -> 64 unsigned addition (C = A + B)
0265 #define addu64(reg_a_c_hi, reg_a_c_lo, b_hi, b_lo) /*
0266 */ add b32 reg_a_c_lo b_lo /*
0267 */ adc b32 reg_a_c_hi b_hi
0268
0269 // does a 64+64 -> 64 substraction (C = A - B)
0270 #define subu64(reg_a_c_hi, reg_a_c_lo, b_hi, b_lo) /*
0271 */ sub b32 reg_a_c_lo b_lo /*
0272 */ sbb b32 reg_a_c_hi b_hi
