subdev/pci/g84.c

0001 /*
0002  * Copyright 2015 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Ben Skeggs <bskeggs@redhat.com>
0023  */
0024 #include "priv.h"
0025
0026 #include <core/pci.h>
0027
0028 static int
0029 g84_pcie_version_supported(struct nvkm_pci *pci)
0030 {
0031     /* g84 and g86 report wrong information about what they support */
0032     return 1;
0033 }
0034
0035 int
0036 g84_pcie_version(struct nvkm_pci *pci)
0037 {
0038     struct nvkm_device *device = pci->subdev.device;
0039     return (nvkm_rd32(device, 0x00154c) & 0x1) + 1;
0040 }
0041
0042 void
0043 g84_pcie_set_version(struct nvkm_pci *pci, u8 ver)
0044 {
0045     struct nvkm_device *device = pci->subdev.device;
0046     nvkm_mask(device, 0x00154c, 0x1, (ver >= 2 ? 0x1 : 0x0));
0047 }
0048
0049 static void
0050 g84_pcie_set_cap_speed(struct nvkm_pci *pci, bool full_speed)
0051 {
0052     struct nvkm_device *device = pci->subdev.device;
0053     nvkm_mask(device, 0x00154c, 0x80, full_speed ? 0x80 : 0x0);
0054 }
0055
0056 enum nvkm_pcie_speed
0057 g84_pcie_cur_speed(struct nvkm_pci *pci)
0058 {
0059     u32 reg_v = nvkm_pci_rd32(pci, 0x88) & 0x30000;
0060     switch (reg_v) {
0061     case 0x30000:
0062         return NVKM_PCIE_SPEED_8_0;
0063     case 0x20000:
0064         return NVKM_PCIE_SPEED_5_0;
0065     case 0x10000:
0066     default:
0067         return NVKM_PCIE_SPEED_2_5;
0068     }
0069 }
0070
0071 enum nvkm_pcie_speed
0072 g84_pcie_max_speed(struct nvkm_pci *pci)
0073 {
0074     u32 reg_v = nvkm_pci_rd32(pci, 0x460) & 0x3300;
0075     if (reg_v == 0x2200)
0076         return NVKM_PCIE_SPEED_5_0;
0077     return NVKM_PCIE_SPEED_2_5;
0078 }
0079
0080 void
0081 g84_pcie_set_link_speed(struct nvkm_pci *pci, enum nvkm_pcie_speed speed)
0082 {
0083     u32 mask_value;
0084
0085     if (speed == NVKM_PCIE_SPEED_5_0)
0086         mask_value = 0x20;
0087     else
0088         mask_value = 0x10;
0089
0090     nvkm_pci_mask(pci, 0x460, 0x30, mask_value);
0091     nvkm_pci_mask(pci, 0x460, 0x1, 0x1);
0092 }
0093
0094 int
0095 g84_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed speed, u8 width)
0096 {
0097     g84_pcie_set_cap_speed(pci, speed == NVKM_PCIE_SPEED_5_0);
0098     g84_pcie_set_link_speed(pci, speed);
0099     return 0;
0100 }
0101
0102 void
0103 g84_pci_init(struct nvkm_pci *pci)
0104 {
0105     /* The following only concerns PCIe cards. */
0106     if (!pci_is_pcie(pci->pdev))
0107         return;
0108
0109     /* Tag field is 8-bit long, regardless of EXT_TAG.
0110      * However, if EXT_TAG is disabled, only the lower 5 bits of the tag
0111      * field should be used, limiting the number of request to 32.
0112      *
0113      * Apparently, 0x041c stores some limit on the number of requests
0114      * possible, so if EXT_TAG is disabled, limit that requests number to
0115      * 32
0116      *
0117      * Fixes fdo#86537
0118      */
0119     if (nvkm_pci_rd32(pci, 0x007c) & 0x00000020)
0120         nvkm_pci_mask(pci, 0x0080, 0x00000100, 0x00000100);
0121     else
0122         nvkm_pci_mask(pci, 0x041c, 0x00000060, 0x00000000);
0123 }
0124
0125 int
0126 g84_pcie_init(struct nvkm_pci *pci)
0127 {
0128     bool full_speed = g84_pcie_cur_speed(pci) == NVKM_PCIE_SPEED_5_0;
0129     g84_pcie_set_cap_speed(pci, full_speed);
0130     return 0;
0131 }
0132
0133 static const struct nvkm_pci_func
0134 g84_pci_func = {
0135     .init = g84_pci_init,
0136     .rd32 = nv40_pci_rd32,
0137     .wr08 = nv40_pci_wr08,
0138     .wr32 = nv40_pci_wr32,
0139     .msi_rearm = nv46_pci_msi_rearm,
0140
0141     .pcie.init = g84_pcie_init,
0142     .pcie.set_link = g84_pcie_set_link,
0143
0144     .pcie.max_speed = g84_pcie_max_speed,
0145     .pcie.cur_speed = g84_pcie_cur_speed,
0146
0147     .pcie.set_version = g84_pcie_set_version,
0148     .pcie.version = g84_pcie_version,
0149     .pcie.version_supported = g84_pcie_version_supported,
0150 };
0151
0152 int
0153 g84_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
0154         struct nvkm_pci **ppci)
0155 {
0156     return nvkm_pci_new_(&g84_pci_func, device, type, inst, ppci);
0157 }