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0001 /*
0002  * Copyright 2017 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022 #include "vmm.h"
0023 
0024 #include <core/client.h>
0025 #include <subdev/fb.h>
0026 #include <subdev/ltc.h>
0027 #include <subdev/timer.h>
0028 #include <engine/gr.h>
0029 
0030 #include <nvif/ifc00d.h>
0031 #include <nvif/unpack.h>
0032 
0033 static void
0034 gp100_vmm_pfn_unmap(struct nvkm_vmm *vmm,
0035             struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
0036 {
0037     struct device *dev = vmm->mmu->subdev.device->dev;
0038     dma_addr_t addr;
0039 
0040     nvkm_kmap(pt->memory);
0041     while (ptes--) {
0042         u32 datalo = nvkm_ro32(pt->memory, pt->base + ptei * 8 + 0);
0043         u32 datahi = nvkm_ro32(pt->memory, pt->base + ptei * 8 + 4);
0044         u64 data   = (u64)datahi << 32 | datalo;
0045         if ((data & (3ULL << 1)) != 0) {
0046             addr = (data >> 8) << 12;
0047             dma_unmap_page(dev, addr, PAGE_SIZE, DMA_BIDIRECTIONAL);
0048         }
0049         ptei++;
0050     }
0051     nvkm_done(pt->memory);
0052 }
0053 
0054 static bool
0055 gp100_vmm_pfn_clear(struct nvkm_vmm *vmm,
0056             struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
0057 {
0058     bool dma = false;
0059     nvkm_kmap(pt->memory);
0060     while (ptes--) {
0061         u32 datalo = nvkm_ro32(pt->memory, pt->base + ptei * 8 + 0);
0062         u32 datahi = nvkm_ro32(pt->memory, pt->base + ptei * 8 + 4);
0063         u64 data   = (u64)datahi << 32 | datalo;
0064         if ((data & BIT_ULL(0)) && (data & (3ULL << 1)) != 0) {
0065             VMM_WO064(pt, vmm, ptei * 8, data & ~BIT_ULL(0));
0066             dma = true;
0067         }
0068         ptei++;
0069     }
0070     nvkm_done(pt->memory);
0071     return dma;
0072 }
0073 
0074 static void
0075 gp100_vmm_pgt_pfn(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
0076           u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
0077 {
0078     struct device *dev = vmm->mmu->subdev.device->dev;
0079     dma_addr_t addr;
0080 
0081     nvkm_kmap(pt->memory);
0082     for (; ptes; ptes--, map->pfn++) {
0083         u64 data = 0;
0084 
0085         if (!(*map->pfn & NVKM_VMM_PFN_V))
0086             continue;
0087 
0088         if (!(*map->pfn & NVKM_VMM_PFN_W))
0089             data |= BIT_ULL(6); /* RO. */
0090 
0091         if (!(*map->pfn & NVKM_VMM_PFN_A))
0092             data |= BIT_ULL(7); /* Atomic disable. */
0093 
0094         if (!(*map->pfn & NVKM_VMM_PFN_VRAM)) {
0095             addr = *map->pfn >> NVKM_VMM_PFN_ADDR_SHIFT;
0096             addr = dma_map_page(dev, pfn_to_page(addr), 0,
0097                         PAGE_SIZE, DMA_BIDIRECTIONAL);
0098             if (!WARN_ON(dma_mapping_error(dev, addr))) {
0099                 data |= addr >> 4;
0100                 data |= 2ULL << 1; /* SYSTEM_COHERENT_MEMORY. */
0101                 data |= BIT_ULL(3); /* VOL. */
0102                 data |= BIT_ULL(0); /* VALID. */
0103             }
0104         } else {
0105             data |= (*map->pfn & NVKM_VMM_PFN_ADDR) >> 4;
0106             data |= BIT_ULL(0); /* VALID. */
0107         }
0108 
0109         VMM_WO064(pt, vmm, ptei++ * 8, data);
0110     }
0111     nvkm_done(pt->memory);
0112 }
0113 
0114 static inline void
0115 gp100_vmm_pgt_pte(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
0116           u32 ptei, u32 ptes, struct nvkm_vmm_map *map, u64 addr)
0117 {
0118     u64 data = (addr >> 4) | map->type;
0119 
0120     map->type += ptes * map->ctag;
0121 
0122     while (ptes--) {
0123         VMM_WO064(pt, vmm, ptei++ * 8, data);
0124         data += map->next;
0125     }
0126 }
0127 
0128 static void
0129 gp100_vmm_pgt_sgl(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
0130           u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
0131 {
0132     VMM_MAP_ITER_SGL(vmm, pt, ptei, ptes, map, gp100_vmm_pgt_pte);
0133 }
0134 
0135 static void
0136 gp100_vmm_pgt_dma(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
0137           u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
0138 {
0139     if (map->page->shift == PAGE_SHIFT) {
0140         VMM_SPAM(vmm, "DMAA %08x %08x PTE(s)", ptei, ptes);
0141         nvkm_kmap(pt->memory);
0142         while (ptes--) {
0143             const u64 data = (*map->dma++ >> 4) | map->type;
0144             VMM_WO064(pt, vmm, ptei++ * 8, data);
0145             map->type += map->ctag;
0146         }
0147         nvkm_done(pt->memory);
0148         return;
0149     }
0150 
0151     VMM_MAP_ITER_DMA(vmm, pt, ptei, ptes, map, gp100_vmm_pgt_pte);
0152 }
0153 
0154 static void
0155 gp100_vmm_pgt_mem(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
0156           u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
0157 {
0158     VMM_MAP_ITER_MEM(vmm, pt, ptei, ptes, map, gp100_vmm_pgt_pte);
0159 }
0160 
0161 static void
0162 gp100_vmm_pgt_sparse(struct nvkm_vmm *vmm,
0163              struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
0164 {
0165     /* VALID_FALSE + VOL tells the MMU to treat the PTE as sparse. */
0166     VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(3) /* VOL. */, ptes);
0167 }
0168 
0169 static const struct nvkm_vmm_desc_func
0170 gp100_vmm_desc_spt = {
0171     .unmap = gf100_vmm_pgt_unmap,
0172     .sparse = gp100_vmm_pgt_sparse,
0173     .mem = gp100_vmm_pgt_mem,
0174     .dma = gp100_vmm_pgt_dma,
0175     .sgl = gp100_vmm_pgt_sgl,
0176     .pfn = gp100_vmm_pgt_pfn,
0177     .pfn_clear = gp100_vmm_pfn_clear,
0178     .pfn_unmap = gp100_vmm_pfn_unmap,
0179 };
0180 
0181 static void
0182 gp100_vmm_lpt_invalid(struct nvkm_vmm *vmm,
0183               struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
0184 {
0185     /* VALID_FALSE + PRIV tells the MMU to ignore corresponding SPTEs. */
0186     VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(5) /* PRIV. */, ptes);
0187 }
0188 
0189 static const struct nvkm_vmm_desc_func
0190 gp100_vmm_desc_lpt = {
0191     .invalid = gp100_vmm_lpt_invalid,
0192     .unmap = gf100_vmm_pgt_unmap,
0193     .sparse = gp100_vmm_pgt_sparse,
0194     .mem = gp100_vmm_pgt_mem,
0195 };
0196 
0197 static inline void
0198 gp100_vmm_pd0_pte(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
0199           u32 ptei, u32 ptes, struct nvkm_vmm_map *map, u64 addr)
0200 {
0201     u64 data = (addr >> 4) | map->type;
0202 
0203     map->type += ptes * map->ctag;
0204 
0205     while (ptes--) {
0206         VMM_WO128(pt, vmm, ptei++ * 0x10, data, 0ULL);
0207         data += map->next;
0208     }
0209 }
0210 
0211 static void
0212 gp100_vmm_pd0_mem(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
0213           u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
0214 {
0215     VMM_MAP_ITER_MEM(vmm, pt, ptei, ptes, map, gp100_vmm_pd0_pte);
0216 }
0217 
0218 static inline bool
0219 gp100_vmm_pde(struct nvkm_mmu_pt *pt, u64 *data)
0220 {
0221     switch (nvkm_memory_target(pt->memory)) {
0222     case NVKM_MEM_TARGET_VRAM: *data |= 1ULL << 1; break;
0223     case NVKM_MEM_TARGET_HOST: *data |= 2ULL << 1;
0224         *data |= BIT_ULL(3); /* VOL. */
0225         break;
0226     case NVKM_MEM_TARGET_NCOH: *data |= 3ULL << 1; break;
0227     default:
0228         WARN_ON(1);
0229         return false;
0230     }
0231     *data |= pt->addr >> 4;
0232     return true;
0233 }
0234 
0235 static void
0236 gp100_vmm_pd0_pde(struct nvkm_vmm *vmm, struct nvkm_vmm_pt *pgd, u32 pdei)
0237 {
0238     struct nvkm_vmm_pt *pgt = pgd->pde[pdei];
0239     struct nvkm_mmu_pt *pd = pgd->pt[0];
0240     u64 data[2] = {};
0241 
0242     if (pgt->pt[0] && !gp100_vmm_pde(pgt->pt[0], &data[0]))
0243         return;
0244     if (pgt->pt[1] && !gp100_vmm_pde(pgt->pt[1], &data[1]))
0245         return;
0246 
0247     nvkm_kmap(pd->memory);
0248     VMM_WO128(pd, vmm, pdei * 0x10, data[0], data[1]);
0249     nvkm_done(pd->memory);
0250 }
0251 
0252 static void
0253 gp100_vmm_pd0_sparse(struct nvkm_vmm *vmm,
0254              struct nvkm_mmu_pt *pt, u32 pdei, u32 pdes)
0255 {
0256     /* VALID_FALSE + VOL_BIG tells the MMU to treat the PDE as sparse. */
0257     VMM_FO128(pt, vmm, pdei * 0x10, BIT_ULL(3) /* VOL_BIG. */, 0ULL, pdes);
0258 }
0259 
0260 static void
0261 gp100_vmm_pd0_unmap(struct nvkm_vmm *vmm,
0262             struct nvkm_mmu_pt *pt, u32 pdei, u32 pdes)
0263 {
0264     VMM_FO128(pt, vmm, pdei * 0x10, 0ULL, 0ULL, pdes);
0265 }
0266 
0267 static void
0268 gp100_vmm_pd0_pfn_unmap(struct nvkm_vmm *vmm,
0269             struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
0270 {
0271     struct device *dev = vmm->mmu->subdev.device->dev;
0272     dma_addr_t addr;
0273 
0274     nvkm_kmap(pt->memory);
0275     while (ptes--) {
0276         u32 datalo = nvkm_ro32(pt->memory, pt->base + ptei * 16 + 0);
0277         u32 datahi = nvkm_ro32(pt->memory, pt->base + ptei * 16 + 4);
0278         u64 data   = (u64)datahi << 32 | datalo;
0279 
0280         if ((data & (3ULL << 1)) != 0) {
0281             addr = (data >> 8) << 12;
0282             dma_unmap_page(dev, addr, 1UL << 21, DMA_BIDIRECTIONAL);
0283         }
0284         ptei++;
0285     }
0286     nvkm_done(pt->memory);
0287 }
0288 
0289 static bool
0290 gp100_vmm_pd0_pfn_clear(struct nvkm_vmm *vmm,
0291             struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
0292 {
0293     bool dma = false;
0294 
0295     nvkm_kmap(pt->memory);
0296     while (ptes--) {
0297         u32 datalo = nvkm_ro32(pt->memory, pt->base + ptei * 16 + 0);
0298         u32 datahi = nvkm_ro32(pt->memory, pt->base + ptei * 16 + 4);
0299         u64 data   = (u64)datahi << 32 | datalo;
0300 
0301         if ((data & BIT_ULL(0)) && (data & (3ULL << 1)) != 0) {
0302             VMM_WO064(pt, vmm, ptei * 16, data & ~BIT_ULL(0));
0303             dma = true;
0304         }
0305         ptei++;
0306     }
0307     nvkm_done(pt->memory);
0308     return dma;
0309 }
0310 
0311 static void
0312 gp100_vmm_pd0_pfn(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
0313           u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
0314 {
0315     struct device *dev = vmm->mmu->subdev.device->dev;
0316     dma_addr_t addr;
0317 
0318     nvkm_kmap(pt->memory);
0319     for (; ptes; ptes--, map->pfn++) {
0320         u64 data = 0;
0321 
0322         if (!(*map->pfn & NVKM_VMM_PFN_V))
0323             continue;
0324 
0325         if (!(*map->pfn & NVKM_VMM_PFN_W))
0326             data |= BIT_ULL(6); /* RO. */
0327 
0328         if (!(*map->pfn & NVKM_VMM_PFN_A))
0329             data |= BIT_ULL(7); /* Atomic disable. */
0330 
0331         if (!(*map->pfn & NVKM_VMM_PFN_VRAM)) {
0332             addr = *map->pfn >> NVKM_VMM_PFN_ADDR_SHIFT;
0333             addr = dma_map_page(dev, pfn_to_page(addr), 0,
0334                         1UL << 21, DMA_BIDIRECTIONAL);
0335             if (!WARN_ON(dma_mapping_error(dev, addr))) {
0336                 data |= addr >> 4;
0337                 data |= 2ULL << 1; /* SYSTEM_COHERENT_MEMORY. */
0338                 data |= BIT_ULL(3); /* VOL. */
0339                 data |= BIT_ULL(0); /* VALID. */
0340             }
0341         } else {
0342             data |= (*map->pfn & NVKM_VMM_PFN_ADDR) >> 4;
0343             data |= BIT_ULL(0); /* VALID. */
0344         }
0345 
0346         VMM_WO064(pt, vmm, ptei++ * 16, data);
0347     }
0348     nvkm_done(pt->memory);
0349 }
0350 
0351 static const struct nvkm_vmm_desc_func
0352 gp100_vmm_desc_pd0 = {
0353     .unmap = gp100_vmm_pd0_unmap,
0354     .sparse = gp100_vmm_pd0_sparse,
0355     .pde = gp100_vmm_pd0_pde,
0356     .mem = gp100_vmm_pd0_mem,
0357     .pfn = gp100_vmm_pd0_pfn,
0358     .pfn_clear = gp100_vmm_pd0_pfn_clear,
0359     .pfn_unmap = gp100_vmm_pd0_pfn_unmap,
0360 };
0361 
0362 static void
0363 gp100_vmm_pd1_pde(struct nvkm_vmm *vmm, struct nvkm_vmm_pt *pgd, u32 pdei)
0364 {
0365     struct nvkm_vmm_pt *pgt = pgd->pde[pdei];
0366     struct nvkm_mmu_pt *pd = pgd->pt[0];
0367     u64 data = 0;
0368 
0369     if (!gp100_vmm_pde(pgt->pt[0], &data))
0370         return;
0371 
0372     nvkm_kmap(pd->memory);
0373     VMM_WO064(pd, vmm, pdei * 8, data);
0374     nvkm_done(pd->memory);
0375 }
0376 
0377 static const struct nvkm_vmm_desc_func
0378 gp100_vmm_desc_pd1 = {
0379     .unmap = gf100_vmm_pgt_unmap,
0380     .sparse = gp100_vmm_pgt_sparse,
0381     .pde = gp100_vmm_pd1_pde,
0382 };
0383 
0384 const struct nvkm_vmm_desc
0385 gp100_vmm_desc_16[] = {
0386     { LPT, 5,  8, 0x0100, &gp100_vmm_desc_lpt },
0387     { PGD, 8, 16, 0x1000, &gp100_vmm_desc_pd0 },
0388     { PGD, 9,  8, 0x1000, &gp100_vmm_desc_pd1 },
0389     { PGD, 9,  8, 0x1000, &gp100_vmm_desc_pd1 },
0390     { PGD, 2,  8, 0x1000, &gp100_vmm_desc_pd1 },
0391     {}
0392 };
0393 
0394 const struct nvkm_vmm_desc
0395 gp100_vmm_desc_12[] = {
0396     { SPT, 9,  8, 0x1000, &gp100_vmm_desc_spt },
0397     { PGD, 8, 16, 0x1000, &gp100_vmm_desc_pd0 },
0398     { PGD, 9,  8, 0x1000, &gp100_vmm_desc_pd1 },
0399     { PGD, 9,  8, 0x1000, &gp100_vmm_desc_pd1 },
0400     { PGD, 2,  8, 0x1000, &gp100_vmm_desc_pd1 },
0401     {}
0402 };
0403 
0404 int
0405 gp100_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc,
0406         struct nvkm_vmm_map *map)
0407 {
0408     const enum nvkm_memory_target target = nvkm_memory_target(map->memory);
0409     const struct nvkm_vmm_page *page = map->page;
0410     union {
0411         struct gp100_vmm_map_vn vn;
0412         struct gp100_vmm_map_v0 v0;
0413     } *args = argv;
0414     struct nvkm_device *device = vmm->mmu->subdev.device;
0415     struct nvkm_memory *memory = map->memory;
0416     u8  kind, kind_inv, priv, ro, vol;
0417     int kindn, aper, ret = -ENOSYS;
0418     const u8 *kindm;
0419 
0420     map->next = (1ULL << page->shift) >> 4;
0421     map->type = 0;
0422 
0423     if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
0424         vol  = !!args->v0.vol;
0425         ro   = !!args->v0.ro;
0426         priv = !!args->v0.priv;
0427         kind =   args->v0.kind;
0428     } else
0429     if (!(ret = nvif_unvers(ret, &argv, &argc, args->vn))) {
0430         vol  = target == NVKM_MEM_TARGET_HOST;
0431         ro   = 0;
0432         priv = 0;
0433         kind = 0x00;
0434     } else {
0435         VMM_DEBUG(vmm, "args");
0436         return ret;
0437     }
0438 
0439     aper = vmm->func->aper(target);
0440     if (WARN_ON(aper < 0))
0441         return aper;
0442 
0443     kindm = vmm->mmu->func->kind(vmm->mmu, &kindn, &kind_inv);
0444     if (kind >= kindn || kindm[kind] == kind_inv) {
0445         VMM_DEBUG(vmm, "kind %02x", kind);
0446         return -EINVAL;
0447     }
0448 
0449     if (kindm[kind] != kind) {
0450         u64 tags = nvkm_memory_size(memory) >> 16;
0451         if (aper != 0 || !(page->type & NVKM_VMM_PAGE_COMP)) {
0452             VMM_DEBUG(vmm, "comp %d %02x", aper, page->type);
0453             return -EINVAL;
0454         }
0455 
0456         ret = nvkm_memory_tags_get(memory, device, tags,
0457                        nvkm_ltc_tags_clear,
0458                        &map->tags);
0459         if (ret) {
0460             VMM_DEBUG(vmm, "comp %d", ret);
0461             return ret;
0462         }
0463 
0464         if (map->tags->mn) {
0465             tags = map->tags->mn->offset + (map->offset >> 16);
0466             map->ctag |= ((1ULL << page->shift) >> 16) << 36;
0467             map->type |= tags << 36;
0468             map->next |= map->ctag;
0469         } else {
0470             kind = kindm[kind];
0471         }
0472     }
0473 
0474     map->type |= BIT(0);
0475     map->type |= (u64)aper << 1;
0476     map->type |= (u64) vol << 3;
0477     map->type |= (u64)priv << 5;
0478     map->type |= (u64)  ro << 6;
0479     map->type |= (u64)kind << 56;
0480     return 0;
0481 }
0482 
0483 static int
0484 gp100_vmm_fault_cancel(struct nvkm_vmm *vmm, void *argv, u32 argc)
0485 {
0486     struct nvkm_device *device = vmm->mmu->subdev.device;
0487     union {
0488         struct gp100_vmm_fault_cancel_v0 v0;
0489     } *args = argv;
0490     int ret = -ENOSYS;
0491     u32 aper;
0492 
0493     if ((ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false)))
0494         return ret;
0495 
0496     /* Translate MaxwellFaultBufferA instance pointer to the same
0497      * format as the NV_GR_FECS_CURRENT_CTX register.
0498      */
0499     aper = (args->v0.inst >> 8) & 3;
0500     args->v0.inst >>= 12;
0501     args->v0.inst |= aper << 28;
0502     args->v0.inst |= 0x80000000;
0503 
0504     if (!WARN_ON(nvkm_gr_ctxsw_pause(device))) {
0505         if (nvkm_gr_ctxsw_inst(device) == args->v0.inst) {
0506             gf100_vmm_invalidate(vmm, 0x0000001b
0507                          /* CANCEL_TARGETED. */ |
0508                          (args->v0.hub    << 20) |
0509                          (args->v0.gpc    << 15) |
0510                          (args->v0.client << 9));
0511         }
0512         WARN_ON(nvkm_gr_ctxsw_resume(device));
0513     }
0514 
0515     return 0;
0516 }
0517 
0518 static int
0519 gp100_vmm_fault_replay(struct nvkm_vmm *vmm, void *argv, u32 argc)
0520 {
0521     union {
0522         struct gp100_vmm_fault_replay_vn vn;
0523     } *args = argv;
0524     int ret = -ENOSYS;
0525 
0526     if (!(ret = nvif_unvers(ret, &argv, &argc, args->vn))) {
0527         gf100_vmm_invalidate(vmm, 0x0000000b); /* REPLAY_GLOBAL. */
0528     }
0529 
0530     return ret;
0531 }
0532 
0533 int
0534 gp100_vmm_mthd(struct nvkm_vmm *vmm,
0535            struct nvkm_client *client, u32 mthd, void *argv, u32 argc)
0536 {
0537     switch (mthd) {
0538     case GP100_VMM_VN_FAULT_REPLAY:
0539         return gp100_vmm_fault_replay(vmm, argv, argc);
0540     case GP100_VMM_VN_FAULT_CANCEL:
0541         return gp100_vmm_fault_cancel(vmm, argv, argc);
0542     default:
0543         break;
0544     }
0545     return -EINVAL;
0546 }
0547 
0548 void
0549 gp100_vmm_invalidate_pdb(struct nvkm_vmm *vmm, u64 addr)
0550 {
0551     struct nvkm_device *device = vmm->mmu->subdev.device;
0552     nvkm_wr32(device, 0x100cb8, lower_32_bits(addr));
0553     nvkm_wr32(device, 0x100cec, upper_32_bits(addr));
0554 }
0555 
0556 void
0557 gp100_vmm_flush(struct nvkm_vmm *vmm, int depth)
0558 {
0559     u32 type = (5 /* CACHE_LEVEL_UP_TO_PDE3 */ - depth) << 24;
0560     if (atomic_read(&vmm->engref[NVKM_SUBDEV_BAR]))
0561         type |= 0x00000004; /* HUB_ONLY */
0562     type |= 0x00000001; /* PAGE_ALL */
0563     gf100_vmm_invalidate(vmm, type);
0564 }
0565 
0566 int
0567 gp100_vmm_join(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
0568 {
0569     u64 base = BIT_ULL(10) /* VER2 */ | BIT_ULL(11) /* 64KiB */;
0570     if (vmm->replay) {
0571         base |= BIT_ULL(4); /* FAULT_REPLAY_TEX */
0572         base |= BIT_ULL(5); /* FAULT_REPLAY_GCC */
0573     }
0574     return gf100_vmm_join_(vmm, inst, base);
0575 }
0576 
0577 static const struct nvkm_vmm_func
0578 gp100_vmm = {
0579     .join = gp100_vmm_join,
0580     .part = gf100_vmm_part,
0581     .aper = gf100_vmm_aper,
0582     .valid = gp100_vmm_valid,
0583     .flush = gp100_vmm_flush,
0584     .mthd = gp100_vmm_mthd,
0585     .invalidate_pdb = gp100_vmm_invalidate_pdb,
0586     .page = {
0587         { 47, &gp100_vmm_desc_16[4], NVKM_VMM_PAGE_Sxxx },
0588         { 38, &gp100_vmm_desc_16[3], NVKM_VMM_PAGE_Sxxx },
0589         { 29, &gp100_vmm_desc_16[2], NVKM_VMM_PAGE_Sxxx },
0590         { 21, &gp100_vmm_desc_16[1], NVKM_VMM_PAGE_SVxC },
0591         { 16, &gp100_vmm_desc_16[0], NVKM_VMM_PAGE_SVxC },
0592         { 12, &gp100_vmm_desc_12[0], NVKM_VMM_PAGE_SVHx },
0593         {}
0594     }
0595 };
0596 
0597 int
0598 gp100_vmm_new_(const struct nvkm_vmm_func *func,
0599            struct nvkm_mmu *mmu, bool managed, u64 addr, u64 size,
0600            void *argv, u32 argc, struct lock_class_key *key,
0601            const char *name, struct nvkm_vmm **pvmm)
0602 {
0603     union {
0604         struct gp100_vmm_vn vn;
0605         struct gp100_vmm_v0 v0;
0606     } *args = argv;
0607     int ret = -ENOSYS;
0608     bool replay;
0609 
0610     if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
0611         replay = args->v0.fault_replay != 0;
0612     } else
0613     if (!(ret = nvif_unvers(ret, &argv, &argc, args->vn))) {
0614         replay = false;
0615     } else
0616         return ret;
0617 
0618     ret = nvkm_vmm_new_(func, mmu, 0, managed, addr, size, key, name, pvmm);
0619     if (ret)
0620         return ret;
0621 
0622     (*pvmm)->replay = replay;
0623     return 0;
0624 }
0625 
0626 int
0627 gp100_vmm_new(struct nvkm_mmu *mmu, bool managed, u64 addr, u64 size,
0628           void *argv, u32 argc, struct lock_class_key *key,
0629           const char *name, struct nvkm_vmm **pvmm)
0630 {
0631     return gp100_vmm_new_(&gp100_vmm, mmu, managed, addr, size,
0632                   argv, argc, key, name, pvmm);
0633 }
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